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/*
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* QEMU Sun4m & Sun4d & Sun4c System Emulator
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authored
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*
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* Copyright ( c ) 2003 - 2005 Fabrice Bellard
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authored
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*
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* Permission is hereby granted , free of charge , to any person obtaining a copy
* of this software and associated documentation files ( the "Software" ), to deal
* in the Software without restriction , including without limitation the rights
* to use , copy , modify , merge , publish , distribute , sublicense , and / or sell
* copies of the Software , and to permit persons to whom the Software is
* furnished to do so , subject to the following conditions :
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software .
*
* THE SOFTWARE IS PROVIDED "AS IS" , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR
* IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY ,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM , DAMAGES OR OTHER
* LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , ARISING FROM ,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE .
*/
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# include "hw.h"
# include "qemu-timer.h"
# include "sun4m.h"
# include "nvram.h"
# include "sparc32_dma.h"
# include "fdc.h"
# include "sysemu.h"
# include "net.h"
# include "boards.h"
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# include "firmware_abi.h"
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# include "scsi.h"
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# include "pc.h"
# include "isa.h"
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// # define DEBUG_IRQ
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/*
* Sun4m architecture was used in the following machines :
*
* SPARCserver 6 xxMP / xx
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* SPARCclassic ( SPARCclassic Server )( SPARCstation LC ) ( 4 / 15 ),
* SPARCclassic X ( 4 / 10 )
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* SPARCstation LX / ZX ( 4 / 30 )
* SPARCstation Voyager
* SPARCstation 10 / xx , SPARCserver 10 / xx
* SPARCstation 5 , SPARCserver 5
* SPARCstation 20 / xx , SPARCserver 20
* SPARCstation 4
*
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* Sun4d architecture was used in the following machines :
*
* SPARCcenter 2000
* SPARCserver 1000
*
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* Sun4c architecture was used in the following machines :
* SPARCstation 1 / 1 + , SPARCserver 1 / 1 +
* SPARCstation SLC
* SPARCstation IPC
* SPARCstation ELC
* SPARCstation IPX
*
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* See for example : http :// www . sunhelp . org / faq / sunref1 . html
*/
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# ifdef DEBUG_IRQ
# define DPRINTF ( fmt , args ...) \
do { printf ( "CPUIRQ: " fmt , ## args ); } while ( 0 )
# else
# define DPRINTF ( fmt , args ...)
# endif
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# define KERNEL_LOAD_ADDR 0x00004000
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# define CMDLINE_ADDR 0x007ff000
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# define INITRD_LOAD_ADDR 0x00800000
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# define PROM_SIZE_MAX ( 512 * 1024 )
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# define PROM_VADDR 0xffd00000
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# define PROM_FILENAME "openbios-sparc32"
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// Control plane , 8 - bit and 24 - bit planes
# define TCX_SIZE ( 9 * 1024 * 1024 )
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# define MAX_CPUS 16
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# define MAX_PILS 16
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struct hwdef {
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target_phys_addr_t iommu_base , slavio_base ;
target_phys_addr_t intctl_base , counter_base , nvram_base , ms_kb_base ;
target_phys_addr_t serial_base , fd_base ;
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target_phys_addr_t idreg_base , dma_base , esp_base , le_base ;
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target_phys_addr_t tcx_base , cs_base , apc_base , aux1_base , aux2_base ;
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target_phys_addr_t ecc_base ;
uint32_t ecc_version ;
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target_phys_addr_t sun4c_intctl_base , sun4c_counter_base ;
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long vram_size , nvram_size ;
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// IRQ numbers are not PIL ones , but master interrupt controller
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// register bit numbers
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int intctl_g_intr , esp_irq , le_irq , clock_irq , clock1_irq ;
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int ser_irq , ms_kb_irq , fd_irq , me_irq , cs_irq , ecc_irq ;
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int machine_id ; // For NVRAM
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uint32_t iommu_version ;
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uint32_t intbit_to_level [ 32 ];
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uint64_t max_mem ;
const char * const default_cpu_model ;
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};
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# define MAX_IOUNITS 5
struct sun4d_hwdef {
target_phys_addr_t iounit_bases [ MAX_IOUNITS ], slavio_base ;
target_phys_addr_t counter_base , nvram_base , ms_kb_base ;
target_phys_addr_t serial_base ;
target_phys_addr_t espdma_base , esp_base ;
target_phys_addr_t ledma_base , le_base ;
target_phys_addr_t tcx_base ;
target_phys_addr_t sbi_base ;
unsigned long vram_size , nvram_size ;
// IRQ numbers are not PIL ones , but SBI register bit numbers
int esp_irq , le_irq , clock_irq , clock1_irq ;
int ser_irq , ms_kb_irq , me_irq ;
int machine_id ; // For NVRAM
uint32_t iounit_version ;
uint64_t max_mem ;
const char * const default_cpu_model ;
};
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int DMA_get_channel_mode ( int nchan )
{
return 0 ;
}
int DMA_read_memory ( int nchan , void * buf , int pos , int size )
{
return 0 ;
}
int DMA_write_memory ( int nchan , void * buf , int pos , int size )
{
return 0 ;
}
void DMA_hold_DREQ ( int nchan ) {}
void DMA_release_DREQ ( int nchan ) {}
void DMA_schedule ( int nchan ) {}
void DMA_run ( void ) {}
void DMA_init ( int high_page_enable ) {}
void DMA_register_channel ( int nchan ,
DMA_transfer_handler transfer_handler ,
void * opaque )
{
}
extern int nographic ;
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static void nvram_init ( m48t59_t * nvram , uint8_t * macaddr , const char * cmdline ,
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const char * boot_devices , ram_addr_t RAM_size ,
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uint32_t kernel_size ,
int width , int height , int depth ,
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int machine_id , const char * arch )
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{
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unsigned int i ;
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uint32_t start , end ;
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uint8_t image [ 0x1ff0 ];
ohwcfg_v3_t * header = ( ohwcfg_v3_t * ) & image ;
struct sparc_arch_cfg * sparc_header ;
struct OpenBIOS_nvpart_v1 * part_header ;
memset ( image , '\0' , sizeof ( image ));
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// Try to match PPC NVRAM
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strcpy ( header -> struct_ident , "QEMU_BIOS" );
header -> struct_version = cpu_to_be32 ( 3 ); /* structure v3 */
header -> nvram_size = cpu_to_be16 ( 0x2000 );
header -> nvram_arch_ptr = cpu_to_be16 ( sizeof ( ohwcfg_v3_t ));
header -> nvram_arch_size = cpu_to_be16 ( sizeof ( struct sparc_arch_cfg ));
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strcpy ( header -> arch , arch );
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header -> nb_cpus = smp_cpus & 0xff ;
header -> RAM0_base = 0 ;
header -> RAM0_size = cpu_to_be64 (( uint64_t ) RAM_size );
strcpy ( header -> boot_devices , boot_devices );
header -> nboot_devices = strlen ( boot_devices ) & 0xff ;
header -> kernel_image = cpu_to_be64 (( uint64_t ) KERNEL_LOAD_ADDR );
header -> kernel_size = cpu_to_be64 (( uint64_t ) kernel_size );
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if ( cmdline ) {
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pstrcpy_targphys ( CMDLINE_ADDR , TARGET_PAGE_SIZE , cmdline );
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header -> cmdline = cpu_to_be64 (( uint64_t ) CMDLINE_ADDR );
header -> cmdline_size = cpu_to_be64 (( uint64_t ) strlen ( cmdline ));
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}
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// XXX add initrd_image , initrd_size
header -> width = cpu_to_be16 ( width );
header -> height = cpu_to_be16 ( height );
header -> depth = cpu_to_be16 ( depth );
if ( nographic )
header -> graphic_flags = cpu_to_be16 ( OHW_GF_NOGRAPHICS );
header -> crc = cpu_to_be16 ( OHW_compute_crc ( header , 0x00 , 0xF8 ));
// Architecture specific header
start = sizeof ( ohwcfg_v3_t );
sparc_header = ( struct sparc_arch_cfg * ) & image [ start ];
sparc_header -> valid = 0 ;
start += sizeof ( struct sparc_arch_cfg );
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// OpenBIOS nvram variables
// Variable partition
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part_header = ( struct OpenBIOS_nvpart_v1 * ) & image [ start ];
part_header -> signature = OPENBIOS_PART_SYSTEM ;
strcpy ( part_header -> name , "system" );
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end = start + sizeof ( struct OpenBIOS_nvpart_v1 );
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for ( i = 0 ; i < nb_prom_envs ; i ++ )
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end = OpenBIOS_set_var ( image , end , prom_envs [ i ]);
// End marker
image [ end ++ ] = '\0' ;
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end = start + (( end - start + 15 ) & ~ 15 );
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OpenBIOS_finish_partition ( part_header , end - start );
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// free partition
start = end ;
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part_header = ( struct OpenBIOS_nvpart_v1 * ) & image [ start ];
part_header -> signature = OPENBIOS_PART_FREE ;
strcpy ( part_header -> name , "free" );
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end = 0x1fd0 ;
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OpenBIOS_finish_partition ( part_header , end - start );
Sun_init_header (( struct Sun_nvram * ) & image [ 0x1fd8 ], macaddr , machine_id );
for ( i = 0 ; i < sizeof ( image ); i ++ )
m48t59_write ( nvram , i , image [ i ]);
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}
static void * slavio_intctl ;
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void pic_info ( void )
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{
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if ( slavio_intctl )
slavio_pic_info ( slavio_intctl );
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}
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void irq_info ( void )
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{
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if ( slavio_intctl )
slavio_irq_info ( slavio_intctl );
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}
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void cpu_check_irqs ( CPUState * env )
{
if ( env -> pil_in && ( env -> interrupt_index == 0 ||
( env -> interrupt_index & ~ 15 ) == TT_EXTINT )) {
unsigned int i ;
for ( i = 15 ; i > 0 ; i -- ) {
if ( env -> pil_in & ( 1 << i )) {
int old_interrupt = env -> interrupt_index ;
env -> interrupt_index = TT_EXTINT | i ;
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if ( old_interrupt != env -> interrupt_index ) {
DPRINTF ( "Set CPU IRQ %d \n " , i );
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cpu_interrupt ( env , CPU_INTERRUPT_HARD );
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}
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break ;
}
}
} else if ( ! env -> pil_in && ( env -> interrupt_index & ~ 15 ) == TT_EXTINT ) {
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DPRINTF ( "Reset CPU IRQ %d \n " , env -> interrupt_index & 15 );
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env -> interrupt_index = 0 ;
cpu_reset_interrupt ( env , CPU_INTERRUPT_HARD );
}
}
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static void cpu_set_irq ( void * opaque , int irq , int level )
{
CPUState * env = opaque ;
if ( level ) {
DPRINTF ( "Raise CPU IRQ %d \n " , irq );
env -> halted = 0 ;
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env -> pil_in |= 1 << irq ;
cpu_check_irqs ( env );
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} else {
DPRINTF ( "Lower CPU IRQ %d \n " , irq );
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env -> pil_in &= ~ ( 1 << irq );
cpu_check_irqs ( env );
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}
}
static void dummy_cpu_set_irq ( void * opaque , int irq , int level )
{
}
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static void * slavio_misc ;
void qemu_system_powerdown ( void )
{
slavio_set_power_fail ( slavio_misc , 1 );
}
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static void main_cpu_reset ( void * opaque )
{
CPUState * env = opaque ;
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cpu_reset ( env );
env -> halted = 0 ;
}
static void secondary_cpu_reset ( void * opaque )
{
CPUState * env = opaque ;
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cpu_reset ( env );
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env -> halted = 1 ;
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}
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static unsigned long sun4m_load_kernel ( const char * kernel_filename ,
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const char * initrd_filename ,
ram_addr_t RAM_size )
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{
int linux_boot ;
unsigned int i ;
long initrd_size , kernel_size ;
linux_boot = ( kernel_filename != NULL );
kernel_size = 0 ;
if ( linux_boot ) {
kernel_size = load_elf ( kernel_filename , - 0xf0000000ULL , NULL , NULL ,
NULL );
if ( kernel_size < 0 )
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kernel_size = load_aout ( kernel_filename , KERNEL_LOAD_ADDR ,
RAM_size - KERNEL_LOAD_ADDR );
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if ( kernel_size < 0 )
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kernel_size = load_image_targphys ( kernel_filename ,
KERNEL_LOAD_ADDR ,
RAM_size - KERNEL_LOAD_ADDR );
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if ( kernel_size < 0 ) {
fprintf ( stderr , "qemu: could not load kernel '%s' \n " ,
kernel_filename );
exit ( 1 );
}
/* load initrd */
initrd_size = 0 ;
if ( initrd_filename ) {
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initrd_size = load_image_targphys ( initrd_filename ,
INITRD_LOAD_ADDR ,
RAM_size - INITRD_LOAD_ADDR );
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if ( initrd_size < 0 ) {
fprintf ( stderr , "qemu: could not load initial ram disk '%s' \n " ,
initrd_filename );
exit ( 1 );
}
}
if ( initrd_size > 0 ) {
for ( i = 0 ; i < 64 * TARGET_PAGE_SIZE ; i += TARGET_PAGE_SIZE ) {
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if ( ldl_phys ( KERNEL_LOAD_ADDR + i ) == 0x48647253 ) { // HdrS
stl_phys ( KERNEL_LOAD_ADDR + i + 16 , INITRD_LOAD_ADDR );
stl_phys ( KERNEL_LOAD_ADDR + i + 20 , initrd_size );
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break ;
}
}
}
}
return kernel_size ;
}
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static void sun4m_hw_init ( const struct hwdef * hwdef , ram_addr_t RAM_size ,
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const char * boot_device ,
DisplayState * ds , const char * kernel_filename ,
const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
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{
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CPUState * env , * envs [ MAX_CPUS ];
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unsigned int i ;
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void * iommu , * espdma , * ledma , * main_esp , * nvram ;
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qemu_irq * cpu_irqs [ MAX_CPUS ], * slavio_irq , * slavio_cpu_irq ,
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* espdma_irq , * ledma_irq ;
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qemu_irq * esp_reset , * le_reset ;
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qemu_irq * fdc_tc ;
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unsigned long prom_offset , kernel_size ;
int ret ;
char buf [ 1024 ];
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BlockDriverState * fd [ MAX_FD ];
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int drive_index ;
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/* init CPUs */
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if ( ! cpu_model )
cpu_model = hwdef -> default_cpu_model ;
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for ( i = 0 ; i < smp_cpus ; i ++ ) {
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env = cpu_init ( cpu_model );
if ( ! env ) {
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fprintf ( stderr , "qemu: Unable to find Sparc CPU definition \n " );
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exit ( 1 );
}
cpu_sparc_set_id ( env , i );
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envs [ i ] = env ;
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if ( i == 0 ) {
qemu_register_reset ( main_cpu_reset , env );
} else {
qemu_register_reset ( secondary_cpu_reset , env );
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env -> halted = 1 ;
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}
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register_savevm ( "cpu" , i , 3 , cpu_save , cpu_load , env );
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cpu_irqs [ i ] = qemu_allocate_irqs ( cpu_set_irq , envs [ i ], MAX_PILS );
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env -> prom_addr = hwdef -> slavio_base ;
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}
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for ( i = smp_cpus ; i < MAX_CPUS ; i ++ )
cpu_irqs [ i ] = qemu_allocate_irqs ( dummy_cpu_set_irq , NULL , MAX_PILS );
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/* allocate RAM */
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if (( uint64_t ) RAM_size > hwdef -> max_mem ) {
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fprintf ( stderr ,
"qemu: Too much memory for this machine: %d, maximum %d \n " ,
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( unsigned int )( RAM_size / ( 1024 * 1024 )),
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( unsigned int )( hwdef -> max_mem / ( 1024 * 1024 )));
exit ( 1 );
}
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cpu_register_physical_memory ( 0 , RAM_size , 0 );
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/* load boot prom */
prom_offset = RAM_size + hwdef -> vram_size ;
cpu_register_physical_memory ( hwdef -> slavio_base ,
( PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1 ) &
TARGET_PAGE_MASK ,
prom_offset | IO_MEM_ROM );
if ( bios_name == NULL )
bios_name = PROM_FILENAME ;
snprintf ( buf , sizeof ( buf ), "%s/%s" , bios_dir , bios_name );
ret = load_elf ( buf , hwdef -> slavio_base - PROM_VADDR , NULL , NULL , NULL );
if ( ret < 0 || ret > PROM_SIZE_MAX )
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ret = load_image_targphys ( buf , hwdef -> slavio_base , PROM_SIZE_MAX );
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if ( ret < 0 || ret > PROM_SIZE_MAX ) {
fprintf ( stderr , "qemu: could not load prom '%s' \n " ,
buf );
exit ( 1 );
}
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prom_offset += ( ret + TARGET_PAGE_SIZE - 1 ) & TARGET_PAGE_MASK ;
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/* set up devices */
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slavio_intctl = slavio_intctl_init ( hwdef -> intctl_base ,
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hwdef -> intctl_base + 0x10000ULL ,
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& hwdef -> intbit_to_level [ 0 ],
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& slavio_irq , & slavio_cpu_irq ,
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cpu_irqs ,
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hwdef -> clock_irq );
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if ( hwdef -> idreg_base != ( target_phys_addr_t ) - 1 ) {
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static const uint8_t idreg_data [] = { 0xfe , 0x81 , 0x01 , 0x03 };
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cpu_register_physical_memory ( hwdef -> idreg_base , sizeof ( idreg_data ),
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prom_offset | IO_MEM_ROM );
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cpu_physical_memory_write_rom ( hwdef -> idreg_base , idreg_data ,
sizeof ( idreg_data ));
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}
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iommu = iommu_init ( hwdef -> iommu_base , hwdef -> iommu_version ,
slavio_irq [ hwdef -> me_irq ]);
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espdma = sparc32_dma_init ( hwdef -> dma_base , slavio_irq [ hwdef -> esp_irq ],
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iommu , & espdma_irq , & esp_reset );
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ledma = sparc32_dma_init ( hwdef -> dma_base + 16ULL ,
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slavio_irq [ hwdef -> le_irq ], iommu , & ledma_irq ,
& le_reset );
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if ( graphic_depth != 8 && graphic_depth != 24 ) {
fprintf ( stderr , "qemu: Unsupported depth: %d \n " , graphic_depth );
exit ( 1 );
}
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tcx_init ( ds , hwdef -> tcx_base , phys_ram_base + RAM_size , RAM_size ,
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hwdef -> vram_size , graphic_width , graphic_height , graphic_depth );
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if ( nd_table [ 0 ]. model == NULL
|| strcmp ( nd_table [ 0 ]. model , "lance" ) == 0 ) {
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lance_init ( & nd_table [ 0 ], hwdef -> le_base , ledma , * ledma_irq , le_reset );
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} else if ( strcmp ( nd_table [ 0 ]. model , "?" ) == 0 ) {
fprintf ( stderr , "qemu: Supported NICs: lance \n " );
exit ( 1 );
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} else {
fprintf ( stderr , "qemu: Unsupported NIC: %s \n " , nd_table [ 0 ]. model );
exit ( 1 );
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}
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nvram = m48t59_init ( slavio_irq [ 0 ], hwdef -> nvram_base , 0 ,
hwdef -> nvram_size , 8 );
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slavio_timer_init_all ( hwdef -> counter_base , slavio_irq [ hwdef -> clock1_irq ],
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slavio_cpu_irq , smp_cpus );
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slavio_serial_ms_kbd_init ( hwdef -> ms_kb_base , slavio_irq [ hwdef -> ms_kb_irq ],
nographic );
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// Slavio TTYA ( base + 4 , Linux ttyS0 ) is the first Qemu serial device
// Slavio TTYB ( base + 0 , Linux ttyS1 ) is the second Qemu serial device
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slavio_serial_init ( hwdef -> serial_base , slavio_irq [ hwdef -> ser_irq ],
serial_hds [ 1 ], serial_hds [ 0 ]);
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slavio_misc = slavio_misc_init ( hwdef -> slavio_base , hwdef -> apc_base ,
hwdef -> aux1_base , hwdef -> aux2_base ,
slavio_irq [ hwdef -> me_irq ], envs [ 0 ],
& fdc_tc );
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if ( hwdef -> fd_base != ( target_phys_addr_t ) - 1 ) {
/* there is zero or one floppy drive */
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memset ( fd , 0 , sizeof ( fd ));
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drive_index = drive_get_index ( IF_FLOPPY , 0 , 0 );
if ( drive_index != - 1 )
fd [ 0 ] = drives_table [ drive_index ]. bdrv ;
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sun4m_fdctrl_init ( slavio_irq [ hwdef -> fd_irq ], hwdef -> fd_base , fd ,
fdc_tc );
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}
if ( drive_get_max_bus ( IF_SCSI ) > 0 ) {
fprintf ( stderr , "qemu: too many SCSI bus \n " );
exit ( 1 );
}
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main_esp = esp_init ( hwdef -> esp_base , 2 ,
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espdma_memory_read , espdma_memory_write ,
espdma , * espdma_irq , esp_reset );
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for ( i = 0 ; i < ESP_MAX_DEVS ; i ++ ) {
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drive_index = drive_get_index ( IF_SCSI , 0 , i );
if ( drive_index == - 1 )
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continue ;
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esp_scsi_attach ( main_esp , drives_table [ drive_index ]. bdrv , i );
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}
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if ( hwdef -> cs_base != ( target_phys_addr_t ) - 1 )
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cs_init ( hwdef -> cs_base , hwdef -> cs_irq , slavio_intctl );
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kernel_size = sun4m_load_kernel ( kernel_filename , initrd_filename ,
RAM_size );
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nvram_init ( nvram , ( uint8_t * ) & nd_table [ 0 ]. macaddr , kernel_cmdline ,
543
boot_device , RAM_size , kernel_size , graphic_width ,
544
graphic_height , graphic_depth , hwdef -> machine_id , "Sun4m" );
545
546
if ( hwdef -> ecc_base != ( target_phys_addr_t ) - 1 )
547
548
ecc_init ( hwdef -> ecc_base , slavio_irq [ hwdef -> ecc_irq ],
hwdef -> ecc_version );
549
550
}
551
static void sun4c_hw_init ( const struct hwdef * hwdef , ram_addr_t RAM_size ,
552
553
554
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560
561
const char * boot_device ,
DisplayState * ds , const char * kernel_filename ,
const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
CPUState * env ;
unsigned int i ;
void * iommu , * espdma , * ledma , * main_esp , * nvram ;
qemu_irq * cpu_irqs , * slavio_irq , * espdma_irq , * ledma_irq ;
qemu_irq * esp_reset , * le_reset ;
562
qemu_irq * fdc_tc ;
563
564
565
566
unsigned long prom_offset , kernel_size ;
int ret ;
char buf [ 1024 ];
BlockDriverState * fd [ MAX_FD ];
567
int drive_index ;
568
569
570
571
572
573
574
/* init CPU */
if ( ! cpu_model )
cpu_model = hwdef -> default_cpu_model ;
env = cpu_init ( cpu_model );
if ( ! env ) {
575
fprintf ( stderr , "qemu: Unable to find Sparc CPU definition \n " );
576
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579
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581
582
583
exit ( 1 );
}
cpu_sparc_set_id ( env , 0 );
qemu_register_reset ( main_cpu_reset , env );
register_savevm ( "cpu" , 0 , 3 , cpu_save , cpu_load , env );
cpu_irqs = qemu_allocate_irqs ( cpu_set_irq , env , MAX_PILS );
584
env -> prom_addr = hwdef -> slavio_base ;
585
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587
/* allocate RAM */
if (( uint64_t ) RAM_size > hwdef -> max_mem ) {
588
589
fprintf ( stderr ,
"qemu: Too much memory for this machine: %d, maximum %d \n " ,
590
591
( unsigned int )( RAM_size / ( 1024 * 1024 )),
( unsigned int )( hwdef -> max_mem / ( 1024 * 1024 )));
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607
exit ( 1 );
}
cpu_register_physical_memory ( 0 , RAM_size , 0 );
/* load boot prom */
prom_offset = RAM_size + hwdef -> vram_size ;
cpu_register_physical_memory ( hwdef -> slavio_base ,
( PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1 ) &
TARGET_PAGE_MASK ,
prom_offset | IO_MEM_ROM );
if ( bios_name == NULL )
bios_name = PROM_FILENAME ;
snprintf ( buf , sizeof ( buf ), "%s/%s" , bios_dir , bios_name );
ret = load_elf ( buf , hwdef -> slavio_base - PROM_VADDR , NULL , NULL , NULL );
if ( ret < 0 || ret > PROM_SIZE_MAX )
608
ret = load_image_targphys ( buf , hwdef -> slavio_base , PROM_SIZE_MAX );
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619
if ( ret < 0 || ret > PROM_SIZE_MAX ) {
fprintf ( stderr , "qemu: could not load prom '%s' \n " ,
buf );
exit ( 1 );
}
prom_offset += ( ret + TARGET_PAGE_SIZE - 1 ) & TARGET_PAGE_MASK ;
/* set up devices */
slavio_intctl = sun4c_intctl_init ( hwdef -> sun4c_intctl_base ,
& slavio_irq , cpu_irqs );
620
621
iommu = iommu_init ( hwdef -> iommu_base , hwdef -> iommu_version ,
slavio_irq [ hwdef -> me_irq ]);
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espdma = sparc32_dma_init ( hwdef -> dma_base , slavio_irq [ hwdef -> esp_irq ],
iommu , & espdma_irq , & esp_reset );
ledma = sparc32_dma_init ( hwdef -> dma_base + 16ULL ,
slavio_irq [ hwdef -> le_irq ], iommu , & ledma_irq ,
& le_reset );
if ( graphic_depth != 8 && graphic_depth != 24 ) {
fprintf ( stderr , "qemu: Unsupported depth: %d \n " , graphic_depth );
exit ( 1 );
}
tcx_init ( ds , hwdef -> tcx_base , phys_ram_base + RAM_size , RAM_size ,
hwdef -> vram_size , graphic_width , graphic_height , graphic_depth );
if ( nd_table [ 0 ]. model == NULL
|| strcmp ( nd_table [ 0 ]. model , "lance" ) == 0 ) {
lance_init ( & nd_table [ 0 ], hwdef -> le_base , ledma , * ledma_irq , le_reset );
} else if ( strcmp ( nd_table [ 0 ]. model , "?" ) == 0 ) {
fprintf ( stderr , "qemu: Supported NICs: lance \n " );
exit ( 1 );
} else {
fprintf ( stderr , "qemu: Unsupported NIC: %s \n " , nd_table [ 0 ]. model );
exit ( 1 );
}
nvram = m48t59_init ( slavio_irq [ 0 ], hwdef -> nvram_base , 0 ,
649
hwdef -> nvram_size , 2 );
650
651
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654
655
656
657
slavio_serial_ms_kbd_init ( hwdef -> ms_kb_base , slavio_irq [ hwdef -> ms_kb_irq ],
nographic );
// Slavio TTYA ( base + 4 , Linux ttyS0 ) is the first Qemu serial device
// Slavio TTYB ( base + 0 , Linux ttyS1 ) is the second Qemu serial device
slavio_serial_init ( hwdef -> serial_base , slavio_irq [ hwdef -> ser_irq ],
serial_hds [ 1 ], serial_hds [ 0 ]);
658
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661
slavio_misc = slavio_misc_init ( - 1 , hwdef -> apc_base ,
hwdef -> aux1_base , hwdef -> aux2_base ,
slavio_irq [ hwdef -> me_irq ], env , & fdc_tc );
662
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664
if ( hwdef -> fd_base != ( target_phys_addr_t ) - 1 ) {
/* there is zero or one floppy drive */
fd [ 1 ] = fd [ 0 ] = NULL ;
665
666
667
drive_index = drive_get_index ( IF_FLOPPY , 0 , 0 );
if ( drive_index != - 1 )
fd [ 0 ] = drives_table [ drive_index ]. bdrv ;
668
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sun4m_fdctrl_init ( slavio_irq [ hwdef -> fd_irq ], hwdef -> fd_base , fd ,
fdc_tc );
671
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677
}
if ( drive_get_max_bus ( IF_SCSI ) > 0 ) {
fprintf ( stderr , "qemu: too many SCSI bus \n " );
exit ( 1 );
}
678
main_esp = esp_init ( hwdef -> esp_base , 2 ,
679
680
espdma_memory_read , espdma_memory_write ,
espdma , * espdma_irq , esp_reset );
681
682
for ( i = 0 ; i < ESP_MAX_DEVS ; i ++ ) {
683
684
drive_index = drive_get_index ( IF_SCSI , 0 , i );
if ( drive_index == - 1 )
685
continue ;
686
esp_scsi_attach ( main_esp , drives_table [ drive_index ]. bdrv , i );
687
688
}
689
690
kernel_size = sun4m_load_kernel ( kernel_filename , initrd_filename ,
RAM_size );
691
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693
694
695
696
nvram_init ( nvram , ( uint8_t * ) & nd_table [ 0 ]. macaddr , kernel_cmdline ,
boot_device , RAM_size , kernel_size , graphic_width ,
graphic_height , graphic_depth , hwdef -> machine_id , "Sun4c" );
}
697
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700
701
702
static const struct hwdef hwdefs [] = {
/* SS-5 */
{
. iommu_base = 0x10000000 ,
. tcx_base = 0x50000000 ,
. cs_base = 0x6c000000 ,
703
. slavio_base = 0x70000000 ,
704
705
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708
709
. ms_kb_base = 0x71000000 ,
. serial_base = 0x71100000 ,
. nvram_base = 0x71200000 ,
. fd_base = 0x71400000 ,
. counter_base = 0x71d00000 ,
. intctl_base = 0x71e00000 ,
710
. idreg_base = 0x78000000 ,
711
712
713
. dma_base = 0x78400000 ,
. esp_base = 0x78800000 ,
. le_base = 0x78c00000 ,
714
. apc_base = 0x6a000000 ,
715
716
. aux1_base = 0x71900000 ,
. aux2_base = 0x71910000 ,
717
. ecc_base = - 1 ,
718
719
. sun4c_intctl_base = - 1 ,
. sun4c_counter_base = - 1 ,
720
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722
723
. vram_size = 0x00100000 ,
. nvram_size = 0x2000 ,
. esp_irq = 18 ,
. le_irq = 16 ,
724
. clock_irq = 7 ,
725
726
727
728
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730
731
. clock1_irq = 19 ,
. ms_kb_irq = 14 ,
. ser_irq = 15 ,
. fd_irq = 22 ,
. me_irq = 30 ,
. cs_irq = 5 ,
. machine_id = 0x80 ,
732
. iommu_version = 0x05000000 ,
733
. intbit_to_level = {
734
735
2 , 3 , 5 , 7 , 9 , 11 , 0 , 14 , 3 , 5 , 7 , 9 , 11 , 13 , 12 , 12 ,
6 , 0 , 4 , 10 , 8 , 0 , 11 , 0 , 0 , 0 , 0 , 0 , 15 , 0 , 15 , 0 ,
736
},
737
738
. max_mem = 0x10000000 ,
. default_cpu_model = "Fujitsu MB86904" ,
739
740
741
},
/* SS-10 */
{
742
743
. iommu_base = 0xfe0000000ULL ,
. tcx_base = 0xe20000000ULL ,
744
. cs_base = - 1 ,
745
746
747
748
749
750
751
. slavio_base = 0xff0000000ULL ,
. ms_kb_base = 0xff1000000ULL ,
. serial_base = 0xff1100000ULL ,
. nvram_base = 0xff1200000ULL ,
. fd_base = 0xff1700000ULL ,
. counter_base = 0xff1300000ULL ,
. intctl_base = 0xff1400000ULL ,
752
. idreg_base = 0xef0000000ULL ,
753
754
755
. dma_base = 0xef0400000ULL ,
. esp_base = 0xef0800000ULL ,
. le_base = 0xef0c00000ULL ,
756
. apc_base = 0xefa000000ULL , // XXX should not exist
757
758
. aux1_base = 0xff1800000ULL ,
. aux2_base = 0xff1a01000ULL ,
759
760
. ecc_base = 0xf00000000ULL ,
. ecc_version = 0x10000000 , // version 0 , implementation 1
761
762
. sun4c_intctl_base = - 1 ,
. sun4c_counter_base = - 1 ,
763
764
765
766
. vram_size = 0x00100000 ,
. nvram_size = 0x2000 ,
. esp_irq = 18 ,
. le_irq = 16 ,
767
. clock_irq = 7 ,
768
769
770
771
772
. clock1_irq = 19 ,
. ms_kb_irq = 14 ,
. ser_irq = 15 ,
. fd_irq = 22 ,
. me_irq = 30 ,
773
. cs_irq = - 1 ,
774
. ecc_irq = 28 ,
775
. machine_id = 0x72 ,
776
. iommu_version = 0x03000000 ,
777
. intbit_to_level = {
778
779
2 , 3 , 5 , 7 , 9 , 11 , 0 , 14 , 3 , 5 , 7 , 9 , 11 , 13 , 12 , 12 ,
6 , 0 , 4 , 10 , 8 , 0 , 11 , 0 , 0 , 0 , 0 , 0 , 15 , 0 , 15 , 0 ,
780
},
781
. max_mem = 0xf00000000ULL ,
782
. default_cpu_model = "TI SuperSparc II" ,
783
},
784
785
786
787
788
789
790
791
792
793
794
795
/* SS-600MP */
{
. iommu_base = 0xfe0000000ULL ,
. tcx_base = 0xe20000000ULL ,
. cs_base = - 1 ,
. slavio_base = 0xff0000000ULL ,
. ms_kb_base = 0xff1000000ULL ,
. serial_base = 0xff1100000ULL ,
. nvram_base = 0xff1200000ULL ,
. fd_base = - 1 ,
. counter_base = 0xff1300000ULL ,
. intctl_base = 0xff1400000ULL ,
796
. idreg_base = - 1 ,
797
798
799
. dma_base = 0xef0081000ULL ,
. esp_base = 0xef0080000ULL ,
. le_base = 0xef0060000ULL ,
800
. apc_base = 0xefa000000ULL , // XXX should not exist
801
802
. aux1_base = 0xff1800000ULL ,
. aux2_base = 0xff1a01000ULL , // XXX should not exist
803
804
. ecc_base = 0xf00000000ULL ,
. ecc_version = 0x00000000 , // version 0 , implementation 0
805
806
. sun4c_intctl_base = - 1 ,
. sun4c_counter_base = - 1 ,
807
808
809
810
. vram_size = 0x00100000 ,
. nvram_size = 0x2000 ,
. esp_irq = 18 ,
. le_irq = 16 ,
811
. clock_irq = 7 ,
812
813
814
815
816
817
. clock1_irq = 19 ,
. ms_kb_irq = 14 ,
. ser_irq = 15 ,
. fd_irq = 22 ,
. me_irq = 30 ,
. cs_irq = - 1 ,
818
. ecc_irq = 28 ,
819
. machine_id = 0x71 ,
820
. iommu_version = 0x01000000 ,
821
822
823
824
. intbit_to_level = {
2 , 3 , 5 , 7 , 9 , 11 , 0 , 14 , 3 , 5 , 7 , 9 , 11 , 13 , 12 , 12 ,
6 , 0 , 4 , 10 , 8 , 0 , 11 , 0 , 0 , 0 , 0 , 0 , 15 , 0 , 15 , 0 ,
},
825
. max_mem = 0xf00000000ULL ,
826
. default_cpu_model = "TI SuperSparc II" ,
827
},
828
829
830
831
832
833
834
835
836
837
838
839
/* SS-20 */
{
. iommu_base = 0xfe0000000ULL ,
. tcx_base = 0xe20000000ULL ,
. cs_base = - 1 ,
. slavio_base = 0xff0000000ULL ,
. ms_kb_base = 0xff1000000ULL ,
. serial_base = 0xff1100000ULL ,
. nvram_base = 0xff1200000ULL ,
. fd_base = 0xff1700000ULL ,
. counter_base = 0xff1300000ULL ,
. intctl_base = 0xff1400000ULL ,
840
. idreg_base = 0xef0000000ULL ,
841
842
843
. dma_base = 0xef0400000ULL ,
. esp_base = 0xef0800000ULL ,
. le_base = 0xef0c00000ULL ,
844
. apc_base = 0xefa000000ULL , // XXX should not exist
845
846
. aux1_base = 0xff1800000ULL ,
. aux2_base = 0xff1a01000ULL ,
847
848
. ecc_base = 0xf00000000ULL ,
. ecc_version = 0x20000000 , // version 0 , implementation 2
849
850
. sun4c_intctl_base = - 1 ,
. sun4c_counter_base = - 1 ,
851
852
853
854
. vram_size = 0x00100000 ,
. nvram_size = 0x2000 ,
. esp_irq = 18 ,
. le_irq = 16 ,
855
. clock_irq = 7 ,
856
857
858
859
860
861
. clock1_irq = 19 ,
. ms_kb_irq = 14 ,
. ser_irq = 15 ,
. fd_irq = 22 ,
. me_irq = 30 ,
. cs_irq = - 1 ,
862
. ecc_irq = 28 ,
863
864
865
866
867
868
. machine_id = 0x72 ,
. iommu_version = 0x13000000 ,
. intbit_to_level = {
2 , 3 , 5 , 7 , 9 , 11 , 0 , 14 , 3 , 5 , 7 , 9 , 11 , 13 , 12 , 12 ,
6 , 0 , 4 , 10 , 8 , 0 , 11 , 0 , 0 , 0 , 0 , 0 , 15 , 0 , 15 , 0 ,
},
869
. max_mem = 0xf00000000ULL ,
870
871
. default_cpu_model = "TI SuperSparc II" ,
},
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
/* SS-2 */
{
. iommu_base = 0xf8000000 ,
. tcx_base = 0xfe000000 ,
. cs_base = - 1 ,
. slavio_base = 0xf6000000 ,
. ms_kb_base = 0xf0000000 ,
. serial_base = 0xf1000000 ,
. nvram_base = 0xf2000000 ,
. fd_base = 0xf7200000 ,
. counter_base = - 1 ,
. intctl_base = - 1 ,
. dma_base = 0xf8400000 ,
. esp_base = 0xf8800000 ,
. le_base = 0xf8c00000 ,
887
888
889
. apc_base = - 1 ,
. aux1_base = 0xf7400003 ,
. aux2_base = - 1 ,
890
891
892
. sun4c_intctl_base = 0xf5000000 ,
. sun4c_counter_base = 0xf3000000 ,
. vram_size = 0x00100000 ,
893
. nvram_size = 0x800 ,
894
895
896
897
898
899
900
901
902
903
904
905
906
. esp_irq = 2 ,
. le_irq = 3 ,
. clock_irq = 5 ,
. clock1_irq = 7 ,
. ms_kb_irq = 1 ,
. ser_irq = 1 ,
. fd_irq = 1 ,
. me_irq = 1 ,
. cs_irq = - 1 ,
. machine_id = 0x55 ,
. max_mem = 0x10000000 ,
. default_cpu_model = "Cypress CY7C601" ,
},
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
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937
938
939
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961
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970
971
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977
978
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981
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985
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1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
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1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
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1101
1102
1103
1104
1105
1106
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1111
1112
1113
1114
1115
1116
/* Voyager */
{
. iommu_base = 0x10000000 ,
. tcx_base = 0x50000000 ,
. cs_base = - 1 ,
. slavio_base = 0x70000000 ,
. ms_kb_base = 0x71000000 ,
. serial_base = 0x71100000 ,
. nvram_base = 0x71200000 ,
. fd_base = 0x71400000 ,
. counter_base = 0x71d00000 ,
. intctl_base = 0x71e00000 ,
. idreg_base = 0x78000000 ,
. dma_base = 0x78400000 ,
. esp_base = 0x78800000 ,
. le_base = 0x78c00000 ,
. apc_base = 0x71300000 , // pmc
. aux1_base = 0x71900000 ,
. aux2_base = 0x71910000 ,
. ecc_base = - 1 ,
. sun4c_intctl_base = - 1 ,
. sun4c_counter_base = - 1 ,
. vram_size = 0x00100000 ,
. nvram_size = 0x2000 ,
. esp_irq = 18 ,
. le_irq = 16 ,
. clock_irq = 7 ,
. clock1_irq = 19 ,
. ms_kb_irq = 14 ,
. ser_irq = 15 ,
. fd_irq = 22 ,
. me_irq = 30 ,
. cs_irq = - 1 ,
. machine_id = 0x80 ,
. iommu_version = 0x05000000 ,
. intbit_to_level = {
2 , 3 , 5 , 7 , 9 , 11 , 0 , 14 , 3 , 5 , 7 , 9 , 11 , 13 , 12 , 12 ,
6 , 0 , 4 , 10 , 8 , 0 , 11 , 0 , 0 , 0 , 0 , 0 , 15 , 0 , 15 , 0 ,
},
. max_mem = 0x10000000 ,
. default_cpu_model = "Fujitsu MB86904" ,
},
/* LX */
{
. iommu_base = 0x10000000 ,
. tcx_base = 0x50000000 ,
. cs_base = - 1 ,
. slavio_base = 0x70000000 ,
. ms_kb_base = 0x71000000 ,
. serial_base = 0x71100000 ,
. nvram_base = 0x71200000 ,
. fd_base = 0x71400000 ,
. counter_base = 0x71d00000 ,
. intctl_base = 0x71e00000 ,
. idreg_base = 0x78000000 ,
. dma_base = 0x78400000 ,
. esp_base = 0x78800000 ,
. le_base = 0x78c00000 ,
. apc_base = - 1 ,
. aux1_base = 0x71900000 ,
. aux2_base = 0x71910000 ,
. ecc_base = - 1 ,
. sun4c_intctl_base = - 1 ,
. sun4c_counter_base = - 1 ,
. vram_size = 0x00100000 ,
. nvram_size = 0x2000 ,
. esp_irq = 18 ,
. le_irq = 16 ,
. clock_irq = 7 ,
. clock1_irq = 19 ,
. ms_kb_irq = 14 ,
. ser_irq = 15 ,
. fd_irq = 22 ,
. me_irq = 30 ,
. cs_irq = - 1 ,
. machine_id = 0x80 ,
. iommu_version = 0x04000000 ,
. intbit_to_level = {
2 , 3 , 5 , 7 , 9 , 11 , 0 , 14 , 3 , 5 , 7 , 9 , 11 , 13 , 12 , 12 ,
6 , 0 , 4 , 10 , 8 , 0 , 11 , 0 , 0 , 0 , 0 , 0 , 15 , 0 , 15 , 0 ,
},
. max_mem = 0x10000000 ,
. default_cpu_model = "TI MicroSparc I" ,
},
/* SS-4 */
{
. iommu_base = 0x10000000 ,
. tcx_base = 0x50000000 ,
. cs_base = 0x6c000000 ,
. slavio_base = 0x70000000 ,
. ms_kb_base = 0x71000000 ,
. serial_base = 0x71100000 ,
. nvram_base = 0x71200000 ,
. fd_base = 0x71400000 ,
. counter_base = 0x71d00000 ,
. intctl_base = 0x71e00000 ,
. idreg_base = 0x78000000 ,
. dma_base = 0x78400000 ,
. esp_base = 0x78800000 ,
. le_base = 0x78c00000 ,
. apc_base = 0x6a000000 ,
. aux1_base = 0x71900000 ,
. aux2_base = 0x71910000 ,
. ecc_base = - 1 ,
. sun4c_intctl_base = - 1 ,
. sun4c_counter_base = - 1 ,
. vram_size = 0x00100000 ,
. nvram_size = 0x2000 ,
. esp_irq = 18 ,
. le_irq = 16 ,
. clock_irq = 7 ,
. clock1_irq = 19 ,
. ms_kb_irq = 14 ,
. ser_irq = 15 ,
. fd_irq = 22 ,
. me_irq = 30 ,
. cs_irq = 5 ,
. machine_id = 0x80 ,
. iommu_version = 0x05000000 ,
. intbit_to_level = {
2 , 3 , 5 , 7 , 9 , 11 , 0 , 14 , 3 , 5 , 7 , 9 , 11 , 13 , 12 , 12 ,
6 , 0 , 4 , 10 , 8 , 0 , 11 , 0 , 0 , 0 , 0 , 0 , 15 , 0 , 15 , 0 ,
},
. max_mem = 0x10000000 ,
. default_cpu_model = "Fujitsu MB86904" ,
},
/* SPARCClassic */
{
. iommu_base = 0x10000000 ,
. tcx_base = 0x50000000 ,
. cs_base = - 1 ,
. slavio_base = 0x70000000 ,
. ms_kb_base = 0x71000000 ,
. serial_base = 0x71100000 ,
. nvram_base = 0x71200000 ,
. fd_base = 0x71400000 ,
. counter_base = 0x71d00000 ,
. intctl_base = 0x71e00000 ,
. idreg_base = 0x78000000 ,
. dma_base = 0x78400000 ,
. esp_base = 0x78800000 ,
. le_base = 0x78c00000 ,
. apc_base = 0x6a000000 ,
. aux1_base = 0x71900000 ,
. aux2_base = 0x71910000 ,
. ecc_base = - 1 ,
. sun4c_intctl_base = - 1 ,
. sun4c_counter_base = - 1 ,
. vram_size = 0x00100000 ,
. nvram_size = 0x2000 ,
. esp_irq = 18 ,
. le_irq = 16 ,
. clock_irq = 7 ,
. clock1_irq = 19 ,
. ms_kb_irq = 14 ,
. ser_irq = 15 ,
. fd_irq = 22 ,
. me_irq = 30 ,
. cs_irq = - 1 ,
. machine_id = 0x80 ,
. iommu_version = 0x05000000 ,
. intbit_to_level = {
2 , 3 , 5 , 7 , 9 , 11 , 0 , 14 , 3 , 5 , 7 , 9 , 11 , 13 , 12 , 12 ,
6 , 0 , 4 , 10 , 8 , 0 , 11 , 0 , 0 , 0 , 0 , 0 , 15 , 0 , 15 , 0 ,
},
. max_mem = 0x10000000 ,
. default_cpu_model = "TI MicroSparc I" ,
},
/* SPARCbook */
{
. iommu_base = 0x10000000 ,
. tcx_base = 0x50000000 , // XXX
. cs_base = - 1 ,
. slavio_base = 0x70000000 ,
. ms_kb_base = 0x71000000 ,
. serial_base = 0x71100000 ,
. nvram_base = 0x71200000 ,
. fd_base = 0x71400000 ,
. counter_base = 0x71d00000 ,
. intctl_base = 0x71e00000 ,
. idreg_base = 0x78000000 ,
. dma_base = 0x78400000 ,
. esp_base = 0x78800000 ,
. le_base = 0x78c00000 ,
. apc_base = 0x6a000000 ,
. aux1_base = 0x71900000 ,
. aux2_base = 0x71910000 ,
. ecc_base = - 1 ,
. sun4c_intctl_base = - 1 ,
. sun4c_counter_base = - 1 ,
. vram_size = 0x00100000 ,
. nvram_size = 0x2000 ,
. esp_irq = 18 ,
. le_irq = 16 ,
. clock_irq = 7 ,
. clock1_irq = 19 ,
. ms_kb_irq = 14 ,
. ser_irq = 15 ,
. fd_irq = 22 ,
. me_irq = 30 ,
. cs_irq = - 1 ,
. machine_id = 0x80 ,
. iommu_version = 0x05000000 ,
. intbit_to_level = {
2 , 3 , 5 , 7 , 9 , 11 , 0 , 14 , 3 , 5 , 7 , 9 , 11 , 13 , 12 , 12 ,
6 , 0 , 4 , 10 , 8 , 0 , 11 , 0 , 0 , 0 , 0 , 0 , 15 , 0 , 15 , 0 ,
},
. max_mem = 0x10000000 ,
. default_cpu_model = "TI MicroSparc I" ,
},
1117
1118
1119
};
/* SPARCstation 5 hardware initialisation */
1120
static void ss5_init ( ram_addr_t RAM_size , int vga_ram_size ,
1121
1122
1123
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
1124
{
1125
1126
sun4m_hw_init ( & hwdefs [ 0 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
1127
}
1128
1129
/* SPARCstation 10 hardware initialisation */
1130
static void ss10_init ( ram_addr_t RAM_size , int vga_ram_size ,
1131
1132
1133
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
1134
{
1135
1136
sun4m_hw_init ( & hwdefs [ 1 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
1137
1138
}
1139
/* SPARCserver 600MP hardware initialisation */
1140
static void ss600mp_init ( ram_addr_t RAM_size , int vga_ram_size ,
1141
const char * boot_device , DisplayState * ds ,
1142
1143
const char * kernel_filename ,
const char * kernel_cmdline ,
1144
1145
const char * initrd_filename , const char * cpu_model )
{
1146
1147
sun4m_hw_init ( & hwdefs [ 2 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
1148
1149
}
1150
/* SPARCstation 20 hardware initialisation */
1151
static void ss20_init ( ram_addr_t RAM_size , int vga_ram_size ,
1152
1153
1154
1155
1156
1157
1158
1159
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
sun4m_hw_init ( & hwdefs [ 3 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
}
1160
/* SPARCstation 2 hardware initialisation */
1161
static void ss2_init ( ram_addr_t RAM_size , int vga_ram_size ,
1162
1163
1164
1165
1166
1167
1168
1169
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
sun4c_hw_init ( & hwdefs [ 4 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
}
1170
/* SPARCstation Voyager hardware initialisation */
1171
static void vger_init ( ram_addr_t RAM_size , int vga_ram_size ,
1172
1173
1174
1175
1176
1177
1178
1179
1180
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
sun4m_hw_init ( & hwdefs [ 5 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
}
/* SPARCstation LX hardware initialisation */
1181
static void ss_lx_init ( ram_addr_t RAM_size , int vga_ram_size ,
1182
1183
1184
1185
1186
1187
1188
1189
1190
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
sun4m_hw_init ( & hwdefs [ 6 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
}
/* SPARCstation 4 hardware initialisation */
1191
static void ss4_init ( ram_addr_t RAM_size , int vga_ram_size ,
1192
1193
1194
1195
1196
1197
1198
1199
1200
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
sun4m_hw_init ( & hwdefs [ 7 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
}
/* SPARCClassic hardware initialisation */
1201
static void scls_init ( ram_addr_t RAM_size , int vga_ram_size ,
1202
1203
1204
1205
1206
1207
1208
1209
1210
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
sun4m_hw_init ( & hwdefs [ 8 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
}
/* SPARCbook hardware initialisation */
1211
static void sbook_init ( ram_addr_t RAM_size , int vga_ram_size ,
1212
1213
1214
1215
1216
1217
1218
1219
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
sun4m_hw_init ( & hwdefs [ 9 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
}
1220
1221
1222
1223
QEMUMachine ss5_machine = {
"SS-5" ,
"Sun4m platform, SPARCstation 5" ,
ss5_init ,
1224
PROM_SIZE_MAX + TCX_SIZE ,
1225
};
1226
1227
1228
1229
1230
QEMUMachine ss10_machine = {
"SS-10" ,
"Sun4m platform, SPARCstation 10" ,
ss10_init ,
1231
PROM_SIZE_MAX + TCX_SIZE ,
1232
};
1233
1234
1235
1236
1237
QEMUMachine ss600mp_machine = {
"SS-600MP" ,
"Sun4m platform, SPARCserver 600MP" ,
ss600mp_init ,
1238
PROM_SIZE_MAX + TCX_SIZE ,
1239
};
1240
1241
1242
1243
1244
QEMUMachine ss20_machine = {
"SS-20" ,
"Sun4m platform, SPARCstation 20" ,
ss20_init ,
1245
PROM_SIZE_MAX + TCX_SIZE ,
1246
1247
};
1248
1249
1250
1251
QEMUMachine ss2_machine = {
"SS-2" ,
"Sun4c platform, SPARCstation 2" ,
ss2_init ,
1252
PROM_SIZE_MAX + TCX_SIZE ,
1253
};
1254
1255
1256
1257
1258
QEMUMachine voyager_machine = {
"Voyager" ,
"Sun4m platform, SPARCstation Voyager" ,
vger_init ,
1259
PROM_SIZE_MAX + TCX_SIZE ,
1260
1261
1262
1263
1264
1265
};
QEMUMachine ss_lx_machine = {
"LX" ,
"Sun4m platform, SPARCstation LX" ,
ss_lx_init ,
1266
PROM_SIZE_MAX + TCX_SIZE ,
1267
1268
1269
1270
1271
1272
};
QEMUMachine ss4_machine = {
"SS-4" ,
"Sun4m platform, SPARCstation 4" ,
ss4_init ,
1273
PROM_SIZE_MAX + TCX_SIZE ,
1274
1275
1276
1277
1278
1279
};
QEMUMachine scls_machine = {
"SPARCClassic" ,
"Sun4m platform, SPARCClassic" ,
scls_init ,
1280
PROM_SIZE_MAX + TCX_SIZE ,
1281
1282
1283
1284
1285
1286
};
QEMUMachine sbook_machine = {
"SPARCbook" ,
"Sun4m platform, SPARCbook" ,
sbook_init ,
1287
PROM_SIZE_MAX + TCX_SIZE ,
1288
1289
};
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
static const struct sun4d_hwdef sun4d_hwdefs [] = {
/* SS-1000 */
{
. iounit_bases = {
0xfe0200000ULL ,
0xfe1200000ULL ,
0xfe2200000ULL ,
0xfe3200000ULL ,
- 1 ,
},
. tcx_base = 0x820000000ULL ,
. slavio_base = 0xf00000000ULL ,
. ms_kb_base = 0xf00240000ULL ,
. serial_base = 0xf00200000ULL ,
. nvram_base = 0xf00280000ULL ,
. counter_base = 0xf00300000ULL ,
. espdma_base = 0x800081000ULL ,
. esp_base = 0x800080000ULL ,
. ledma_base = 0x800040000ULL ,
. le_base = 0x800060000ULL ,
. sbi_base = 0xf02800000ULL ,
1311
. vram_size = 0x00100000 ,
1312
1313
1314
1315
1316
1317
1318
1319
1320
. nvram_size = 0x2000 ,
. esp_irq = 3 ,
. le_irq = 4 ,
. clock_irq = 14 ,
. clock1_irq = 10 ,
. ms_kb_irq = 12 ,
. ser_irq = 12 ,
. machine_id = 0x80 ,
. iounit_version = 0x03000000 ,
1321
. max_mem = 0xf00000000ULL ,
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
. default_cpu_model = "TI SuperSparc II" ,
},
/* SS-2000 */
{
. iounit_bases = {
0xfe0200000ULL ,
0xfe1200000ULL ,
0xfe2200000ULL ,
0xfe3200000ULL ,
0xfe4200000ULL ,
},
. tcx_base = 0x820000000ULL ,
. slavio_base = 0xf00000000ULL ,
. ms_kb_base = 0xf00240000ULL ,
. serial_base = 0xf00200000ULL ,
. nvram_base = 0xf00280000ULL ,
. counter_base = 0xf00300000ULL ,
. espdma_base = 0x800081000ULL ,
. esp_base = 0x800080000ULL ,
. ledma_base = 0x800040000ULL ,
. le_base = 0x800060000ULL ,
. sbi_base = 0xf02800000ULL ,
1344
. vram_size = 0x00100000 ,
1345
1346
1347
1348
1349
1350
1351
1352
1353
. nvram_size = 0x2000 ,
. esp_irq = 3 ,
. le_irq = 4 ,
. clock_irq = 14 ,
. clock1_irq = 10 ,
. ms_kb_irq = 12 ,
. ser_irq = 12 ,
. machine_id = 0x80 ,
. iounit_version = 0x03000000 ,
1354
. max_mem = 0xf00000000ULL ,
1355
1356
1357
1358
. default_cpu_model = "TI SuperSparc II" ,
},
};
1359
static void sun4d_hw_init ( const struct sun4d_hwdef * hwdef , ram_addr_t RAM_size ,
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
const char * boot_device ,
DisplayState * ds , const char * kernel_filename ,
const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
CPUState * env , * envs [ MAX_CPUS ];
unsigned int i ;
void * iounits [ MAX_IOUNITS ], * espdma , * ledma , * main_esp , * nvram , * sbi ;
qemu_irq * cpu_irqs [ MAX_CPUS ], * sbi_irq , * sbi_cpu_irq ,
* espdma_irq , * ledma_irq ;
qemu_irq * esp_reset , * le_reset ;
unsigned long prom_offset , kernel_size ;
int ret ;
char buf [ 1024 ];
1374
int drive_index ;
1375
1376
1377
1378
1379
1380
1381
1382
/* init CPUs */
if ( ! cpu_model )
cpu_model = hwdef -> default_cpu_model ;
for ( i = 0 ; i < smp_cpus ; i ++ ) {
env = cpu_init ( cpu_model );
if ( ! env ) {
1383
fprintf ( stderr , "qemu: Unable to find Sparc CPU definition \n " );
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
exit ( 1 );
}
cpu_sparc_set_id ( env , i );
envs [ i ] = env ;
if ( i == 0 ) {
qemu_register_reset ( main_cpu_reset , env );
} else {
qemu_register_reset ( secondary_cpu_reset , env );
env -> halted = 1 ;
}
register_savevm ( "cpu" , i , 3 , cpu_save , cpu_load , env );
cpu_irqs [ i ] = qemu_allocate_irqs ( cpu_set_irq , envs [ i ], MAX_PILS );
env -> prom_addr = hwdef -> slavio_base ;
}
for ( i = smp_cpus ; i < MAX_CPUS ; i ++ )
cpu_irqs [ i ] = qemu_allocate_irqs ( dummy_cpu_set_irq , NULL , MAX_PILS );
/* allocate RAM */
if (( uint64_t ) RAM_size > hwdef -> max_mem ) {
1404
1405
fprintf ( stderr ,
"qemu: Too much memory for this machine: %d, maximum %d \n " ,
1406
( unsigned int )( RAM_size / ( 1024 * 1024 )),
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
( unsigned int )( hwdef -> max_mem / ( 1024 * 1024 )));
exit ( 1 );
}
cpu_register_physical_memory ( 0 , RAM_size , 0 );
/* load boot prom */
prom_offset = RAM_size + hwdef -> vram_size ;
cpu_register_physical_memory ( hwdef -> slavio_base ,
( PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1 ) &
TARGET_PAGE_MASK ,
prom_offset | IO_MEM_ROM );
if ( bios_name == NULL )
bios_name = PROM_FILENAME ;
snprintf ( buf , sizeof ( buf ), "%s/%s" , bios_dir , bios_name );
ret = load_elf ( buf , hwdef -> slavio_base - PROM_VADDR , NULL , NULL , NULL );
if ( ret < 0 || ret > PROM_SIZE_MAX )
1424
ret = load_image_targphys ( buf , hwdef -> slavio_base , PROM_SIZE_MAX );
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
if ( ret < 0 || ret > PROM_SIZE_MAX ) {
fprintf ( stderr , "qemu: could not load prom '%s' \n " ,
buf );
exit ( 1 );
}
/* set up devices */
sbi = sbi_init ( hwdef -> sbi_base , & sbi_irq , & sbi_cpu_irq , cpu_irqs );
for ( i = 0 ; i < MAX_IOUNITS ; i ++ )
if ( hwdef -> iounit_bases [ i ] != ( target_phys_addr_t ) - 1 )
1436
1437
1438
iounits [ i ] = iommu_init ( hwdef -> iounit_bases [ i ],
hwdef -> iounit_version ,
sbi_irq [ hwdef -> me_irq ]);
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
espdma = sparc32_dma_init ( hwdef -> espdma_base , sbi_irq [ hwdef -> esp_irq ],
iounits [ 0 ], & espdma_irq , & esp_reset );
ledma = sparc32_dma_init ( hwdef -> ledma_base , sbi_irq [ hwdef -> le_irq ],
iounits [ 0 ], & ledma_irq , & le_reset );
if ( graphic_depth != 8 && graphic_depth != 24 ) {
fprintf ( stderr , "qemu: Unsupported depth: %d \n " , graphic_depth );
exit ( 1 );
}
tcx_init ( ds , hwdef -> tcx_base , phys_ram_base + RAM_size , RAM_size ,
hwdef -> vram_size , graphic_width , graphic_height , graphic_depth );
if ( nd_table [ 0 ]. model == NULL
|| strcmp ( nd_table [ 0 ]. model , "lance" ) == 0 ) {
lance_init ( & nd_table [ 0 ], hwdef -> le_base , ledma , * ledma_irq , le_reset );
} else if ( strcmp ( nd_table [ 0 ]. model , "?" ) == 0 ) {
fprintf ( stderr , "qemu: Supported NICs: lance \n " );
exit ( 1 );
} else {
fprintf ( stderr , "qemu: Unsupported NIC: %s \n " , nd_table [ 0 ]. model );
exit ( 1 );
}
nvram = m48t59_init ( sbi_irq [ 0 ], hwdef -> nvram_base , 0 ,
hwdef -> nvram_size , 8 );
slavio_timer_init_all ( hwdef -> counter_base , sbi_irq [ hwdef -> clock1_irq ],
sbi_cpu_irq , smp_cpus );
slavio_serial_ms_kbd_init ( hwdef -> ms_kb_base , sbi_irq [ hwdef -> ms_kb_irq ],
nographic );
// Slavio TTYA ( base + 4 , Linux ttyS0 ) is the first Qemu serial device
// Slavio TTYB ( base + 0 , Linux ttyS1 ) is the second Qemu serial device
slavio_serial_init ( hwdef -> serial_base , sbi_irq [ hwdef -> ser_irq ],
serial_hds [ 1 ], serial_hds [ 0 ]);
if ( drive_get_max_bus ( IF_SCSI ) > 0 ) {
fprintf ( stderr , "qemu: too many SCSI bus \n " );
exit ( 1 );
}
1482
main_esp = esp_init ( hwdef -> esp_base , 2 ,
1483
1484
espdma_memory_read , espdma_memory_write ,
espdma , * espdma_irq , esp_reset );
1485
1486
for ( i = 0 ; i < ESP_MAX_DEVS ; i ++ ) {
1487
1488
drive_index = drive_get_index ( IF_SCSI , 0 , i );
if ( drive_index == - 1 )
1489
continue ;
1490
esp_scsi_attach ( main_esp , drives_table [ drive_index ]. bdrv , i );
1491
1492
}
1493
1494
kernel_size = sun4m_load_kernel ( kernel_filename , initrd_filename ,
RAM_size );
1495
1496
1497
1498
1499
1500
1501
nvram_init ( nvram , ( uint8_t * ) & nd_table [ 0 ]. macaddr , kernel_cmdline ,
boot_device , RAM_size , kernel_size , graphic_width ,
graphic_height , graphic_depth , hwdef -> machine_id , "Sun4d" );
}
/* SPARCserver 1000 hardware initialisation */
1502
static void ss1000_init ( ram_addr_t RAM_size , int vga_ram_size ,
1503
1504
1505
1506
1507
1508
1509
1510
1511
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
sun4d_hw_init ( & sun4d_hwdefs [ 0 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
}
/* SPARCcenter 2000 hardware initialisation */
1512
static void ss2000_init ( ram_addr_t RAM_size , int vga_ram_size ,
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
const char * boot_device , DisplayState * ds ,
const char * kernel_filename , const char * kernel_cmdline ,
const char * initrd_filename , const char * cpu_model )
{
sun4d_hw_init ( & sun4d_hwdefs [ 1 ], RAM_size , boot_device , ds , kernel_filename ,
kernel_cmdline , initrd_filename , cpu_model );
}
QEMUMachine ss1000_machine = {
"SS-1000" ,
"Sun4d platform, SPARCserver 1000" ,
ss1000_init ,
1525
PROM_SIZE_MAX + TCX_SIZE ,
1526
1527
1528
1529
1530
1531
};
QEMUMachine ss2000_machine = {
"SS-2000" ,
"Sun4d platform, SPARCcenter 2000" ,
ss2000_init ,
1532
PROM_SIZE_MAX + TCX_SIZE ,
1533
};