gwj / at91sam9263 · Commits

Commit b8174937ed2c885aca5b9b08773a34397d802717

Authored by bellard
1 parent 519945df

dummy cs4231 audio driver for sun4m (Blue Swirl) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2157 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 191 additions and 0 deletions
Makefile.target
  View file @b817493
... ... @@ -361,6 +361,7 @@ VL_OBJS+= cirrus_vga.o parallel.o
361 361 else
362 362 VL_OBJS+= sun4m.o tcx.o pcnet.o iommu.o m48t59.o slavio_intctl.o
363 363 VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o sparc32_dma.o
  364 +VL_OBJS+= cs4231.o
364 365 endif
365 366 endif
366 367 ifeq ($(TARGET_BASE_ARCH), arm)
... ...
hw/cs4231.c 0 → 100644
  View file @b817493
  1 +/*
  2 + * QEMU Crystal CS4231 audio chip emulation
  3 + *
  4 + * Copyright (c) 2006 Fabrice Bellard
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +#include "vl.h"
  25 +
  26 +/* debug CS4231 */
  27 +//#define DEBUG_CS
  28 +
  29 +/*
  30 + * In addition to Crystal CS4231 there is a DMA controller on Sparc.
  31 + */
  32 +#define CS_MAXADDR 0x3f
  33 +#define CS_REGS 16
  34 +#define CS_DREGS 32
  35 +#define CS_MAXDREG (CS_DREGS - 1)
  36 +
  37 +typedef struct CSState {
  38 + uint32_t regs[CS_REGS];
  39 + uint8_t dregs[CS_DREGS];
  40 + void *intctl;
  41 +} CSState;
  42 +
  43 +#define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
  44 +#define CS_VER 0xa0
  45 +#define CS_CDC_VER 0x8a
  46 +
  47 +#ifdef DEBUG_CS
  48 +#define DPRINTF(fmt, args...) \
  49 + do { printf("CS: " fmt , ##args); } while (0)
  50 +#define pic_set_irq_new(intctl, irq, level) \
  51 + do { printf("CS: set_irq(%d): %d\n", (irq), (level)); \
  52 + pic_set_irq_new((intctl), (irq),(level));} while (0)
  53 +#else
  54 +#define DPRINTF(fmt, args...)
  55 +#endif
  56 +
  57 +static void cs_reset(void *opaque)
  58 +{
  59 + CSState *s = opaque;
  60 +
  61 + memset(s->regs, 0, CS_REGS * 4);
  62 + memset(s->dregs, 0, CS_DREGS);
  63 + s->dregs[12] = CS_CDC_VER;
  64 + s->dregs[25] = CS_VER;
  65 +}
  66 +
  67 +static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
  68 +{
  69 + CSState *s = opaque;
  70 + uint32_t saddr, ret;
  71 +
  72 + saddr = (addr & CS_MAXADDR) >> 2;
  73 + switch (saddr) {
  74 + case 1:
  75 + switch (CS_RAP(s)) {
  76 + case 3: // Write only
  77 + ret = 0;
  78 + break;
  79 + default:
  80 + ret = s->dregs[CS_RAP(s)];
  81 + break;
  82 + }
  83 + DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
  84 + break;
  85 + default:
  86 + ret = s->regs[saddr];
  87 + DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
  88 + break;
  89 + }
  90 + return ret;
  91 +}
  92 +
  93 +static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  94 +{
  95 + CSState *s = opaque;
  96 + uint32_t saddr;
  97 +
  98 + saddr = (addr & CS_MAXADDR) >> 2;
  99 + DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
  100 + switch (saddr) {
  101 + case 1:
  102 + DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), s->dregs[CS_RAP(s)], val);
  103 + switch(CS_RAP(s)) {
  104 + case 11:
  105 + case 25: // Read only
  106 + break;
  107 + case 12:
  108 + val &= 0x40;
  109 + val |= CS_CDC_VER; // Codec version
  110 + s->dregs[CS_RAP(s)] = val;
  111 + break;
  112 + default:
  113 + s->dregs[CS_RAP(s)] = val;
  114 + break;
  115 + }
  116 + break;
  117 + case 2: // Read only
  118 + break;
  119 + case 4:
  120 + if (val & 1)
  121 + cs_reset(s);
  122 + val &= 0x7f;
  123 + s->regs[saddr] = val;
  124 + break;
  125 + default:
  126 + s->regs[saddr] = val;
  127 + break;
  128 + }
  129 +}
  130 +
  131 +static CPUReadMemoryFunc *cs_mem_read[3] = {
  132 + cs_mem_readl,
  133 + cs_mem_readl,
  134 + cs_mem_readl,
  135 +};
  136 +
  137 +static CPUWriteMemoryFunc *cs_mem_write[3] = {
  138 + cs_mem_writel,
  139 + cs_mem_writel,
  140 + cs_mem_writel,
  141 +};
  142 +
  143 +static void cs_save(QEMUFile *f, void *opaque)
  144 +{
  145 + CSState *s = opaque;
  146 + unsigned int i;
  147 +
  148 + for (i = 0; i < CS_REGS; i++)
  149 + qemu_put_be32s(f, &s->regs[i]);
  150 +
  151 + qemu_put_buffer(f, s->dregs, CS_DREGS);
  152 +}
  153 +
  154 +static int cs_load(QEMUFile *f, void *opaque, int version_id)
  155 +{
  156 + CSState *s = opaque;
  157 + unsigned int i;
  158 +
  159 + if (version_id > 1)
  160 + return -EINVAL;
  161 +
  162 + for (i = 0; i < CS_REGS; i++)
  163 + qemu_get_be32s(f, &s->regs[i]);
  164 +
  165 + qemu_get_buffer(f, s->dregs, CS_DREGS);
  166 + return 0;
  167 +}
  168 +
  169 +void cs_init(target_phys_addr_t base, int irq, void *intctl)
  170 +{
  171 + int cs_io_memory;
  172 + CSState *s;
  173 +
  174 + s = qemu_mallocz(sizeof(CSState));
  175 + if (!s)
  176 + return;
  177 +
  178 + cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
  179 + cpu_register_physical_memory(base, CS_MAXADDR, cs_io_memory);
  180 + register_savevm("cs4231", base, 1, cs_save, cs_load, s);
  181 + qemu_register_reset(cs_reset, s);
  182 + cs_reset(s);
  183 +}
... ...
hw/sun4m.c
  View file @b817493
... ... @@ -55,6 +55,9 @@
55 55 #define PHYS_JJ_FDC 0x71400000 /* Floppy */
56 56 #define PHYS_JJ_FLOPPY_IRQ 22
57 57 #define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */
  58 +#define PHYS_JJ_CS 0x6c000000 /* Crystal CS4231 */
  59 +#define PHYS_JJ_CS_IRQ 5
  60 +
58 61 #define MAX_CPUS 16
59 62  
60 63 /* TSC handling */
... ... @@ -260,6 +263,7 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
260 263 fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
261 264 main_esp = esp_init(bs_table, PHYS_JJ_ESP, dma);
262 265 slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
  266 + cs_init(PHYS_JJ_CS, PHYS_JJ_CS_IRQ, slavio_intctl);
263 267 sparc32_dma_set_reset_data(dma, main_esp, main_lance);
264 268  
265 269 prom_offset = ram_size + vram_size;
... ...
... ... @@ -1097,6 +1097,9 @@ void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1097 1097 void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1098 1098 void *lance_opaque);
1099 1099  
  1100 +/* cs4231.c */
  1101 +void cs_init(target_phys_addr_t base, int irq, void *intctl);
  1102 +
1100 1103 /* sun4u.c */
1101 1104 extern QEMUMachine sun4u_machine;
1102 1105  
... ...