gwj / at91sam9263 · Commits

Commit 7fbfb139ec0b3d3572369db977ea354c274dabdf

Authored by blueswir1
1 parent 2761992d

Machine specific IOMMU version (Robert Reif) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3664 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 13 additions and 6 deletions
hw/iommu.c
  View file @7fbfb13
... ... @@ -37,7 +37,6 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
37 37 #define IOMMU_CTRL (0x0000 >> 2)
38 38 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
39 39 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
40   -#define IOMMU_VERSION 0x04000000
41 40 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
42 41 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
43 42 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
... ... @@ -104,6 +103,7 @@ typedef struct IOMMUState {
104 103 target_phys_addr_t addr;
105 104 uint32_t regs[IOMMU_NREGS];
106 105 target_phys_addr_t iostart;
  106 + uint32_t version;
107 107 } IOMMUState;
108 108  
109 109 static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
... ... @@ -158,7 +158,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
158 158 break;
159 159 }
160 160 DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
161   - s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
  161 + s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
162 162 break;
163 163 case IOMMU_BASE:
164 164 s->regs[saddr] = val & IOMMU_BASE_MASK;
... ... @@ -308,10 +308,11 @@ static void iommu_reset(void *opaque)
308 308  
309 309 memset(s->regs, 0, IOMMU_NREGS * 4);
310 310 s->iostart = 0;
311   - s->regs[IOMMU_CTRL] = IOMMU_VERSION;
  311 + s->regs[IOMMU_CTRL] = s->version;
  312 + s->regs[IOMMU_ARBEN] = IOMMU_MID;
312 313 }
313 314  
314   -void *iommu_init(target_phys_addr_t addr)
  315 +void *iommu_init(target_phys_addr_t addr, uint32_t version)
315 316 {
316 317 IOMMUState *s;
317 318 int iommu_io_memory;
... ... @@ -321,12 +322,14 @@ void *iommu_init(target_phys_addr_t addr)
321 322 return NULL;
322 323  
323 324 s->addr = addr;
  325 + s->version = version;
324 326  
325 327 iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
326 328 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
327 329  
328 330 register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
329 331 qemu_register_reset(iommu_reset, s);
  332 + iommu_reset(s);
330 333 return s;
331 334 }
332 335  
... ...
hw/sun4m.c
  View file @7fbfb13
... ... @@ -72,6 +72,7 @@ struct hwdef {
72 72 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
73 73 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
74 74 int machine_id; // For NVRAM
  75 + uint32_t iommu_version;
75 76 uint32_t intbit_to_level[32];
76 77 };
77 78  
... ... @@ -302,7 +303,7 @@ static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
302 303 /* allocate RAM */
303 304 cpu_register_physical_memory(0, RAM_size, 0);
304 305  
305   - iommu = iommu_init(hwdef->iommu_base);
  306 + iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version);
306 307 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
307 308 hwdef->intctl_base + 0x10000ULL,
308 309 &hwdef->intbit_to_level[0],
... ... @@ -468,6 +469,7 @@ static const struct hwdef hwdefs[] = {
468 469 .me_irq = 30,
469 470 .cs_irq = 5,
470 471 .machine_id = 0x80,
  472 + .iommu_version = 0x04000000,
471 473 .intbit_to_level = {
472 474 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
473 475 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
... ... @@ -501,6 +503,7 @@ static const struct hwdef hwdefs[] = {
501 503 .me_irq = 30,
502 504 .cs_irq = -1,
503 505 .machine_id = 0x72,
  506 + .iommu_version = 0x03000000,
504 507 .intbit_to_level = {
505 508 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
506 509 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
... ... @@ -534,6 +537,7 @@ static const struct hwdef hwdefs[] = {
534 537 .me_irq = 30,
535 538 .cs_irq = -1,
536 539 .machine_id = 0x71,
  540 + .iommu_version = 0x01000000,
537 541 .intbit_to_level = {
538 542 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
539 543 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
... ...
... ... @@ -1051,7 +1051,7 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1051 1051 extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine;
1052 1052  
1053 1053 /* iommu.c */
1054   -void *iommu_init(target_phys_addr_t addr);
  1054 +void *iommu_init(target_phys_addr_t addr, uint32_t version);
1055 1055 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1056 1056 uint8_t *buf, int len, int is_write);
1057 1057 static inline void sparc_iommu_memory_read(void *opaque,
... ...