gwj / at91sam9263 · Commits

Commit 77f193daa80a097a892c5c86e6038de9ffe59938

Authored by blueswir1
1 parent 8686c490

Wrap long lines 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4440 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 13 changed files with 395 additions and 200 deletions
hw/apb_pci.c
  View file @77f193d
... ... @@ -230,9 +230,12 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
230 230 pci_apb_iowrite, s);
231 231  
232 232 cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config);
233   - cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config);
234   - cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport);
235   - cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
  233 + cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10,
  234 + pci_mem_config);
  235 + cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000,
  236 + pci_ioport);
  237 + cpu_register_physical_memory(mem_base, 0x10000000,
  238 + pci_mem_data); // XXX size should be 4G-prom
236 239  
237 240 d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice),
238 241 0, NULL, NULL);
... ... @@ -252,8 +255,10 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
252 255 d->config[0x0E] = 0x00; // header_type
253 256  
254 257 /* APB secondary busses */
255   - secondary = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 1");
256   - pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 2");
  258 + secondary = pci_bridge_init(s->bus, 8, 0x108e5000, pci_apb_map_irq,
  259 + "Advanced PCI Bus secondary bridge 1");
  260 + pci_bridge_init(s->bus, 9, 0x108e5000, pci_apb_map_irq,
  261 + "Advanced PCI Bus secondary bridge 2");
257 262 return secondary;
258 263 }
259 264  
... ...
hw/cs4231.c
  View file @77f193d
... ... @@ -98,7 +98,8 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
98 98 DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
99 99 switch (saddr) {
100 100 case 1:
101   - DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), s->dregs[CS_RAP(s)], val);
  101 + DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
  102 + s->dregs[CS_RAP(s)], val);
102 103 switch(CS_RAP(s)) {
103 104 case 11:
104 105 case 25: // Read only
... ...
hw/eccmemctl.c
  View file @77f193d
... ... @@ -53,7 +53,8 @@
53 53  
54 54 /* ECC fault control register */
55 55 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */
56   -#define ECC_MER_EI 0x00000002 /* Enable Interrupts on correctable errors */
  56 +#define ECC_MER_EI 0x00000002 /* Enable Interrupts on
  57 + correctable errors */
57 58 #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */
58 59 #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */
59 60 #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */
... ... @@ -65,7 +66,7 @@
65 66 #define ECC_MER_REU 0x00000200 /* Memory Refresh Enable (600MP) */
66 67 #define ECC_MER_MRR 0x000003fc /* MRR mask */
67 68 #define ECC_MEM_A 0x00000400 /* Memory controller addr map select */
68   -#define ECC_MER_DCI 0x00000800 /* Dsiables Coherent Invalidate ACK */
  69 +#define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */
69 70 #define ECC_MER_VER 0x0f000000 /* Version */
70 71 #define ECC_MER_IMPL 0xf0000000 /* Implementation */
71 72  
... ...
hw/slavio_intctl.c
  View file @77f193d
... ... @@ -99,7 +99,8 @@ static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
99 99 return ret;
100 100 }
101 101  
102   -static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  102 +static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
  103 + uint32_t val)
103 104 {
104 105 SLAVIO_INTCTLState *s = opaque;
105 106 uint32_t saddr;
... ... @@ -115,13 +116,15 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint
115 116 val &= CPU_SOFTIRQ_MASK;
116 117 s->intreg_pending[cpu] &= ~val;
117 118 slavio_check_interrupts(s);
118   - DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
  119 + DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val,
  120 + s->intreg_pending[cpu]);
119 121 break;
120 122 case 2: // set softint
121 123 val &= CPU_SOFTIRQ_MASK;
122 124 s->intreg_pending[cpu] |= val;
123 125 slavio_check_interrupts(s);
124   - DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
  126 + DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val,
  127 + s->intreg_pending[cpu]);
125 128 break;
126 129 default:
127 130 break;
... ... @@ -166,7 +169,8 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
166 169 return ret;
167 170 }
168 171  
169   -static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  172 +static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
  173 + uint32_t val)
170 174 {
171 175 SLAVIO_INTCTLState *s = opaque;
172 176 uint32_t saddr;
... ... @@ -178,7 +182,8 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin
178 182 // Force clear unused bits
179 183 val &= MASTER_IRQ_MASK;
180 184 s->intregm_disabled &= ~val;
181   - DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
  185 + DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
  186 + s->intregm_disabled);
182 187 slavio_check_interrupts(s);
183 188 break;
184 189 case 3: // set (disable, clear pending)
... ... @@ -187,7 +192,8 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin
187 192 s->intregm_disabled |= val;
188 193 s->intregm_pending &= ~val;
189 194 slavio_check_interrupts(s);
190   - DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
  195 + DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
  196 + s->intregm_disabled);
191 197 break;
192 198 case 4:
193 199 s->target_cpu = val & (MAX_CPUS - 1);
... ... @@ -219,7 +225,8 @@ void slavio_pic_info(void *opaque)
219 225 for (i = 0; i < MAX_CPUS; i++) {
220 226 term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
221 227 }
222   - term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
  228 + term_printf("master: pending 0x%08x, disabled 0x%08x\n",
  229 + s->intregm_pending, s->intregm_disabled);
223 230 }
224 231  
225 232 void slavio_irq_info(void *opaque)
... ... @@ -376,16 +383,23 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
376 383  
377 384 s->intbit_to_level = intbit_to_level;
378 385 for (i = 0; i < MAX_CPUS; i++) {
379   - slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
  386 + slavio_intctl_io_memory = cpu_register_io_memory(0,
  387 + slavio_intctl_mem_read,
  388 + slavio_intctl_mem_write,
  389 + s);
380 390 cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
381 391 slavio_intctl_io_memory);
382 392 s->cpu_irqs[i] = parent_irq[i];
383 393 }
384 394  
385   - slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
  395 + slavio_intctlm_io_memory = cpu_register_io_memory(0,
  396 + slavio_intctlm_mem_read,
  397 + slavio_intctlm_mem_write,
  398 + s);
386 399 cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
387 400  
388   - register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
  401 + register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
  402 + slavio_intctl_load, s);
389 403 qemu_register_reset(slavio_intctl_reset, s);
390 404 *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
391 405  
... ...
hw/slavio_timer.c
  View file @77f193d
... ... @@ -206,7 +206,8 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
206 206 s->limit = val & TIMER_MAX_COUNT32;
207 207 if (s->timer) {
208 208 if (s->limit == 0) /* free-run */
209   - ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
  209 + ptimer_set_limit(s->timer,
  210 + LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
210 211 else
211 212 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
212 213 }
... ... @@ -233,7 +234,8 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
233 234 s->limit = val & TIMER_MAX_COUNT32;
234 235 if (s->timer) {
235 236 if (s->limit == 0) /* free-run */
236   - ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
  237 + ptimer_set_limit(s->timer,
  238 + LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
237 239 else
238 240 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
239 241 }
... ... @@ -271,7 +273,8 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
271 273 // user timer limit is always the same
272 274 s->slave[i]->limit = TIMER_MAX_COUNT64;
273 275 ptimer_set_limit(s->slave[i]->timer,
274   - LIMIT_TO_PERIODS(s->slave[i]->limit), 1);
  276 + LIMIT_TO_PERIODS(s->slave[i]->limit),
  277 + 1);
275 278 // set this processors user timer bit in config
276 279 // register
277 280 s->slave_mode |= processor;
... ...
hw/sun4c_intctl.c
  View file @77f193d
... ... @@ -68,7 +68,8 @@ static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
68 68 return ret;
69 69 }
70 70  
71   -static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  71 +static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr,
  72 + uint32_t val)
72 73 {
73 74 Sun4c_INTCTLState *s = opaque;
74 75  
... ... @@ -94,7 +95,8 @@ void sun4c_pic_info(void *opaque)
94 95 {
95 96 Sun4c_INTCTLState *s = opaque;
96 97  
97   - term_printf("master: pending 0x%2.2x, enabled 0x%2.2x\n", s->pending, s->reg);
  98 + term_printf("master: pending 0x%2.2x, enabled 0x%2.2x\n", s->pending,
  99 + s->reg);
98 100 }
99 101  
100 102 void sun4c_irq_info(void *opaque)
... ...
hw/sun4m.c
  View file @77f193d
... ... @@ -41,7 +41,8 @@
41 41 * Sun4m architecture was used in the following machines:
42 42 *
43 43 * SPARCserver 6xxMP/xx
44   - * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
  44 + * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
  45 + * SPARCclassic X (4/10)
45 46 * SPARCstation LX/ZX (4/30)
46 47 * SPARCstation Voyager
47 48 * SPARCstation 10/xx, SPARCserver 10/xx
... ... @@ -327,9 +328,11 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename,
327 328 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328 329 NULL);
329 330 if (kernel_size < 0)
330   - kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
  331 + kernel_size = load_aout(kernel_filename,
  332 + phys_ram_base + KERNEL_LOAD_ADDR);
331 333 if (kernel_size < 0)
332   - kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
  334 + kernel_size = load_image(kernel_filename,
  335 + phys_ram_base + KERNEL_LOAD_ADDR);
333 336 if (kernel_size < 0) {
334 337 fprintf(stderr, "qemu: could not load kernel '%s'\n",
335 338 kernel_filename);
... ... @@ -339,7 +342,8 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename,
339 342 /* load initrd */
340 343 initrd_size = 0;
341 344 if (initrd_filename) {
342   - initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
  345 + initrd_size = load_image(initrd_filename,
  346 + phys_ram_base + INITRD_LOAD_ADDR);
343 347 if (initrd_size < 0) {
344 348 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
345 349 initrd_filename);
... ... @@ -350,8 +354,10 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename,
350 354 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
351 355 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
352 356 == 0x48647253) { // HdrS
353   - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
354   - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
  357 + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16,
  358 + INITRD_LOAD_ADDR);
  359 + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20,
  360 + initrd_size);
355 361 break;
356 362 }
357 363 }
... ... @@ -409,7 +415,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
409 415  
410 416 /* allocate RAM */
411 417 if ((uint64_t)RAM_size > hwdef->max_mem) {
412   - fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
  418 + fprintf(stderr,
  419 + "qemu: Too much memory for this machine: %d, maximum %d\n",
413 420 (unsigned int)(RAM_size / (1024 * 1024)),
414 421 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
415 422 exit(1);
... ... @@ -575,7 +582,8 @@ static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
575 582  
576 583 /* allocate RAM */
577 584 if ((uint64_t)RAM_size > hwdef->max_mem) {
578   - fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
  585 + fprintf(stderr,
  586 + "qemu: Too much memory for this machine: %d, maximum %d\n",
579 587 (unsigned int)(RAM_size / (1024 * 1024)),
580 588 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
581 589 exit(1);
... ... @@ -1127,7 +1135,8 @@ static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1127 1135 /* SPARCserver 600MP hardware initialisation */
1128 1136 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1129 1137 const char *boot_device, DisplayState *ds,
1130   - const char *kernel_filename, const char *kernel_cmdline,
  1138 + const char *kernel_filename,
  1139 + const char *kernel_cmdline,
1131 1140 const char *initrd_filename, const char *cpu_model)
1132 1141 {
1133 1142 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
... ... @@ -1388,7 +1397,8 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1388 1397  
1389 1398 /* allocate RAM */
1390 1399 if ((uint64_t)RAM_size > hwdef->max_mem) {
1391   - fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
  1400 + fprintf(stderr,
  1401 + "qemu: Too much memory for this machine: %d, maximum %d\n",
1392 1402 (unsigned int)(RAM_size / (1024 * 1024)),
1393 1403 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1394 1404 exit(1);
... ...
hw/sun4u.c
  View file @77f193d
... ... @@ -72,7 +72,8 @@ extern int nographic;
72 72  
73 73 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
74 74 const unsigned char *arch,
75   - ram_addr_t RAM_size, const char *boot_devices,
  75 + ram_addr_t RAM_size,
  76 + const char *boot_devices,
76 77 uint32_t kernel_image, uint32_t kernel_size,
77 78 const char *cmdline,
78 79 uint32_t initrd_image, uint32_t initrd_size,
... ... @@ -268,7 +269,8 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
268 269  
269 270 prom_offset = RAM_size + vga_ram_size;
270 271 cpu_register_physical_memory(PROM_ADDR,
271   - (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
  272 + (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
  273 + TARGET_PAGE_MASK,
272 274 prom_offset | IO_MEM_ROM);
273 275  
274 276 if (bios_name == NULL)
... ... @@ -287,9 +289,11 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
287 289 /* XXX: put correct offset */
288 290 kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
289 291 if (kernel_size < 0)
290   - kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
  292 + kernel_size = load_aout(kernel_filename,
  293 + phys_ram_base + KERNEL_LOAD_ADDR);
291 294 if (kernel_size < 0)
292   - kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
  295 + kernel_size = load_image(kernel_filename,
  296 + phys_ram_base + KERNEL_LOAD_ADDR);
293 297 if (kernel_size < 0) {
294 298 fprintf(stderr, "qemu: could not load kernel '%s'\n",
295 299 kernel_filename);
... ... @@ -298,7 +302,8 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
298 302  
299 303 /* load initrd */
300 304 if (initrd_filename) {
301   - initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
  305 + initrd_size = load_image(initrd_filename,
  306 + phys_ram_base + INITRD_LOAD_ADDR);
302 307 if (initrd_size < 0) {
303 308 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
304 309 initrd_filename);
... ... @@ -309,8 +314,10 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
309 314 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
310 315 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
311 316 == 0x48647253) { // HdrS
312   - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
313   - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
  317 + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16,
  318 + INITRD_LOAD_ADDR);
  319 + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20,
  320 + initrd_size);
314 321 break;
315 322 }
316 323 }
... ... @@ -318,7 +325,8 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
318 325 }
319 326 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
320 327 isa_mem_base = VGA_BASE;
321   - pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size, vga_ram_size);
  328 + pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
  329 + vga_ram_size);
322 330  
323 331 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
324 332 if (serial_hds[i]) {
... ... @@ -329,7 +337,8 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
329 337  
330 338 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
331 339 if (parallel_hds[i]) {
332   - parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
  340 + parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
  341 + parallel_hds[i]);
333 342 }
334 343 }
335 344  
... ...
hw/tcx.c
  View file @77f193d
... ... @@ -516,7 +516,8 @@ void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
516 516 vram_base += size;
517 517  
518 518 io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
519   - cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory);
  519 + cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
  520 + io_memory);
520 521  
521 522 dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
522 523 s);
... ...
target-sparc/cpu.h
  View file @77f193d
... ... @@ -347,7 +347,7 @@ void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
347 347 #ifdef TARGET_SPARC64
348 348 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
349 349 #define PUT_CCR(env, val) do { int _tmp = val; \
350   - env->xcc = (_tmp >> 4) << 20; \
  350 + env->xcc = (_tmp >> 4) << 20; \
351 351 env->psr = (_tmp & 0xf) << 20; \
352 352 } while (0)
353 353 #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
... ...
target-sparc/helper.c
  View file @77f193d
... ... @@ -193,7 +193,8 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
193 193 return (3 << 8) | (4 << 2);
194 194 case 2: /* L3 PTE */
195 195 virt_addr = address & TARGET_PAGE_MASK;
196   - page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
  196 + page_offset = (address & TARGET_PAGE_MASK) &
  197 + (TARGET_PAGE_SIZE - 1);
197 198 }
198 199 break;
199 200 case 2: /* L2 PTE */
... ... @@ -243,7 +244,8 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
243 244 target_ulong vaddr;
244 245 int error_code = 0, prot, ret = 0, access_index;
245 246  
246   - error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
  247 + error_code = get_physical_address(env, &paddr, &prot, &access_index,
  248 + address, rw, mmu_idx);
247 249 if (error_code == 0) {
248 250 vaddr = address & TARGET_PAGE_MASK;
249 251 paddr &= TARGET_PAGE_MASK;
... ... @@ -387,7 +389,8 @@ void dump_mmu(CPUState *env)
387 389 /*
388 390 * UltraSparc IIi I/DMMUs
389 391 */
390   -static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
  392 +static int get_physical_address_data(CPUState *env,
  393 + target_phys_addr_t *physical, int *prot,
391 394 target_ulong address, int rw, int is_user)
392 395 {
393 396 target_ulong mask;
... ... @@ -423,7 +426,8 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
423 426 ((env->dtlb_tte[i] & 0x4) && is_user) ||
424 427 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
425 428 if (env->dmmuregs[3]) /* Fault status register */
426   - env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
  429 + env->dmmuregs[3] = 2; /* overflow (not read before
  430 + another fault) */
427 431 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
428 432 env->dmmuregs[4] = address; /* Fault address register */
429 433 env->exception_index = TT_DFAULT;
... ... @@ -432,7 +436,8 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
432 436 #endif
433 437 return 1;
434 438 }
435   - *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
  439 + *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
  440 + (address & ~mask & 0x1fffffff000ULL);
436 441 *prot = PAGE_READ;
437 442 if (env->dtlb_tte[i] & 0x2)
438 443 *prot |= PAGE_WRITE;
... ... @@ -446,7 +451,8 @@ static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical
446 451 return 1;
447 452 }
448 453  
449   -static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
  454 +static int get_physical_address_code(CPUState *env,
  455 + target_phys_addr_t *physical, int *prot,
450 456 target_ulong address, int is_user)
451 457 {
452 458 target_ulong mask;
... ... @@ -481,7 +487,8 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
481 487 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
482 488 ((env->itlb_tte[i] & 0x4) && is_user)) {
483 489 if (env->immuregs[3]) /* Fault status register */
484   - env->immuregs[3] = 2; /* overflow (not read before another fault) */
  490 + env->immuregs[3] = 2; /* overflow (not read before
  491 + another fault) */
485 492 env->immuregs[3] |= (is_user << 3) | 1;
486 493 env->exception_index = TT_TFAULT;
487 494 #ifdef DEBUG_MMU
... ... @@ -489,7 +496,8 @@ static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical
489 496 #endif
490 497 return 1;
491 498 }
492   - *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
  499 + *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
  500 + (address & ~mask & 0x1fffffff000ULL);
493 501 *prot = PAGE_EXEC;
494 502 return 0;
495 503 }
... ... @@ -523,12 +531,15 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
523 531 target_phys_addr_t paddr;
524 532 int error_code = 0, prot, ret = 0, access_index;
525 533  
526   - error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
  534 + error_code = get_physical_address(env, &paddr, &prot, &access_index,
  535 + address, rw, mmu_idx);
527 536 if (error_code == 0) {
528 537 virt_addr = address & TARGET_PAGE_MASK;
529   - vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
  538 + vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
  539 + (TARGET_PAGE_SIZE - 1));
530 540 #ifdef DEBUG_MMU
531   - printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
  541 + printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
  542 + "\n", address, paddr, vaddr);
532 543 #endif
533 544 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
534 545 return ret;
... ... @@ -543,7 +554,8 @@ void dump_mmu(CPUState *env)
543 554 unsigned int i;
544 555 const char *mask;
545 556  
546   - printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
  557 + printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
  558 + env->dmmuregs[1], env->dmmuregs[2]);
547 559 if ((env->lsu & DMMU_E) == 0) {
548 560 printf("DMMU disabled\n");
549 561 } else {
... ... @@ -565,7 +577,8 @@ void dump_mmu(CPUState *env)
565 577 break;
566 578 }
567 579 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
568   - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
  580 + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
  581 + ", %s, %s, %s, %s, ctx %" PRId64 "\n",
569 582 env->dtlb_tag[i] & ~0x1fffULL,
570 583 env->dtlb_tte[i] & 0x1ffffffe000ULL,
571 584 mask,
... ... @@ -597,7 +610,8 @@ void dump_mmu(CPUState *env)
597 610 break;
598 611 }
599 612 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
600   - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
  613 + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
  614 + ", %s, %s, %s, ctx %" PRId64 "\n",
601 615 env->itlb_tag[i] & ~0x1fffULL,
602 616 env->itlb_tte[i] & 0x1ffffffe000ULL,
603 617 mask,
... ... @@ -1206,7 +1220,8 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1206 1220 goto error;
1207 1221 }
1208 1222 } else {
1209   - fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
  1223 + fprintf(stderr, "feature string `%s' not in format "
  1224 + "(+feature|-feature|feature=xyz)\n", featurestr);
1210 1225 goto error;
1211 1226 }
1212 1227 featurestr = strtok(NULL, ",");
... ... @@ -1224,7 +1239,7 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1224 1239 return -1;
1225 1240 }
1226 1241  
1227   -void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
  1242 +void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1228 1243 {
1229 1244 unsigned int i;
1230 1245  
... ... @@ -1234,14 +1249,17 @@ void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1234 1249 sparc_defs[i].iu_version,
1235 1250 sparc_defs[i].fpu_version,
1236 1251 sparc_defs[i].mmu_version);
1237   - print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
1238   - print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
  1252 + print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
  1253 + ~sparc_defs[i].features, "-");
  1254 + print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
  1255 + sparc_defs[i].features, "+");
1239 1256 (*cpu_fprintf)(f, "\n");
1240 1257 }
1241 1258 (*cpu_fprintf)(f, "CPU feature flags (+/-): ");
1242 1259 print_features(f, cpu_fprintf, -1, NULL);
1243 1260 (*cpu_fprintf)(f, "\n");
1244   - (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version mmu_version\n");
  1261 + (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version "
  1262 + "mmu_version\n");
1245 1263 }
1246 1264  
1247 1265 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
... ... @@ -1252,7 +1270,8 @@ void cpu_dump_state(CPUState *env, FILE *f,
1252 1270 {
1253 1271 int i, x;
1254 1272  
1255   - cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
  1273 + cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
  1274 + env->npc);
1256 1275 cpu_fprintf(f, "General Registers:\n");
1257 1276 for (i = 0; i < 4; i++)
1258 1277 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
... ... @@ -1283,15 +1302,16 @@ void cpu_dump_state(CPUState *env, FILE *f,
1283 1302 #ifdef TARGET_SPARC64
1284 1303 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1285 1304 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1286   - cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
  1305 + cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
  1306 + "cleanwin %d cwp %d\n",
1287 1307 env->cansave, env->canrestore, env->otherwin, env->wstate,
1288 1308 env->cleanwin, NWINDOWS - 1 - env->cwp);
1289 1309 #else
1290   - cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
1291   - GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1292   - GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1293   - env->psrs?'S':'-', env->psrps?'P':'-',
1294   - env->psret?'E':'-', env->wim);
  1310 + cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
  1311 + GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
  1312 + GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
  1313 + env->psrs?'S':'-', env->psrps?'P':'-',
  1314 + env->psret?'E':'-', env->wim);
1295 1315 #endif
1296 1316 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
1297 1317 }
... ...
target-sparc/op_helper.c
  View file @77f193d
... ... @@ -795,15 +795,19 @@ GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
795 795 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
796 796 #endif
797 797  
798   -#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
  798 +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
  799 + defined(DEBUG_MXCC)
799 800 static void dump_mxcc(CPUState *env)
800 801 {
801 802 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
802   - env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
  803 + env->mxccdata[0], env->mxccdata[1],
  804 + env->mxccdata[2], env->mxccdata[3]);
803 805 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
804 806 " %016llx %016llx %016llx %016llx\n",
805   - env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
806   - env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
  807 + env->mxccregs[0], env->mxccregs[1],
  808 + env->mxccregs[2], env->mxccregs[3],
  809 + env->mxccregs[4], env->mxccregs[5],
  810 + env->mxccregs[6], env->mxccregs[7]);
807 811 }
808 812 #endif
809 813  
... ... @@ -851,32 +855,38 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
851 855 if (size == 8)
852 856 ret = env->mxccregs[3];
853 857 else
854   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  858 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  859 + size);
855 860 break;
856 861 case 0x01c00a04: /* MXCC control register */
857 862 if (size == 4)
858 863 ret = env->mxccregs[3];
859 864 else
860   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  865 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  866 + size);
861 867 break;
862 868 case 0x01c00c00: /* Module reset register */
863 869 if (size == 8) {
864 870 ret = env->mxccregs[5];
865 871 // should we do something here?
866 872 } else
867   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  873 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  874 + size);
868 875 break;
869 876 case 0x01c00f00: /* MBus port address register */
870 877 if (size == 8)
871 878 ret = env->mxccregs[7];
872 879 else
873   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  880 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  881 + size);
874 882 break;
875 883 default:
876   - DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
  884 + DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
  885 + size);
877 886 break;
878 887 }
879   - DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
  888 + DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
  889 + "addr = %08x -> ret = %08x,"
880 890 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
881 891 #ifdef DEBUG_MXCC
882 892 dump_mxcc(env);
... ... @@ -1050,76 +1060,97 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1050 1060 if (size == 8)
1051 1061 env->mxccdata[0] = val;
1052 1062 else
1053   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  1063 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1064 + size);
1054 1065 break;
1055 1066 case 0x01c00008: /* MXCC stream data register 1 */
1056 1067 if (size == 8)
1057 1068 env->mxccdata[1] = val;
1058 1069 else
1059   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  1070 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1071 + size);
1060 1072 break;
1061 1073 case 0x01c00010: /* MXCC stream data register 2 */
1062 1074 if (size == 8)
1063 1075 env->mxccdata[2] = val;
1064 1076 else
1065   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  1077 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1078 + size);
1066 1079 break;
1067 1080 case 0x01c00018: /* MXCC stream data register 3 */
1068 1081 if (size == 8)
1069 1082 env->mxccdata[3] = val;
1070 1083 else
1071   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  1084 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1085 + size);
1072 1086 break;
1073 1087 case 0x01c00100: /* MXCC stream source */
1074 1088 if (size == 8)
1075 1089 env->mxccregs[0] = val;
1076 1090 else
1077   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1078   - env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
1079   - env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
1080   - env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
1081   - env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
  1091 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1092 + size);
  1093 + env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
  1094 + 0);
  1095 + env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
  1096 + 8);
  1097 + env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
  1098 + 16);
  1099 + env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
  1100 + 24);
1082 1101 break;
1083 1102 case 0x01c00200: /* MXCC stream destination */
1084 1103 if (size == 8)
1085 1104 env->mxccregs[1] = val;
1086 1105 else
1087   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
1088   - stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
1089   - stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
1090   - stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
1091   - stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
  1106 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1107 + size);
  1108 + stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
  1109 + env->mxccdata[0]);
  1110 + stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
  1111 + env->mxccdata[1]);
  1112 + stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
  1113 + env->mxccdata[2]);
  1114 + stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
  1115 + env->mxccdata[3]);
1092 1116 break;
1093 1117 case 0x01c00a00: /* MXCC control register */
1094 1118 if (size == 8)
1095 1119 env->mxccregs[3] = val;
1096 1120 else
1097   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  1121 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1122 + size);
1098 1123 break;
1099 1124 case 0x01c00a04: /* MXCC control register */
1100 1125 if (size == 4)
1101   - env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val;
  1126 + env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL)
  1127 + | val;
1102 1128 else
1103   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  1129 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1130 + size);
1104 1131 break;
1105 1132 case 0x01c00e00: /* MXCC error register */
1106 1133 // writing a 1 bit clears the error
1107 1134 if (size == 8)
1108 1135 env->mxccregs[6] &= ~val;
1109 1136 else
1110   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  1137 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1138 + size);
1111 1139 break;
1112 1140 case 0x01c00f00: /* MBus port address register */
1113 1141 if (size == 8)
1114 1142 env->mxccregs[7] = val;
1115 1143 else
1116   - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
  1144 + DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
  1145 + size);
1117 1146 break;
1118 1147 default:
1119   - DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
  1148 + DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
  1149 + size);
1120 1150 break;
1121 1151 }
1122   - DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
  1152 + DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi,
  1153 + size, addr, val);
1123 1154 #ifdef DEBUG_MXCC
1124 1155 dump_mxcc(env);
1125 1156 #endif
... ... @@ -1192,7 +1223,8 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1192 1223 break;
1193 1224 }
1194 1225 if (oldreg != env->mmuregs[reg]) {
1195   - DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
  1226 + DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
  1227 + reg, oldreg, env->mmuregs[reg]);
1196 1228 }
1197 1229 #ifdef DEBUG_MMU
1198 1230 dump_mmu(env);
... ... @@ -1317,7 +1349,8 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1317 1349 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1318 1350 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1319 1351 // Turbosparc snoop RAM
1320   - case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic
  1352 + case 0x32: // store buffer control or Turbosparc page table
  1353 + // descriptor diagnostic
1321 1354 case 0x36: /* I-cache flash clear */
1322 1355 case 0x37: /* D-cache flash clear */
1323 1356 case 0x38: /* breakpoint diagnostics */
... ... @@ -1860,7 +1893,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1860 1893 // Mappings generated during D/I MMU disabled mode are
1861 1894 // invalid in normal mode
1862 1895 if (oldreg != env->lsu) {
1863   - DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
  1896 + DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
  1897 + oldreg, env->lsu);
1864 1898 #ifdef DEBUG_MMU
1865 1899 dump_mmu(env);
1866 1900 #endif
... ... @@ -1894,7 +1928,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1894 1928 }
1895 1929 env->immuregs[reg] = val;
1896 1930 if (oldreg != env->immuregs[reg]) {
1897   - DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
  1931 + DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
  1932 + PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1898 1933 }
1899 1934 #ifdef DEBUG_MMU
1900 1935 dump_mmu(env);
... ... @@ -1963,7 +1998,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1963 1998 }
1964 1999 env->dmmuregs[reg] = val;
1965 2000 if (oldreg != env->dmmuregs[reg]) {
1966   - DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
  2001 + DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
  2002 + PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1967 2003 }
1968 2004 #ifdef DEBUG_MMU
1969 2005 dump_mmu(env);
... ... @@ -2042,7 +2078,8 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2042 2078 }
2043 2079 helper_check_align(addr, 0x3f);
2044 2080 for (i = 0; i < 16; i++) {
2045   - *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0);
  2081 + *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
  2082 + 0);
2046 2083 addr += 4;
2047 2084 }
2048 2085  
... ... @@ -2697,7 +2734,8 @@ void do_interrupt(int intno)
2697 2734 #endif
2698 2735 #if !defined(CONFIG_USER_ONLY)
2699 2736 if (env->tl == MAXTL) {
2700   - cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
  2737 + cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
  2738 + env->exception_index);
2701 2739 return;
2702 2740 }
2703 2741 #endif
... ... @@ -2807,7 +2845,8 @@ void do_interrupt(int intno)
2807 2845 #endif
2808 2846 #if !defined(CONFIG_USER_ONLY)
2809 2847 if (env->psret == 0) {
2810   - cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
  2848 + cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
  2849 + env->exception_index);
2811 2850 return;
2812 2851 }
2813 2852 #endif
... ... @@ -2833,7 +2872,8 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2833 2872 #define MMUSUFFIX _mmu
2834 2873 #define ALIGNED_ONLY
2835 2874 #ifdef __s390__
2836   -# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
  2875 +# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & \
  2876 + 0x7fffffffUL))
2837 2877 #else
2838 2878 # define GETPC() (__builtin_return_address(0))
2839 2879 #endif
... ... @@ -2915,8 +2955,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
2915 2955 env = cpu_single_env;
2916 2956 #ifdef DEBUG_UNASSIGNED
2917 2957 if (is_asi)
2918   - printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from "
2919   - TARGET_FMT_lx "\n",
  2958 + printf("Unassigned mem %s access to " TARGET_FMT_plx
  2959 + " asi 0x%02x from " TARGET_FMT_lx "\n",
2920 2960 is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
2921 2961 env->pc);
2922 2962 else
... ... @@ -2955,8 +2995,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
2955 2995 generated code */
2956 2996 saved_env = env;
2957 2997 env = cpu_single_env;
2958   - printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
2959   - addr, env->pc);
  2998 + printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
  2999 + "\n", addr, env->pc);
2960 3000 env = saved_env;
2961 3001 #endif
2962 3002 if (is_exec)
... ...
target-sparc/translate.c
  View file @77f193d
... ... @@ -38,7 +38,8 @@
38 38 according to jump_pc[T2] */
39 39  
40 40 /* global register indexes */
41   -static TCGv cpu_env, cpu_T[2], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
  41 +static TCGv cpu_env, cpu_T[2], cpu_regwptr;
  42 +static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
42 43 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
43 44 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
44 45 #ifdef TARGET_SPARC64
... ... @@ -109,60 +110,78 @@ static void gen_op_store_FT0_fpr(unsigned int dst)
109 110 static void gen_op_load_fpr_DT0(unsigned int src)
110 111 {
111 112 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
112   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
  113 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
  114 + offsetof(CPU_DoubleU, l.upper));
113 115 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
114   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
  116 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
  117 + offsetof(CPU_DoubleU, l.lower));
115 118 }
116 119  
117 120 static void gen_op_load_fpr_DT1(unsigned int src)
118 121 {
119 122 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
120   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
  123 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
  124 + offsetof(CPU_DoubleU, l.upper));
121 125 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
122   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
  126 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
  127 + offsetof(CPU_DoubleU, l.lower));
123 128 }
124 129  
125 130 static void gen_op_store_DT0_fpr(unsigned int dst)
126 131 {
127   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
  132 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
  133 + offsetof(CPU_DoubleU, l.upper));
128 134 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
129   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
  135 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
  136 + offsetof(CPU_DoubleU, l.lower));
130 137 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
131 138 }
132 139  
133 140 static void gen_op_load_fpr_QT0(unsigned int src)
134 141 {
135 142 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
136   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
  143 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
  144 + offsetof(CPU_QuadU, l.upmost));
137 145 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
138   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
  146 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
  147 + offsetof(CPU_QuadU, l.upper));
139 148 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
140   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
  149 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
  150 + offsetof(CPU_QuadU, l.lower));
141 151 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
142   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
  152 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
  153 + offsetof(CPU_QuadU, l.lowest));
143 154 }
144 155  
145 156 static void gen_op_load_fpr_QT1(unsigned int src)
146 157 {
147 158 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
148   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
  159 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
  160 + offsetof(CPU_QuadU, l.upmost));
149 161 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
150   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
  162 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
  163 + offsetof(CPU_QuadU, l.upper));
151 164 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
152   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
  165 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
  166 + offsetof(CPU_QuadU, l.lower));
153 167 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
154   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
  168 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
  169 + offsetof(CPU_QuadU, l.lowest));
155 170 }
156 171  
157 172 static void gen_op_store_QT0_fpr(unsigned int dst)
158 173 {
159   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
  174 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
  175 + offsetof(CPU_QuadU, l.upmost));
160 176 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
161   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
  177 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
  178 + offsetof(CPU_QuadU, l.upper));
162 179 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
163   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
  180 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
  181 + offsetof(CPU_QuadU, l.lower));
164 182 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
165   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
  183 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
  184 + offsetof(CPU_QuadU, l.lowest));
166 185 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
167 186 }
168 187  
... ... @@ -1591,7 +1610,8 @@ static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1591 1610 return r_asi;
1592 1611 }
1593 1612  
1594   -static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
  1613 +static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
  1614 + int sign)
1595 1615 {
1596 1616 TCGv r_asi;
1597 1617  
... ... @@ -1664,7 +1684,8 @@ static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1664 1684 tcg_const_i32(8));
1665 1685 }
1666 1686  
1667   -static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
  1687 +static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
  1688 + int rd)
1668 1689 {
1669 1690 TCGv r_val1, r_asi;
1670 1691  
... ... @@ -1674,7 +1695,8 @@ static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1674 1695 tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1675 1696 }
1676 1697  
1677   -static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
  1698 +static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
  1699 + int rd)
1678 1700 {
1679 1701 TCGv r_asi;
1680 1702  
... ... @@ -1685,7 +1707,8 @@ static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd
1685 1707  
1686 1708 #elif !defined(CONFIG_USER_ONLY)
1687 1709  
1688   -static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
  1710 +static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
  1711 + int sign)
1689 1712 {
1690 1713 int asi;
1691 1714  
... ... @@ -1970,7 +1993,8 @@ static void disas_sparc_insn(DisasContext * dc)
1970 1993 SPARCv8 manual, rdy on the
1971 1994 microSPARC II */
1972 1995 #endif
1973   - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
  1996 + tcg_gen_ld_tl(cpu_dst, cpu_env,
  1997 + offsetof(CPUSPARCState, y));
1974 1998 gen_movl_TN_reg(rd, cpu_dst);
1975 1999 break;
1976 2000 #ifdef TARGET_SPARC64
... ... @@ -1979,7 +2003,8 @@ static void disas_sparc_insn(DisasContext * dc)
1979 2003 gen_movl_TN_reg(rd, cpu_dst);
1980 2004 break;
1981 2005 case 0x3: /* V9 rdasi */
1982   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
  2006 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2007 + offsetof(CPUSPARCState, asi));
1983 2008 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
1984 2009 gen_movl_TN_reg(rd, cpu_dst);
1985 2010 break;
... ... @@ -1999,7 +2024,8 @@ static void disas_sparc_insn(DisasContext * dc)
1999 2024 gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
2000 2025 break;
2001 2026 case 0x6: /* V9 rdfprs */
2002   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
  2027 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2028 + offsetof(CPUSPARCState, fprs));
2003 2029 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2004 2030 gen_movl_TN_reg(rd, cpu_dst);
2005 2031 break;
... ... @@ -2008,11 +2034,13 @@ static void disas_sparc_insn(DisasContext * dc)
2008 2034 case 0x13: /* Graphics Status */
2009 2035 if (gen_trap_ifnofpu(dc, cpu_cond))
2010 2036 goto jmp_insn;
2011   - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
  2037 + tcg_gen_ld_tl(cpu_dst, cpu_env,
  2038 + offsetof(CPUSPARCState, gsr));
2012 2039 gen_movl_TN_reg(rd, cpu_dst);
2013 2040 break;
2014 2041 case 0x17: /* Tick compare */
2015   - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr));
  2042 + tcg_gen_ld_tl(cpu_dst, cpu_env,
  2043 + offsetof(CPUSPARCState, tick_cmpr));
2016 2044 gen_movl_TN_reg(rd, cpu_dst);
2017 2045 break;
2018 2046 case 0x18: /* System tick */
... ... @@ -2028,7 +2056,8 @@ static void disas_sparc_insn(DisasContext * dc)
2028 2056 }
2029 2057 break;
2030 2058 case 0x19: /* System tick compare */
2031   - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr));
  2059 + tcg_gen_ld_tl(cpu_dst, cpu_env,
  2060 + offsetof(CPUSPARCState, stick_cmpr));
2032 2061 gen_movl_TN_reg(rd, cpu_dst);
2033 2062 break;
2034 2063 case 0x10: /* Performance Control */
... ... @@ -2059,20 +2088,24 @@ static void disas_sparc_insn(DisasContext * dc)
2059 2088 // gen_op_rdhtstate();
2060 2089 break;
2061 2090 case 3: // hintp
2062   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
  2091 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2092 + offsetof(CPUSPARCState, hintp));
2063 2093 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2064 2094 break;
2065 2095 case 5: // htba
2066   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
  2096 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2097 + offsetof(CPUSPARCState, htba));
2067 2098 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2068 2099 break;
2069 2100 case 6: // hver
2070   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
  2101 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2102 + offsetof(CPUSPARCState, hver));
2071 2103 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2072 2104 break;
2073 2105 case 31: // hstick_cmpr
2074 2106 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2075   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
  2107 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  2108 + offsetof(CPUSPARCState, hstick_cmpr));
2076 2109 break;
2077 2110 default:
2078 2111 goto illegal_insn;
... ... @@ -2143,62 +2176,75 @@ static void disas_sparc_insn(DisasContext * dc)
2143 2176 }
2144 2177 break;
2145 2178 case 5: // tba
2146   - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
  2179 + tcg_gen_ld_tl(cpu_dst, cpu_env,
  2180 + offsetof(CPUSPARCState, tbr));
2147 2181 break;
2148 2182 case 6: // pstate
2149   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
  2183 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2184 + offsetof(CPUSPARCState, pstate));
2150 2185 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2151 2186 break;
2152 2187 case 7: // tl
2153   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
  2188 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2189 + offsetof(CPUSPARCState, tl));
2154 2190 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2155 2191 break;
2156 2192 case 8: // pil
2157   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
  2193 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2194 + offsetof(CPUSPARCState, psrpil));
2158 2195 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2159 2196 break;
2160 2197 case 9: // cwp
2161 2198 tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2162 2199 break;
2163 2200 case 10: // cansave
2164   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
  2201 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2202 + offsetof(CPUSPARCState, cansave));
2165 2203 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2166 2204 break;
2167 2205 case 11: // canrestore
2168   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
  2206 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2207 + offsetof(CPUSPARCState, canrestore));
2169 2208 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2170 2209 break;
2171 2210 case 12: // cleanwin
2172   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
  2211 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2212 + offsetof(CPUSPARCState, cleanwin));
2173 2213 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2174 2214 break;
2175 2215 case 13: // otherwin
2176   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
  2216 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2217 + offsetof(CPUSPARCState, otherwin));
2177 2218 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2178 2219 break;
2179 2220 case 14: // wstate
2180   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
  2221 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2222 + offsetof(CPUSPARCState, wstate));
2181 2223 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2182 2224 break;
2183 2225 case 16: // UA2005 gl
2184   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
  2226 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2227 + offsetof(CPUSPARCState, gl));
2185 2228 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2186 2229 break;
2187 2230 case 26: // UA2005 strand status
2188 2231 if (!hypervisor(dc))
2189 2232 goto priv_insn;
2190   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
  2233 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2234 + offsetof(CPUSPARCState, ssr));
2191 2235 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2192 2236 break;
2193 2237 case 31: // ver
2194   - tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version));
  2238 + tcg_gen_ld_tl(cpu_dst, cpu_env,
  2239 + offsetof(CPUSPARCState, version));
2195 2240 break;
2196 2241 case 15: // fq
2197 2242 default:
2198 2243 goto illegal_insn;
2199 2244 }
2200 2245 #else
2201   - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
  2246 + tcg_gen_ld_i32(cpu_tmp32, cpu_env,
  2247 + offsetof(CPUSPARCState, wim));
2202 2248 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2203 2249 #endif
2204 2250 gen_movl_TN_reg(rd, cpu_dst);
... ... @@ -2603,8 +2649,10 @@ static void disas_sparc_insn(DisasContext * dc)
2603 2649 gen_fcond(r_cond, fcc, cond); \
2604 2650 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2605 2651 tcg_const_tl(0), l1); \
2606   - glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2607   - glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
  2652 + glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
  2653 + (glue(size_FDQ, FPREG(rs2))); \
  2654 + glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
  2655 + (glue(size_FDQ, FPREG(rd))); \
2608 2656 gen_set_label(l1); \
2609 2657 }
2610 2658 case 0x001: /* V9 fmovscc %fcc0 */
... ... @@ -2659,8 +2707,10 @@ static void disas_sparc_insn(DisasContext * dc)
2659 2707 gen_cond(r_cond, icc, cond); \
2660 2708 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
2661 2709 tcg_const_tl(0), l1); \
2662   - glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2663   - glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
  2710 + glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
  2711 + (glue(size_FDQ, FPREG(rs2))); \
  2712 + glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
  2713 + (glue(size_FDQ, FPREG(rd))); \
2664 2714 gen_set_label(l1); \
2665 2715 }
2666 2716  
... ... @@ -2916,13 +2966,15 @@ static void disas_sparc_insn(DisasContext * dc)
2916 2966 #endif
2917 2967 case 0xe:
2918 2968 CHECK_IU_FEATURE(dc, DIV);
2919   - tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2);
  2969 + tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
  2970 + cpu_src2);
2920 2971 if (xop & 0x10)
2921 2972 gen_op_div_cc(cpu_dst);
2922 2973 break;
2923 2974 case 0xf:
2924 2975 CHECK_IU_FEATURE(dc, DIV);
2925   - tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2);
  2976 + tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
  2977 + cpu_src2);
2926 2978 if (xop & 0x10)
2927 2979 gen_op_div_cc(cpu_dst);
2928 2980 break;
... ... @@ -2976,7 +3028,8 @@ static void disas_sparc_insn(DisasContext * dc)
2976 3028 switch(rd) {
2977 3029 case 0: /* wry */
2978 3030 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2979   - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
  3031 + tcg_gen_st_tl(cpu_dst, cpu_env,
  3032 + offsetof(CPUSPARCState, y));
2980 3033 break;
2981 3034 #ifndef TARGET_SPARC64
2982 3035 case 0x01 ... 0x0f: /* undefined in the
... ... @@ -2996,12 +3049,14 @@ static void disas_sparc_insn(DisasContext * dc)
2996 3049 case 0x3: /* V9 wrasi */
2997 3050 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2998 3051 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2999   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
  3052 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3053 + offsetof(CPUSPARCState, asi));
3000 3054 break;
3001 3055 case 0x6: /* V9 wrfprs */
3002 3056 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3003 3057 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3004   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
  3058 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3059 + offsetof(CPUSPARCState, fprs));
3005 3060 save_state(dc, cpu_cond);
3006 3061 gen_op_next_insn();
3007 3062 tcg_gen_exit_tb(0);
... ... @@ -3017,7 +3072,8 @@ static void disas_sparc_insn(DisasContext * dc)
3017 3072 if (gen_trap_ifnofpu(dc, cpu_cond))
3018 3073 goto jmp_insn;
3019 3074 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3020   - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
  3075 + tcg_gen_st_tl(cpu_dst, cpu_env,
  3076 + offsetof(CPUSPARCState, gsr));
3021 3077 break;
3022 3078 case 0x17: /* Tick compare */
3023 3079 #if !defined(CONFIG_USER_ONLY)
... ... @@ -3029,8 +3085,9 @@ static void disas_sparc_insn(DisasContext * dc)
3029 3085  
3030 3086 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3031 3087 cpu_src2);
3032   - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3033   - tick_cmpr));
  3088 + tcg_gen_st_tl(cpu_dst, cpu_env,
  3089 + offsetof(CPUSPARCState,
  3090 + tick_cmpr));
3034 3091 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3035 3092 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3036 3093 offsetof(CPUState, tick));
... ... @@ -3065,8 +3122,9 @@ static void disas_sparc_insn(DisasContext * dc)
3065 3122  
3066 3123 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3067 3124 cpu_src2);
3068   - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3069   - stick_cmpr));
  3125 + tcg_gen_st_tl(cpu_dst, cpu_env,
  3126 + offsetof(CPUSPARCState,
  3127 + stick_cmpr));
3070 3128 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3071 3129 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3072 3130 offsetof(CPUState, stick));
... ... @@ -3076,7 +3134,8 @@ static void disas_sparc_insn(DisasContext * dc)
3076 3134 break;
3077 3135  
3078 3136 case 0x10: /* Performance Control */
3079   - case 0x11: /* Performance Instrumentation Counter */
  3137 + case 0x11: /* Performance Instrumentation
  3138 + Counter */
3080 3139 case 0x12: /* Dispatch Control */
3081 3140 case 0x14: /* Softint set */
3082 3141 case 0x15: /* Softint clear */
... ... @@ -3155,7 +3214,8 @@ static void disas_sparc_insn(DisasContext * dc)
3155 3214 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3156 3215 offsetof(CPUState, tsptr));
3157 3216 tcg_gen_st_tl(cpu_dst, r_tsptr,
3158   - offsetof(trap_state, tstate));
  3217 + offsetof(trap_state,
  3218 + tstate));
3159 3219 }
3160 3220 break;
3161 3221 case 3: // tt
... ... @@ -3181,7 +3241,8 @@ static void disas_sparc_insn(DisasContext * dc)
3181 3241 }
3182 3242 break;
3183 3243 case 5: // tba
3184   - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
  3244 + tcg_gen_st_tl(cpu_dst, cpu_env,
  3245 + offsetof(CPUSPARCState, tbr));
3185 3246 break;
3186 3247 case 6: // pstate
3187 3248 save_state(dc, cpu_cond);
... ... @@ -3192,52 +3253,69 @@ static void disas_sparc_insn(DisasContext * dc)
3192 3253 break;
3193 3254 case 7: // tl
3194 3255 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3195   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
  3256 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3257 + offsetof(CPUSPARCState, tl));
3196 3258 break;
3197 3259 case 8: // pil
3198 3260 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3199   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
  3261 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3262 + offsetof(CPUSPARCState,
  3263 + psrpil));
3200 3264 break;
3201 3265 case 9: // cwp
3202 3266 tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3203 3267 break;
3204 3268 case 10: // cansave
3205 3269 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3206   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
  3270 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3271 + offsetof(CPUSPARCState,
  3272 + cansave));
3207 3273 break;
3208 3274 case 11: // canrestore
3209 3275 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3210   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
  3276 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3277 + offsetof(CPUSPARCState,
  3278 + canrestore));
3211 3279 break;
3212 3280 case 12: // cleanwin
3213 3281 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3214   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
  3282 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3283 + offsetof(CPUSPARCState,
  3284 + cleanwin));
3215 3285 break;
3216 3286 case 13: // otherwin
3217 3287 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3218   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
  3288 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3289 + offsetof(CPUSPARCState,
  3290 + otherwin));
3219 3291 break;
3220 3292 case 14: // wstate
3221 3293 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3222   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
  3294 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3295 + offsetof(CPUSPARCState,
  3296 + wstate));
3223 3297 break;
3224 3298 case 16: // UA2005 gl
3225 3299 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3226   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
  3300 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3301 + offsetof(CPUSPARCState, gl));
3227 3302 break;
3228 3303 case 26: // UA2005 strand status
3229 3304 if (!hypervisor(dc))
3230 3305 goto priv_insn;
3231 3306 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3232   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
  3307 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3308 + offsetof(CPUSPARCState, ssr));
3233 3309 break;
3234 3310 default:
3235 3311 goto illegal_insn;
3236 3312 }
3237 3313 #else
3238   - tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1));
  3314 + tcg_gen_andi_tl(cpu_dst, cpu_dst,
  3315 + ((1 << NWINDOWS) - 1));
3239 3316 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3240   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
  3317 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3318 + offsetof(CPUSPARCState, wim));
3241 3319 #endif
3242 3320 }
3243 3321 break;
... ... @@ -3247,7 +3325,8 @@ static void disas_sparc_insn(DisasContext * dc)
3247 3325 if (!supervisor(dc))
3248 3326 goto priv_insn;
3249 3327 tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3250   - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
  3328 + tcg_gen_st_tl(cpu_dst, cpu_env,
  3329 + offsetof(CPUSPARCState, tbr));
3251 3330 #else
3252 3331 if (!hypervisor(dc))
3253 3332 goto priv_insn;
... ... @@ -3265,18 +3344,21 @@ static void disas_sparc_insn(DisasContext * dc)
3265 3344 break;
3266 3345 case 3: // hintp
3267 3346 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3268   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
  3347 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3348 + offsetof(CPUSPARCState, hintp));
3269 3349 break;
3270 3350 case 5: // htba
3271 3351 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3272   - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
  3352 + tcg_gen_st_i32(cpu_tmp32, cpu_env,
  3353 + offsetof(CPUSPARCState, htba));
3273 3354 break;
3274 3355 case 31: // hstick_cmpr
3275 3356 {
3276 3357 TCGv r_tickptr;
3277 3358  
3278   - tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3279   - hstick_cmpr));
  3359 + tcg_gen_st_tl(cpu_dst, cpu_env,
  3360 + offsetof(CPUSPARCState,
  3361 + hstick_cmpr));
3280 3362 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3281 3363 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3282 3364 offsetof(CPUState, hstick));
... ... @@ -3854,7 +3936,8 @@ static void disas_sparc_insn(DisasContext * dc)
3854 3936 }
3855 3937 tcg_gen_helper_0_0(helper_restore);
3856 3938 gen_mov_pc_npc(dc, cpu_cond);
3857   - tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
  3939 + tcg_gen_helper_0_2(helper_check_align, cpu_dst,
  3940 + tcg_const_i32(3));
3858 3941 tcg_gen_mov_tl(cpu_npc, cpu_dst);
3859 3942 dc->npc = DYNAMIC_PC;
3860 3943 goto jmp_insn;
... ... @@ -3877,7 +3960,8 @@ static void disas_sparc_insn(DisasContext * dc)
3877 3960 {
3878 3961 gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
3879 3962 gen_mov_pc_npc(dc, cpu_cond);
3880   - tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
  3963 + tcg_gen_helper_0_2(helper_check_align, cpu_dst,
  3964 + tcg_const_i32(3));
3881 3965 tcg_gen_mov_tl(cpu_npc, cpu_dst);
3882 3966 dc->npc = DYNAMIC_PC;
3883 3967 }
... ... @@ -3888,7 +3972,8 @@ static void disas_sparc_insn(DisasContext * dc)
3888 3972 if (!supervisor(dc))
3889 3973 goto priv_insn;
3890 3974 gen_mov_pc_npc(dc, cpu_cond);
3891   - tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
  3975 + tcg_gen_helper_0_2(helper_check_align, cpu_dst,
  3976 + tcg_const_i32(3));
3892 3977 tcg_gen_mov_tl(cpu_npc, cpu_dst);
3893 3978 dc->npc = DYNAMIC_PC;
3894 3979 tcg_gen_helper_0_0(helper_rett);
... ... @@ -4006,9 +4091,11 @@ static void disas_sparc_insn(DisasContext * dc)
4006 4091 case 0xd: /* ldstub -- XXX: should be atomically */
4007 4092 ABI32_MASK(cpu_addr);
4008 4093 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4009   - tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx);
  4094 + tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr,
  4095 + dc->mem_idx);
4010 4096 break;
4011   - case 0x0f: /* swap register with memory. Also atomically */
  4097 + case 0x0f: /* swap register with memory. Also
  4098 + atomically */
4012 4099 CHECK_IU_FEATURE(dc, SWAP);
4013 4100 gen_movl_reg_TN(rd, cpu_val);
4014 4101 ABI32_MASK(cpu_addr);
... ... @@ -4090,7 +4177,8 @@ static void disas_sparc_insn(DisasContext * dc)
4090 4177 save_state(dc, cpu_cond);
4091 4178 gen_ldstub_asi(cpu_val, cpu_addr, insn);
4092 4179 break;
4093   - case 0x1f: /* swap reg with alt. memory. Also atomically */
  4180 + case 0x1f: /* swap reg with alt. memory. Also
  4181 + atomically */
4094 4182 CHECK_IU_FEATURE(dc, SWAP);
4095 4183 #ifndef TARGET_SPARC64
4096 4184 if (IS_IMM)
... ... @@ -4581,7 +4669,8 @@ void gen_intermediate_code_init(CPUSPARCState *env)
4581 4669 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4582 4670 TCG_AREG0, offsetof(CPUState, t1), "T1");
4583 4671 cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4584   - TCG_AREG0, offsetof(CPUState, cond), "cond");
  4672 + TCG_AREG0, offsetof(CPUState, cond),
  4673 + "cond");
4585 4674 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4586 4675 TCG_AREG0, offsetof(CPUState, cc_src),
4587 4676 "cc_src");
... ...