gwj / at91sam9263 · Commits

Commit e0353fe250eacac23104ff7fe466cd6533536509

Authored by blueswir1
1 parent 36cd9210

Add SparcStation-10 machine 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2571 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 78 additions and 13 deletions
hw/slavio_intctl.c
  View file @e0353fe
... ... @@ -54,6 +54,7 @@ typedef struct SLAVIO_INTCTLState {
54 54 uint64_t irq_count[32];
55 55 #endif
56 56 CPUState *cpu_envs[MAX_CPUS];
  57 + const uint32_t *intbit_to_level;
57 58 } SLAVIO_INTCTLState;
58 59  
59 60 #define INTCTL_MAXADDR 0xf
... ... @@ -208,11 +209,6 @@ void slavio_irq_info(void *opaque)
208 209 #endif
209 210 }
210 211  
211   -static const uint32_t intbit_to_level[32] = {
212   - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
213   - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
214   -};
215   -
216 212 static void slavio_check_interrupts(void *opaque)
217 213 {
218 214 CPUState *env;
... ... @@ -225,8 +221,8 @@ static void slavio_check_interrupts(void *opaque)
225 221 if (pending && !(s->intregm_disabled & 0x80000000)) {
226 222 for (i = 0; i < 32; i++) {
227 223 if (pending & (1 << i)) {
228   - if (max < intbit_to_level[i])
229   - max = intbit_to_level[i];
  224 + if (max < s->intbit_to_level[i])
  225 + max = s->intbit_to_level[i];
230 226 }
231 227 }
232 228 env = s->cpu_envs[s->target_cpu];
... ... @@ -288,7 +284,7 @@ void slavio_pic_set_irq(void *opaque, int irq, int level)
288 284 DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
289 285 if (irq < 32) {
290 286 uint32_t mask = 1 << irq;
291   - uint32_t pil = intbit_to_level[irq];
  287 + uint32_t pil = s->intbit_to_level[irq];
292 288 if (pil > 0) {
293 289 if (level) {
294 290 s->intregm_pending |= mask;
... ... @@ -313,7 +309,7 @@ void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
313 309 return;
314 310 }
315 311 if (irq < 32) {
316   - uint32_t pil = intbit_to_level[irq];
  312 + uint32_t pil = s->intbit_to_level[irq];
317 313 if (pil > 0) {
318 314 if (level) {
319 315 s->intreg_pending[cpu] |= 1 << pil;
... ... @@ -375,7 +371,8 @@ void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
375 371 s->cpu_envs[cpu] = env;
376 372 }
377 373  
378   -void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
  374 +void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
  375 + const uint32_t *intbit_to_level)
379 376 {
380 377 int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
381 378 SLAVIO_INTCTLState *s;
... ... @@ -384,6 +381,7 @@ void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
384 381 if (!s)
385 382 return NULL;
386 383  
  384 + s->intbit_to_level = intbit_to_level;
387 385 for (i = 0; i < MAX_CPUS; i++) {
388 386 slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
389 387 cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
... ...
hw/sun4m.c
  View file @e0353fe
... ... @@ -59,6 +59,7 @@ struct hwdef {
59 59 int intctl_g_intr, esp_irq, le_irq, cpu_irq, clock_irq, clock1_irq;
60 60 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
61 61 int machine_id; // For NVRAM
  62 + uint32_t intbit_to_level[32];
62 63 };
63 64  
64 65 /* TSC handling */
... ... @@ -238,7 +239,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
238 239  
239 240 iommu = iommu_init(hwdef->iommu_base);
240 241 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
241   - hwdef->intctl_base + 0x10000);
  242 + hwdef->intctl_base + 0x10000,
  243 + &hwdef->intbit_to_level[0]);
242 244 for(i = 0; i < smp_cpus; i++) {
243 245 slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
244 246 }
... ... @@ -375,6 +377,43 @@ static const struct hwdef hwdefs[] = {
375 377 .me_irq = 30,
376 378 .cs_irq = 5,
377 379 .machine_id = 0x80,
  380 + .intbit_to_level = {
  381 + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
  382 + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
  383 + },
  384 + },
  385 + /* SS-10 */
  386 + /* XXX: Replace with real values */
  387 + {
  388 + .iommu_base = 0x10000000,
  389 + .tcx_base = 0x50000000,
  390 + .cs_base = 0x6c000000,
  391 + .slavio_base = 0x71000000,
  392 + .ms_kb_base = 0x71000000,
  393 + .serial_base = 0x71100000,
  394 + .nvram_base = 0x71200000,
  395 + .fd_base = 0x71400000,
  396 + .counter_base = 0x71d00000,
  397 + .intctl_base = 0x71e00000,
  398 + .dma_base = 0x78400000,
  399 + .esp_base = 0x78800000,
  400 + .le_base = 0x78c00000,
  401 + .vram_size = 0x00100000,
  402 + .nvram_size = 0x2000,
  403 + .esp_irq = 18,
  404 + .le_irq = 16,
  405 + .clock_irq = 7,
  406 + .clock1_irq = 19,
  407 + .ms_kb_irq = 14,
  408 + .ser_irq = 15,
  409 + .fd_irq = 22,
  410 + .me_irq = 30,
  411 + .cs_irq = 5,
  412 + .machine_id = 0x73,
  413 + .intbit_to_level = {
  414 + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
  415 + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
  416 + },
378 417 },
379 418 };
380 419  
... ... @@ -403,8 +442,27 @@ static void ss5_init(int ram_size, int vga_ram_size, int boot_device,
403 442 0);
404 443 }
405 444  
  445 +/* SPARCstation 10 hardware initialisation */
  446 +static void ss10_init(int ram_size, int vga_ram_size, int boot_device,
  447 + DisplayState *ds, const char **fd_filename, int snapshot,
  448 + const char *kernel_filename, const char *kernel_cmdline,
  449 + const char *initrd_filename, const char *cpu_model)
  450 +{
  451 + if (cpu_model == NULL)
  452 + cpu_model = "TI SuperSparc II";
  453 + sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
  454 + kernel_cmdline, initrd_filename, cpu_model,
  455 + 1);
  456 +}
  457 +
406 458 QEMUMachine ss5_machine = {
407 459 "SS-5",
408 460 "Sun4m platform, SPARCstation 5",
409 461 ss5_init,
410 462 };
  463 +
  464 +QEMUMachine ss10_machine = {
  465 + "SS-10",
  466 + "Sun4m platform, SPARCstation 10",
  467 + ss10_init,
  468 +};
... ...
target-sparc/translate.c
  View file @e0353fe
... ... @@ -2874,6 +2874,13 @@ static const sparc_def_t sparc_defs[] = {
2874 2874 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
2875 2875 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
2876 2876 },
  2877 + {
  2878 + /* XXX: Replace with real values */
  2879 + .name = "TI SuperSparc II",
  2880 + .iu_version = 0x40000000,
  2881 + .fpu_version = 0x00000000,
  2882 + .mmu_version = 0x00000000,
  2883 + },
2877 2884 #endif
2878 2885 };
2879 2886  
... ...
... ... @@ -6691,6 +6691,7 @@ void register_machines(void)
6691 6691 qemu_register_machine(&sun4u_machine);
6692 6692 #else
6693 6693 qemu_register_machine(&ss5_machine);
  6694 + qemu_register_machine(&ss10_machine);
6694 6695 #endif
6695 6696 #elif defined(TARGET_ARM)
6696 6697 qemu_register_machine(&integratorcp_machine);
... ...
... ... @@ -1143,7 +1143,7 @@ extern CPUReadMemoryFunc *PPC_io_read[];
1143 1143 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1144 1144  
1145 1145 /* sun4m.c */
1146   -extern QEMUMachine ss5_machine;
  1146 +extern QEMUMachine ss5_machine, ss10_machine;
1147 1147 void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
1148 1148  
1149 1149 /* iommu.c */
... ... @@ -1169,7 +1169,8 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
1169 1169 unsigned long vram_offset, int vram_size, int width, int height);
1170 1170  
1171 1171 /* slavio_intctl.c */
1172   -void *slavio_intctl_init(uint32_t addr, uint32_t addrg);
  1172 +void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
  1173 + const uint32_t *intbit_to_level);
1173 1174 void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
1174 1175 void slavio_pic_info(void *opaque);
1175 1176 void slavio_irq_info(void *opaque);
... ...