gwj / at91sam9263 · Commits

Commit ee76f82edb8ec8d68c93f1f6eff95793cdb28c74

Authored by blueswir1
1 parent 7d85892b

Initial support for SS-2 (Sun4c) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3870 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 7 changed files with 438 additions and 8 deletions
Makefile.target
  View file @ee76f82
... ... @@ -486,7 +486,7 @@ VL_OBJS+= cirrus_vga.o parallel.o ptimer.o
486 486 else
487 487 VL_OBJS+= sun4m.o tcx.o pcnet.o iommu.o m48t59.o slavio_intctl.o
488 488 VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o sparc32_dma.o
489   -VL_OBJS+= cs4231.o ptimer.o eccmemctl.o sbi.o
  489 +VL_OBJS+= cs4231.o ptimer.o eccmemctl.o sbi.o sun4c_intctl.o
490 490 endif
491 491 endif
492 492 ifeq ($(TARGET_BASE_ARCH), arm)
... ...
hw/boards.h
  View file @ee76f82
... ... @@ -53,6 +53,7 @@ extern QEMUMachine r2d_machine;
53 53  
54 54 /* sun4m.c */
55 55 extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine, ss20_machine;
  56 +extern QEMUMachine ss2_machine;
56 57 extern QEMUMachine ss1000_machine, ss2000_machine;
57 58  
58 59 /* sun4u.c */
... ...
hw/sun4c_intctl.c 0 → 100644
  View file @ee76f82
  1 +/*
  2 + * QEMU Sparc Sun4c interrupt controller emulation
  3 + *
  4 + * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +#include "hw.h"
  25 +#include "sun4m.h"
  26 +#include "console.h"
  27 +//#define DEBUG_IRQ_COUNT
  28 +//#define DEBUG_IRQ
  29 +
  30 +#ifdef DEBUG_IRQ
  31 +#define DPRINTF(fmt, args...) \
  32 +do { printf("IRQ: " fmt , ##args); } while (0)
  33 +#else
  34 +#define DPRINTF(fmt, args...)
  35 +#endif
  36 +
  37 +/*
  38 + * Registers of interrupt controller in sun4c.
  39 + *
  40 + */
  41 +
  42 +#define MAX_PILS 16
  43 +
  44 +typedef struct Sun4c_INTCTLState {
  45 +#ifdef DEBUG_IRQ_COUNT
  46 + uint64_t irq_count;
  47 +#endif
  48 + qemu_irq *cpu_irqs;
  49 + const uint32_t *intbit_to_level;
  50 + uint32_t pil_out;
  51 + uint8_t reg;
  52 + uint8_t pending;
  53 +} Sun4c_INTCTLState;
  54 +
  55 +#define INTCTL_MAXADDR 0
  56 +#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  57 +
  58 +static void sun4c_check_interrupts(void *opaque);
  59 +
  60 +static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
  61 +{
  62 + Sun4c_INTCTLState *s = opaque;
  63 + uint32_t ret;
  64 +
  65 + ret = s->reg;
  66 + DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
  67 +
  68 + return ret;
  69 +}
  70 +
  71 +static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  72 +{
  73 + Sun4c_INTCTLState *s = opaque;
  74 +
  75 + DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
  76 + val &= 0xbf;
  77 + s->reg = val;
  78 + sun4c_check_interrupts(s);
  79 +}
  80 +
  81 +static CPUReadMemoryFunc *sun4c_intctl_mem_read[3] = {
  82 + sun4c_intctl_mem_readb,
  83 + sun4c_intctl_mem_readb,
  84 + sun4c_intctl_mem_readb,
  85 +};
  86 +
  87 +static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3] = {
  88 + sun4c_intctl_mem_writeb,
  89 + sun4c_intctl_mem_writeb,
  90 + sun4c_intctl_mem_writeb,
  91 +};
  92 +
  93 +void sun4c_pic_info(void *opaque)
  94 +{
  95 + Sun4c_INTCTLState *s = opaque;
  96 +
  97 + term_printf("master: pending 0x%2.2x, enabled 0x%2.2x\n", s->pending, s->reg);
  98 +}
  99 +
  100 +void sun4c_irq_info(void *opaque)
  101 +{
  102 +#ifndef DEBUG_IRQ_COUNT
  103 + term_printf("irq statistic code not compiled.\n");
  104 +#else
  105 + Sun4c_INTCTLState *s = opaque;
  106 + int64_t count;
  107 +
  108 + term_printf("IRQ statistics:\n");
  109 + count = s->irq_count[i];
  110 + if (count > 0)
  111 + term_printf("%2d: %" PRId64 "\n", i, count);
  112 +#endif
  113 +}
  114 +
  115 +static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
  116 +
  117 +static void sun4c_check_interrupts(void *opaque)
  118 +{
  119 + Sun4c_INTCTLState *s = opaque;
  120 + uint32_t pil_pending;
  121 + unsigned int i;
  122 +
  123 + DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
  124 + pil_pending = 0;
  125 + if (s->pending && !(s->reg & 0x80000000)) {
  126 + for (i = 0; i < 8; i++) {
  127 + if (s->pending & (1 << i))
  128 + pil_pending |= 1 << intbit_to_level[i];
  129 + }
  130 + }
  131 +
  132 + for (i = 0; i < MAX_PILS; i++) {
  133 + if (pil_pending & (1 << i)) {
  134 + if (!(s->pil_out & (1 << i)))
  135 + qemu_irq_raise(s->cpu_irqs[i]);
  136 + } else {
  137 + if (s->pil_out & (1 << i))
  138 + qemu_irq_lower(s->cpu_irqs[i]);
  139 + }
  140 + }
  141 + s->pil_out = pil_pending;
  142 +}
  143 +
  144 +/*
  145 + * "irq" here is the bit number in the system interrupt register
  146 + */
  147 +static void sun4c_set_irq(void *opaque, int irq, int level)
  148 +{
  149 + Sun4c_INTCTLState *s = opaque;
  150 + uint32_t mask = 1 << irq;
  151 + uint32_t pil = intbit_to_level[irq];
  152 +
  153 + DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
  154 + level);
  155 + if (pil > 0) {
  156 + if (level) {
  157 +#ifdef DEBUG_IRQ_COUNT
  158 + s->irq_count[pil]++;
  159 +#endif
  160 + s->pending |= mask;
  161 + } else {
  162 + s->pending &= ~mask;
  163 + }
  164 + sun4c_check_interrupts(s);
  165 + }
  166 +}
  167 +
  168 +static void sun4c_intctl_save(QEMUFile *f, void *opaque)
  169 +{
  170 + Sun4c_INTCTLState *s = opaque;
  171 +
  172 + qemu_put_8s(f, &s->reg);
  173 + qemu_put_8s(f, &s->pending);
  174 +}
  175 +
  176 +static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id)
  177 +{
  178 + Sun4c_INTCTLState *s = opaque;
  179 +
  180 + if (version_id != 1)
  181 + return -EINVAL;
  182 +
  183 + qemu_get_8s(f, &s->reg);
  184 + qemu_get_8s(f, &s->pending);
  185 + sun4c_check_interrupts(s);
  186 +
  187 + return 0;
  188 +}
  189 +
  190 +static void sun4c_intctl_reset(void *opaque)
  191 +{
  192 + Sun4c_INTCTLState *s = opaque;
  193 +
  194 + s->reg = 1;
  195 + s->pending = 0;
  196 + sun4c_check_interrupts(s);
  197 +}
  198 +
  199 +void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
  200 + qemu_irq *parent_irq)
  201 +{
  202 + int sun4c_intctl_io_memory;
  203 + Sun4c_INTCTLState *s;
  204 +
  205 + s = qemu_mallocz(sizeof(Sun4c_INTCTLState));
  206 + if (!s)
  207 + return NULL;
  208 +
  209 + sun4c_intctl_io_memory = cpu_register_io_memory(0, sun4c_intctl_mem_read,
  210 + sun4c_intctl_mem_write, s);
  211 + cpu_register_physical_memory(addr, INTCTL_SIZE, sun4c_intctl_io_memory);
  212 + s->cpu_irqs = parent_irq;
  213 +
  214 + register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,
  215 + sun4c_intctl_load, s);
  216 +
  217 + qemu_register_reset(sun4c_intctl_reset, s);
  218 + *irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);
  219 +
  220 + sun4c_intctl_reset(s);
  221 + return s;
  222 +}
  223 +
... ...
hw/sun4m.c
  View file @ee76f82
1 1 /*
2   - * QEMU Sun4m & Sun4d System Emulator
  2 + * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 3 *
4 4 * Copyright (c) 2003-2005 Fabrice Bellard
5 5 *
... ... @@ -51,6 +51,13 @@
51 51 * SPARCcenter 2000
52 52 * SPARCserver 1000
53 53 *
  54 + * Sun4c architecture was used in the following machines:
  55 + * SPARCstation 1/1+, SPARCserver 1/1+
  56 + * SPARCstation SLC
  57 + * SPARCstation IPC
  58 + * SPARCstation ELC
  59 + * SPARCstation IPX
  60 + *
54 61 * See for example: http://www.sunhelp.org/faq/sunref1.html
55 62 */
56 63  
... ... @@ -79,6 +86,7 @@ struct hwdef {
79 86 target_phys_addr_t tcx_base, cs_base, power_base;
80 87 target_phys_addr_t ecc_base;
81 88 uint32_t ecc_version;
  89 + target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
82 90 long vram_size, nvram_size;
83 91 // IRQ numbers are not PIL ones, but master interrupt controller register
84 92 // bit numbers
... ... @@ -521,6 +529,142 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
521 529 ecc_init(hwdef->ecc_base, hwdef->ecc_version);
522 530 }
523 531  
  532 +static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
  533 + const char *boot_device,
  534 + DisplayState *ds, const char *kernel_filename,
  535 + const char *kernel_cmdline,
  536 + const char *initrd_filename, const char *cpu_model)
  537 +{
  538 + CPUState *env;
  539 + unsigned int i;
  540 + void *iommu, *espdma, *ledma, *main_esp, *nvram;
  541 + qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
  542 + qemu_irq *esp_reset, *le_reset;
  543 + unsigned long prom_offset, kernel_size;
  544 + int ret;
  545 + char buf[1024];
  546 + BlockDriverState *fd[MAX_FD];
  547 + int index;
  548 +
  549 + /* init CPU */
  550 + if (!cpu_model)
  551 + cpu_model = hwdef->default_cpu_model;
  552 +
  553 + env = cpu_init(cpu_model);
  554 + if (!env) {
  555 + fprintf(stderr, "Unable to find Sparc CPU definition\n");
  556 + exit(1);
  557 + }
  558 +
  559 + cpu_sparc_set_id(env, 0);
  560 +
  561 + qemu_register_reset(main_cpu_reset, env);
  562 + register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
  563 + cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
  564 +
  565 + /* allocate RAM */
  566 + if ((uint64_t)RAM_size > hwdef->max_mem) {
  567 + fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
  568 + (unsigned int)RAM_size / (1024 * 1024),
  569 + (unsigned int)hwdef->max_mem / (1024 * 1024));
  570 + exit(1);
  571 + }
  572 + cpu_register_physical_memory(0, RAM_size, 0);
  573 +
  574 + /* load boot prom */
  575 + prom_offset = RAM_size + hwdef->vram_size;
  576 + cpu_register_physical_memory(hwdef->slavio_base,
  577 + (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
  578 + TARGET_PAGE_MASK,
  579 + prom_offset | IO_MEM_ROM);
  580 +
  581 + if (bios_name == NULL)
  582 + bios_name = PROM_FILENAME;
  583 + snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
  584 + ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
  585 + if (ret < 0 || ret > PROM_SIZE_MAX)
  586 + ret = load_image(buf, phys_ram_base + prom_offset);
  587 + if (ret < 0 || ret > PROM_SIZE_MAX) {
  588 + fprintf(stderr, "qemu: could not load prom '%s'\n",
  589 + buf);
  590 + exit(1);
  591 + }
  592 + prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
  593 +
  594 + /* set up devices */
  595 + slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
  596 + &slavio_irq, cpu_irqs);
  597 +
  598 + iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version);
  599 +
  600 + espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
  601 + iommu, &espdma_irq, &esp_reset);
  602 +
  603 + ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
  604 + slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
  605 + &le_reset);
  606 +
  607 + if (graphic_depth != 8 && graphic_depth != 24) {
  608 + fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
  609 + exit (1);
  610 + }
  611 + tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
  612 + hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
  613 +
  614 + if (nd_table[0].model == NULL
  615 + || strcmp(nd_table[0].model, "lance") == 0) {
  616 + lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
  617 + } else if (strcmp(nd_table[0].model, "?") == 0) {
  618 + fprintf(stderr, "qemu: Supported NICs: lance\n");
  619 + exit (1);
  620 + } else {
  621 + fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
  622 + exit (1);
  623 + }
  624 +
  625 + nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
  626 + hwdef->nvram_size, 8);
  627 +
  628 + slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
  629 + nographic);
  630 + // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
  631 + // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
  632 + slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
  633 + serial_hds[1], serial_hds[0]);
  634 +
  635 + if (hwdef->fd_base != (target_phys_addr_t)-1) {
  636 + /* there is zero or one floppy drive */
  637 + fd[1] = fd[0] = NULL;
  638 + index = drive_get_index(IF_FLOPPY, 0, 0);
  639 + if (index != -1)
  640 + fd[0] = drives_table[index].bdrv;
  641 +
  642 + sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd);
  643 + }
  644 +
  645 + if (drive_get_max_bus(IF_SCSI) > 0) {
  646 + fprintf(stderr, "qemu: too many SCSI bus\n");
  647 + exit(1);
  648 + }
  649 +
  650 + main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
  651 + esp_reset);
  652 +
  653 + for (i = 0; i < ESP_MAX_DEVS; i++) {
  654 + index = drive_get_index(IF_SCSI, 0, i);
  655 + if (index == -1)
  656 + continue;
  657 + esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
  658 + }
  659 +
  660 + kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
  661 + initrd_filename);
  662 +
  663 + nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
  664 + boot_device, RAM_size, kernel_size, graphic_width,
  665 + graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
  666 +}
  667 +
524 668 static const struct hwdef hwdefs[] = {
525 669 /* SS-5 */
526 670 {
... ... @@ -540,6 +684,8 @@ static const struct hwdef hwdefs[] = {
540 684 .le_base = 0x78c00000,
541 685 .power_base = 0x7a000000,
542 686 .ecc_base = -1,
  687 + .sun4c_intctl_base = -1,
  688 + .sun4c_counter_base = -1,
543 689 .vram_size = 0x00100000,
544 690 .nvram_size = 0x2000,
545 691 .esp_irq = 18,
... ... @@ -579,6 +725,8 @@ static const struct hwdef hwdefs[] = {
579 725 .power_base = 0xefa000000ULL,
580 726 .ecc_base = 0xf00000000ULL,
581 727 .ecc_version = 0x10000000, // version 0, implementation 1
  728 + .sun4c_intctl_base = -1,
  729 + .sun4c_counter_base = -1,
582 730 .vram_size = 0x00100000,
583 731 .nvram_size = 0x2000,
584 732 .esp_irq = 18,
... ... @@ -618,6 +766,8 @@ static const struct hwdef hwdefs[] = {
618 766 .power_base = 0xefa000000ULL,
619 767 .ecc_base = 0xf00000000ULL,
620 768 .ecc_version = 0x00000000, // version 0, implementation 0
  769 + .sun4c_intctl_base = -1,
  770 + .sun4c_counter_base = -1,
621 771 .vram_size = 0x00100000,
622 772 .nvram_size = 0x2000,
623 773 .esp_irq = 18,
... ... @@ -657,6 +807,8 @@ static const struct hwdef hwdefs[] = {
657 807 .power_base = 0xefa000000ULL,
658 808 .ecc_base = 0xf00000000ULL,
659 809 .ecc_version = 0x20000000, // version 0, implementation 2
  810 + .sun4c_intctl_base = -1,
  811 + .sun4c_counter_base = -1,
660 812 .vram_size = 0x00100000,
661 813 .nvram_size = 0x2000,
662 814 .esp_irq = 18,
... ... @@ -677,6 +829,39 @@ static const struct hwdef hwdefs[] = {
677 829 .max_mem = 0xffffffff, // XXX actually first 62GB ok
678 830 .default_cpu_model = "TI SuperSparc II",
679 831 },
  832 + /* SS-2 */
  833 + {
  834 + .iommu_base = 0xf8000000,
  835 + .tcx_base = 0xfe000000,
  836 + .cs_base = -1,
  837 + .slavio_base = 0xf6000000,
  838 + .ms_kb_base = 0xf0000000,
  839 + .serial_base = 0xf1000000,
  840 + .nvram_base = 0xf2000000,
  841 + .fd_base = 0xf7200000,
  842 + .counter_base = -1,
  843 + .intctl_base = -1,
  844 + .dma_base = 0xf8400000,
  845 + .esp_base = 0xf8800000,
  846 + .le_base = 0xf8c00000,
  847 + .power_base = -1,
  848 + .sun4c_intctl_base = 0xf5000000,
  849 + .sun4c_counter_base = 0xf3000000,
  850 + .vram_size = 0x00100000,
  851 + .nvram_size = 0x2000, // XXX 0x800,
  852 + .esp_irq = 2,
  853 + .le_irq = 3,
  854 + .clock_irq = 5,
  855 + .clock1_irq = 7,
  856 + .ms_kb_irq = 1,
  857 + .ser_irq = 1,
  858 + .fd_irq = 1,
  859 + .me_irq = 1,
  860 + .cs_irq = -1,
  861 + .machine_id = 0x55,
  862 + .max_mem = 0x10000000,
  863 + .default_cpu_model = "Cypress CY7C601",
  864 + },
680 865 };
681 866  
682 867 /* SPARCstation 5 hardware initialisation */
... ... @@ -719,6 +904,16 @@ static void ss20_init(int RAM_size, int vga_ram_size,
719 904 kernel_cmdline, initrd_filename, cpu_model);
720 905 }
721 906  
  907 +/* SPARCstation 2 hardware initialisation */
  908 +static void ss2_init(int RAM_size, int vga_ram_size,
  909 + const char *boot_device, DisplayState *ds,
  910 + const char *kernel_filename, const char *kernel_cmdline,
  911 + const char *initrd_filename, const char *cpu_model)
  912 +{
  913 + sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
  914 + kernel_cmdline, initrd_filename, cpu_model);
  915 +}
  916 +
722 917 QEMUMachine ss5_machine = {
723 918 "SS-5",
724 919 "Sun4m platform, SPARCstation 5",
... ... @@ -743,6 +938,11 @@ QEMUMachine ss20_machine = {
743 938 ss20_init,
744 939 };
745 940  
  941 +QEMUMachine ss2_machine = {
  942 + "SS-2",
  943 + "Sun4c platform, SPARCstation 2",
  944 + ss2_init,
  945 +};
746 946  
747 947 static const struct sun4d_hwdef sun4d_hwdefs[] = {
748 948 /* SS-1000 */
... ...
hw/sun4m.h
  View file @ee76f82
... ... @@ -38,6 +38,10 @@ void slavio_irq_info(void *opaque);
38 38 void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
39 39 qemu_irq **parent_irq);
40 40  
  41 +/* sun4c_intctl.c */
  42 +void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
  43 + qemu_irq *parent_irq);
  44 +
41 45 /* slavio_timer.c */
42 46 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
43 47 qemu_irq *cpu_irqs, unsigned int num_cpus);
... ...
qemu-doc.texi
  View file @ee76f82
... ... @@ -74,7 +74,7 @@ For system emulation, the following hardware targets are supported:
74 74 @item PREP (PowerPC processor)
75 75 @item G3 BW PowerMac (PowerPC processor)
76 76 @item Mac99 PowerMac (PowerPC processor, in progress)
77   -@item Sun4m/Sun4d (32-bit Sparc processor)
  77 +@item Sun4m/Sun4c/Sun4d (32-bit Sparc processor)
78 78 @item Sun4u (64-bit Sparc processor, in progress)
79 79 @item Malta board (32-bit and 64-bit MIPS processors)
80 80 @item ARM Integrator/CP (ARM)
... ... @@ -2026,10 +2026,11 @@ More information is available at
2026 2026 @section Sparc32 System emulator
2027 2027  
2028 2028 Use the executable @file{qemu-system-sparc} to simulate a SPARCstation
2029   -5, SPARCstation 10, SPARCstation 20, SPARCserver 600MP (sun4m architecture),
2030   -SPARCserver 1000, or SPARCcenter 2000 (sun4d architecture). The
2031   -emulation is somewhat complete. SMP up to 16 CPUs is supported, but
2032   -Linux limits the number of usable CPUs to 4.
  2029 +5, SPARCstation 10, SPARCstation 20, SPARCserver 600MP (sun4m
  2030 +architecture), SPARCstation 2 (sun4c architecture), SPARCserver 1000,
  2031 +or SPARCcenter 2000 (sun4d architecture). The emulation is somewhat
  2032 +complete. SMP up to 16 CPUs is supported, but Linux limits the number
  2033 +of usable CPUs to 4.
2033 2034  
2034 2035 QEMU emulates the following sun4m/sun4d peripherals:
2035 2036  
... ... @@ -2086,7 +2087,7 @@ qemu-system-sparc -prom-env &#39;auto-boot?=false&#39; \
2086 2087 -prom-env 'boot-device=sd(0,2,0):d' -prom-env 'boot-args=linux single'
2087 2088 @end example
2088 2089  
2089   -@item -M [SS-5|SS-10|SS-20|SS-600MP|SS-1000|SS-2000]
  2090 +@item -M [SS-5|SS-10|SS-20|SS-600MP|SS-2|SS-1000|SS-2000]
2090 2091  
2091 2092 Set the emulated machine type. Default is SS-5.
2092 2093  
... ...
... ... @@ -7892,6 +7892,7 @@ static void register_machines(void)
7892 7892 qemu_register_machine(&ss10_machine);
7893 7893 qemu_register_machine(&ss600mp_machine);
7894 7894 qemu_register_machine(&ss20_machine);
  7895 + qemu_register_machine(&ss2_machine);
7895 7896 qemu_register_machine(&ss1000_machine);
7896 7897 qemu_register_machine(&ss2000_machine);
7897 7898 #endif
... ...