gwj / at91sam9263 · Commits

Commit 7d85892b9be865631bd6ab9a732e0fc5629b8797

Authored by blueswir1
1 parent 8543e2cf

Initial support for Sun4d machines (SS-1000, SS-2000) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3869 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 8 changed files with 455 additions and 16 deletions
Makefile.target
  View file @7d85892
... ... @@ -486,7 +486,7 @@ VL_OBJS+= cirrus_vga.o parallel.o ptimer.o
486 486 else
487 487 VL_OBJS+= sun4m.o tcx.o pcnet.o iommu.o m48t59.o slavio_intctl.o
488 488 VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o sparc32_dma.o
489   -VL_OBJS+= cs4231.o ptimer.o eccmemctl.o
  489 +VL_OBJS+= cs4231.o ptimer.o eccmemctl.o sbi.o
490 490 endif
491 491 endif
492 492 ifeq ($(TARGET_BASE_ARCH), arm)
... ...
hw/boards.h
  View file @7d85892
... ... @@ -53,6 +53,7 @@ extern QEMUMachine r2d_machine;
53 53  
54 54 /* sun4m.c */
55 55 extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine, ss20_machine;
  56 +extern QEMUMachine ss1000_machine, ss2000_machine;
56 57  
57 58 /* sun4u.c */
58 59 extern QEMUMachine sun4u_machine;
... ...
hw/sbi.c 0 → 100644
  View file @7d85892
  1 +/*
  2 + * QEMU Sparc SBI interrupt controller emulation
  3 + *
  4 + * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +#include "hw.h"
  25 +#include "sun4m.h"
  26 +#include "console.h"
  27 +
  28 +//#define DEBUG_IRQ
  29 +
  30 +#ifdef DEBUG_IRQ
  31 +#define DPRINTF(fmt, args...) \
  32 +do { printf("IRQ: " fmt , ##args); } while (0)
  33 +#else
  34 +#define DPRINTF(fmt, args...)
  35 +#endif
  36 +
  37 +#define MAX_CPUS 16
  38 +
  39 +#define SBI_NREGS 16
  40 +
  41 +typedef struct SBIState {
  42 + uint32_t regs[SBI_NREGS];
  43 + uint32_t intreg_pending[MAX_CPUS];
  44 + qemu_irq *cpu_irqs[MAX_CPUS];
  45 + uint32_t pil_out[MAX_CPUS];
  46 +} SBIState;
  47 +
  48 +#define SBI_SIZE (SBI_NREGS * 4)
  49 +#define SBI_MASK (SBI_SIZE - 1)
  50 +
  51 +static void sbi_check_interrupts(void *opaque)
  52 +{
  53 +}
  54 +
  55 +static void sbi_set_irq(void *opaque, int irq, int level)
  56 +{
  57 +}
  58 +
  59 +static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level)
  60 +{
  61 +}
  62 +
  63 +static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
  64 +{
  65 + SBIState *s = opaque;
  66 + uint32_t saddr, ret;
  67 +
  68 + saddr = (addr & SBI_MASK) >> 2;
  69 + switch (saddr) {
  70 + default:
  71 + ret = s->regs[saddr];
  72 + break;
  73 + }
  74 + DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
  75 +
  76 + return ret;
  77 +}
  78 +
  79 +static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  80 +{
  81 + SBIState *s = opaque;
  82 + uint32_t saddr;
  83 +
  84 + saddr = (addr & SBI_MASK) >> 2;
  85 + DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
  86 + switch (saddr) {
  87 + default:
  88 + s->regs[saddr] = val;
  89 + break;
  90 + }
  91 +}
  92 +
  93 +static CPUReadMemoryFunc *sbi_mem_read[3] = {
  94 + sbi_mem_readl,
  95 + sbi_mem_readl,
  96 + sbi_mem_readl,
  97 +};
  98 +
  99 +static CPUWriteMemoryFunc *sbi_mem_write[3] = {
  100 + sbi_mem_writel,
  101 + sbi_mem_writel,
  102 + sbi_mem_writel,
  103 +};
  104 +
  105 +static void sbi_save(QEMUFile *f, void *opaque)
  106 +{
  107 + SBIState *s = opaque;
  108 + unsigned int i;
  109 +
  110 + for (i = 0; i < MAX_CPUS; i++) {
  111 + qemu_put_be32s(f, &s->intreg_pending[i]);
  112 + }
  113 +}
  114 +
  115 +static int sbi_load(QEMUFile *f, void *opaque, int version_id)
  116 +{
  117 + SBIState *s = opaque;
  118 + unsigned int i;
  119 +
  120 + if (version_id != 1)
  121 + return -EINVAL;
  122 +
  123 + for (i = 0; i < MAX_CPUS; i++) {
  124 + qemu_get_be32s(f, &s->intreg_pending[i]);
  125 + }
  126 + sbi_check_interrupts(s);
  127 +
  128 + return 0;
  129 +}
  130 +
  131 +static void sbi_reset(void *opaque)
  132 +{
  133 + SBIState *s = opaque;
  134 + unsigned int i;
  135 +
  136 + for (i = 0; i < MAX_CPUS; i++) {
  137 + s->intreg_pending[i] = 0;
  138 + }
  139 + sbi_check_interrupts(s);
  140 +}
  141 +
  142 +void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
  143 + qemu_irq **parent_irq)
  144 +{
  145 + unsigned int i;
  146 + int sbi_io_memory;
  147 + SBIState *s;
  148 +
  149 + s = qemu_mallocz(sizeof(SBIState));
  150 + if (!s)
  151 + return NULL;
  152 +
  153 + for (i = 0; i < MAX_CPUS; i++) {
  154 + s->cpu_irqs[i] = parent_irq[i];
  155 + }
  156 +
  157 + sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s);
  158 + cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
  159 +
  160 + register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
  161 + qemu_register_reset(sbi_reset, s);
  162 + *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
  163 + *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
  164 + sbi_reset(s);
  165 +
  166 + return s;
  167 +}
... ...
hw/sun4m.c
  View file @7d85892
1 1 /*
2   - * QEMU Sun4m System Emulator
  2 + * QEMU Sun4m & Sun4d System Emulator
3 3 *
4 4 * Copyright (c) 2003-2005 Fabrice Bellard
5 5 *
... ... @@ -46,6 +46,11 @@
46 46 * SPARCstation 20/xx, SPARCserver 20
47 47 * SPARCstation 4
48 48 *
  49 + * Sun4d architecture was used in the following machines:
  50 + *
  51 + * SPARCcenter 2000
  52 + * SPARCserver 1000
  53 + *
49 54 * See for example: http://www.sunhelp.org/faq/sunref1.html
50 55 */
51 56  
... ... @@ -86,6 +91,26 @@ struct hwdef {
86 91 const char * const default_cpu_model;
87 92 };
88 93  
  94 +#define MAX_IOUNITS 5
  95 +
  96 +struct sun4d_hwdef {
  97 + target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
  98 + target_phys_addr_t counter_base, nvram_base, ms_kb_base;
  99 + target_phys_addr_t serial_base;
  100 + target_phys_addr_t espdma_base, esp_base;
  101 + target_phys_addr_t ledma_base, le_base;
  102 + target_phys_addr_t tcx_base;
  103 + target_phys_addr_t sbi_base;
  104 + unsigned long vram_size, nvram_size;
  105 + // IRQ numbers are not PIL ones, but SBI register bit numbers
  106 + int esp_irq, le_irq, clock_irq, clock1_irq;
  107 + int ser_irq, ms_kb_irq, me_irq;
  108 + int machine_id; // For NVRAM
  109 + uint32_t iounit_version;
  110 + uint64_t max_mem;
  111 + const char * const default_cpu_model;
  112 +};
  113 +
89 114 /* TSC handling */
90 115  
91 116 uint64_t cpu_get_tsc()
... ... @@ -122,7 +147,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
122 147 const char *boot_devices, uint32_t RAM_size,
123 148 uint32_t kernel_size,
124 149 int width, int height, int depth,
125   - int machine_id)
  150 + int machine_id, const char *arch)
126 151 {
127 152 unsigned int i;
128 153 uint32_t start, end;
... ... @@ -140,7 +165,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
140 165 header->nvram_size = cpu_to_be16(0x2000);
141 166 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
142 167 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
143   - strcpy(header->arch, "sun4m");
  168 + strcpy(header->arch, arch);
144 169 header->nb_cpus = smp_cpus & 0xff;
145 170 header->RAM0_base = 0;
146 171 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
... ... @@ -203,12 +228,14 @@ static void *slavio_intctl;
203 228  
204 229 void pic_info()
205 230 {
206   - slavio_pic_info(slavio_intctl);
  231 + if (slavio_intctl)
  232 + slavio_pic_info(slavio_intctl);
207 233 }
208 234  
209 235 void irq_info()
210 236 {
211   - slavio_irq_info(slavio_intctl);
  237 + if (slavio_intctl)
  238 + slavio_irq_info(slavio_intctl);
212 239 }
213 240  
214 241 void cpu_check_irqs(CPUState *env)
... ... @@ -488,7 +515,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
488 515  
489 516 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
490 517 boot_device, RAM_size, kernel_size, graphic_width,
491   - graphic_height, graphic_depth, hwdef->machine_id);
  518 + graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
492 519  
493 520 if (hwdef->ecc_base != (target_phys_addr_t)-1)
494 521 ecc_init(hwdef->ecc_base, hwdef->ecc_version);
... ... @@ -716,3 +743,242 @@ QEMUMachine ss20_machine = {
716 743 ss20_init,
717 744 };
718 745  
  746 +
  747 +static const struct sun4d_hwdef sun4d_hwdefs[] = {
  748 + /* SS-1000 */
  749 + {
  750 + .iounit_bases = {
  751 + 0xfe0200000ULL,
  752 + 0xfe1200000ULL,
  753 + 0xfe2200000ULL,
  754 + 0xfe3200000ULL,
  755 + -1,
  756 + },
  757 + .tcx_base = 0x820000000ULL,
  758 + .slavio_base = 0xf00000000ULL,
  759 + .ms_kb_base = 0xf00240000ULL,
  760 + .serial_base = 0xf00200000ULL,
  761 + .nvram_base = 0xf00280000ULL,
  762 + .counter_base = 0xf00300000ULL,
  763 + .espdma_base = 0x800081000ULL,
  764 + .esp_base = 0x800080000ULL,
  765 + .ledma_base = 0x800040000ULL,
  766 + .le_base = 0x800060000ULL,
  767 + .sbi_base = 0xf02800000ULL,
  768 + .vram_size = 0x00100000,
  769 + .nvram_size = 0x2000,
  770 + .esp_irq = 3,
  771 + .le_irq = 4,
  772 + .clock_irq = 14,
  773 + .clock1_irq = 10,
  774 + .ms_kb_irq = 12,
  775 + .ser_irq = 12,
  776 + .machine_id = 0x80,
  777 + .iounit_version = 0x03000000,
  778 + .max_mem = 0xffffffff, // XXX actually first 62GB ok
  779 + .default_cpu_model = "TI SuperSparc II",
  780 + },
  781 + /* SS-2000 */
  782 + {
  783 + .iounit_bases = {
  784 + 0xfe0200000ULL,
  785 + 0xfe1200000ULL,
  786 + 0xfe2200000ULL,
  787 + 0xfe3200000ULL,
  788 + 0xfe4200000ULL,
  789 + },
  790 + .tcx_base = 0x820000000ULL,
  791 + .slavio_base = 0xf00000000ULL,
  792 + .ms_kb_base = 0xf00240000ULL,
  793 + .serial_base = 0xf00200000ULL,
  794 + .nvram_base = 0xf00280000ULL,
  795 + .counter_base = 0xf00300000ULL,
  796 + .espdma_base = 0x800081000ULL,
  797 + .esp_base = 0x800080000ULL,
  798 + .ledma_base = 0x800040000ULL,
  799 + .le_base = 0x800060000ULL,
  800 + .sbi_base = 0xf02800000ULL,
  801 + .vram_size = 0x00100000,
  802 + .nvram_size = 0x2000,
  803 + .esp_irq = 3,
  804 + .le_irq = 4,
  805 + .clock_irq = 14,
  806 + .clock1_irq = 10,
  807 + .ms_kb_irq = 12,
  808 + .ser_irq = 12,
  809 + .machine_id = 0x80,
  810 + .iounit_version = 0x03000000,
  811 + .max_mem = 0xffffffff, // XXX actually first 62GB ok
  812 + .default_cpu_model = "TI SuperSparc II",
  813 + },
  814 +};
  815 +
  816 +static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size,
  817 + const char *boot_device,
  818 + DisplayState *ds, const char *kernel_filename,
  819 + const char *kernel_cmdline,
  820 + const char *initrd_filename, const char *cpu_model)
  821 +{
  822 + CPUState *env, *envs[MAX_CPUS];
  823 + unsigned int i;
  824 + void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
  825 + qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
  826 + *espdma_irq, *ledma_irq;
  827 + qemu_irq *esp_reset, *le_reset;
  828 + unsigned long prom_offset, kernel_size;
  829 + int ret;
  830 + char buf[1024];
  831 + int index;
  832 +
  833 + /* init CPUs */
  834 + if (!cpu_model)
  835 + cpu_model = hwdef->default_cpu_model;
  836 +
  837 + for (i = 0; i < smp_cpus; i++) {
  838 + env = cpu_init(cpu_model);
  839 + if (!env) {
  840 + fprintf(stderr, "Unable to find Sparc CPU definition\n");
  841 + exit(1);
  842 + }
  843 + cpu_sparc_set_id(env, i);
  844 + envs[i] = env;
  845 + if (i == 0) {
  846 + qemu_register_reset(main_cpu_reset, env);
  847 + } else {
  848 + qemu_register_reset(secondary_cpu_reset, env);
  849 + env->halted = 1;
  850 + }
  851 + register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
  852 + cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
  853 + env->prom_addr = hwdef->slavio_base;
  854 + }
  855 +
  856 + for (i = smp_cpus; i < MAX_CPUS; i++)
  857 + cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
  858 +
  859 + /* allocate RAM */
  860 + if ((uint64_t)RAM_size > hwdef->max_mem) {
  861 + fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
  862 + (unsigned int)RAM_size / (1024 * 1024),
  863 + (unsigned int)(hwdef->max_mem / (1024 * 1024)));
  864 + exit(1);
  865 + }
  866 + cpu_register_physical_memory(0, RAM_size, 0);
  867 +
  868 + /* load boot prom */
  869 + prom_offset = RAM_size + hwdef->vram_size;
  870 + cpu_register_physical_memory(hwdef->slavio_base,
  871 + (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
  872 + TARGET_PAGE_MASK,
  873 + prom_offset | IO_MEM_ROM);
  874 +
  875 + if (bios_name == NULL)
  876 + bios_name = PROM_FILENAME;
  877 + snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
  878 + ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
  879 + if (ret < 0 || ret > PROM_SIZE_MAX)
  880 + ret = load_image(buf, phys_ram_base + prom_offset);
  881 + if (ret < 0 || ret > PROM_SIZE_MAX) {
  882 + fprintf(stderr, "qemu: could not load prom '%s'\n",
  883 + buf);
  884 + exit(1);
  885 + }
  886 +
  887 + /* set up devices */
  888 + sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
  889 +
  890 + for (i = 0; i < MAX_IOUNITS; i++)
  891 + if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
  892 + iounits[i] = iommu_init(hwdef->iounit_bases[i], hwdef->iounit_version);
  893 +
  894 + espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
  895 + iounits[0], &espdma_irq, &esp_reset);
  896 +
  897 + ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
  898 + iounits[0], &ledma_irq, &le_reset);
  899 +
  900 + if (graphic_depth != 8 && graphic_depth != 24) {
  901 + fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
  902 + exit (1);
  903 + }
  904 + tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
  905 + hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
  906 +
  907 + if (nd_table[0].model == NULL
  908 + || strcmp(nd_table[0].model, "lance") == 0) {
  909 + lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
  910 + } else if (strcmp(nd_table[0].model, "?") == 0) {
  911 + fprintf(stderr, "qemu: Supported NICs: lance\n");
  912 + exit (1);
  913 + } else {
  914 + fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
  915 + exit (1);
  916 + }
  917 +
  918 + nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
  919 + hwdef->nvram_size, 8);
  920 +
  921 + slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
  922 + sbi_cpu_irq, smp_cpus);
  923 +
  924 + slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
  925 + nographic);
  926 + // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
  927 + // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
  928 + slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
  929 + serial_hds[1], serial_hds[0]);
  930 +
  931 + if (drive_get_max_bus(IF_SCSI) > 0) {
  932 + fprintf(stderr, "qemu: too many SCSI bus\n");
  933 + exit(1);
  934 + }
  935 +
  936 + main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
  937 + esp_reset);
  938 +
  939 + for (i = 0; i < ESP_MAX_DEVS; i++) {
  940 + index = drive_get_index(IF_SCSI, 0, i);
  941 + if (index == -1)
  942 + continue;
  943 + esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
  944 + }
  945 +
  946 + kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
  947 + initrd_filename);
  948 +
  949 + nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
  950 + boot_device, RAM_size, kernel_size, graphic_width,
  951 + graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
  952 +}
  953 +
  954 +/* SPARCserver 1000 hardware initialisation */
  955 +static void ss1000_init(int RAM_size, int vga_ram_size,
  956 + const char *boot_device, DisplayState *ds,
  957 + const char *kernel_filename, const char *kernel_cmdline,
  958 + const char *initrd_filename, const char *cpu_model)
  959 +{
  960 + sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
  961 + kernel_cmdline, initrd_filename, cpu_model);
  962 +}
  963 +
  964 +/* SPARCcenter 2000 hardware initialisation */
  965 +static void ss2000_init(int RAM_size, int vga_ram_size,
  966 + const char *boot_device, DisplayState *ds,
  967 + const char *kernel_filename, const char *kernel_cmdline,
  968 + const char *initrd_filename, const char *cpu_model)
  969 +{
  970 + sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
  971 + kernel_cmdline, initrd_filename, cpu_model);
  972 +}
  973 +
  974 +QEMUMachine ss1000_machine = {
  975 + "SS-1000",
  976 + "Sun4d platform, SPARCserver 1000",
  977 + ss1000_init,
  978 +};
  979 +
  980 +QEMUMachine ss2000_machine = {
  981 + "SS-2000",
  982 + "Sun4d platform, SPARCcenter 2000",
  983 + ss2000_init,
  984 +};
... ...
hw/sun4m.h
  View file @7d85892
... ... @@ -34,6 +34,10 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
34 34 void slavio_pic_info(void *opaque);
35 35 void slavio_irq_info(void *opaque);
36 36  
  37 +/* sbi.c */
  38 +void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
  39 + qemu_irq **parent_irq);
  40 +
37 41 /* slavio_timer.c */
38 42 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
39 43 qemu_irq *cpu_irqs, unsigned int num_cpus);
... ...
qemu-doc.texi
  View file @7d85892
... ... @@ -74,7 +74,7 @@ For system emulation, the following hardware targets are supported:
74 74 @item PREP (PowerPC processor)
75 75 @item G3 BW PowerMac (PowerPC processor)
76 76 @item Mac99 PowerMac (PowerPC processor, in progress)
77   -@item Sun4m (32-bit Sparc processor)
  77 +@item Sun4m/Sun4d (32-bit Sparc processor)
78 78 @item Sun4u (64-bit Sparc processor, in progress)
79 79 @item Malta board (32-bit and 64-bit MIPS processors)
80 80 @item ARM Integrator/CP (ARM)
... ... @@ -2026,15 +2026,16 @@ More information is available at
2026 2026 @section Sparc32 System emulator
2027 2027  
2028 2028 Use the executable @file{qemu-system-sparc} to simulate a SPARCstation
2029   -5, SPARCstation 10, or SPARCserver 600MP (sun4m architecture). The
  2029 +5, SPARCstation 10, SPARCstation 20, SPARCserver 600MP (sun4m architecture),
  2030 +SPARCserver 1000, or SPARCcenter 2000 (sun4d architecture). The
2030 2031 emulation is somewhat complete. SMP up to 16 CPUs is supported, but
2031 2032 Linux limits the number of usable CPUs to 4.
2032 2033  
2033   -QEMU emulates the following sun4m peripherals:
  2034 +QEMU emulates the following sun4m/sun4d peripherals:
2034 2035  
2035 2036 @itemize @minus
2036 2037 @item
2037   -IOMMU
  2038 +IOMMU or IO-UNITs
2038 2039 @item
2039 2040 TCX Frame buffer
2040 2041 @item
... ... @@ -2054,7 +2055,7 @@ CS4231 sound device (only on SS-5, not working yet)
2054 2055  
2055 2056 The number of peripherals is fixed in the architecture. Maximum
2056 2057 memory size depends on the machine type, for SS-5 it is 256MB and for
2057   -SS-10 and SS-600MP 2047MB.
  2058 +others 2047MB.
2058 2059  
2059 2060 Since version 0.8.2, QEMU uses OpenBIOS
2060 2061 @url{http://www.openbios.org/}. OpenBIOS is a free (GPL v2) portable
... ... @@ -2085,7 +2086,7 @@ qemu-system-sparc -prom-env &#39;auto-boot?=false&#39; \
2085 2086 -prom-env 'boot-device=sd(0,2,0):d' -prom-env 'boot-args=linux single'
2086 2087 @end example
2087 2088  
2088   -@item -M [SS-5|SS-10|SS-600MP]
  2089 +@item -M [SS-5|SS-10|SS-20|SS-600MP|SS-1000|SS-2000]
2089 2090  
2090 2091 Set the emulated machine type. Default is SS-5.
2091 2092  
... ...
target-sparc/op_helper.c
  View file @7d85892
... ... @@ -418,8 +418,7 @@ void helper_ld_asi(int asi, int size, int sign)
418 418 break;
419 419 }
420 420 break;
421   - case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
422   - case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
  421 + case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
423 422 switch(size) {
424 423 case 1:
425 424 ret = ldub_phys((target_phys_addr_t)T0
... ... @@ -445,7 +444,6 @@ void helper_ld_asi(int asi, int size, int sign)
445 444 case 0x39: /* data cache diagnostic register */
446 445 ret = 0;
447 446 break;
448   - case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
449 447 default:
450 448 do_unassigned_access(T0, 0, 0, asi);
451 449 ret = 0;
... ...
... ... @@ -7892,6 +7892,8 @@ static void register_machines(void)
7892 7892 qemu_register_machine(&ss10_machine);
7893 7893 qemu_register_machine(&ss600mp_machine);
7894 7894 qemu_register_machine(&ss20_machine);
  7895 + qemu_register_machine(&ss1000_machine);
  7896 + qemu_register_machine(&ss2000_machine);
7895 7897 #endif
7896 7898 #elif defined(TARGET_ARM)
7897 7899 qemu_register_machine(&integratorcp_machine);
... ...