gwj / at91sam9263 · Commits

Commit a526a31cb4e02ecdf81c26c3f2f97db4a6089418

Authored by blueswir1
1 parent 18be8d77

Add more machine definitions 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4020 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 297 additions and 0 deletions
hw/boards.h
  View file @a526a31
... ... @@ -53,6 +53,8 @@ extern QEMUMachine r2d_machine;
53 53  
54 54 /* sun4m.c */
55 55 extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine, ss20_machine;
  56 +extern QEMUMachine voyager_machine, ss_lx_machine, ss4_machine, scls_machine;
  57 +extern QEMUMachine sbook_machine;
56 58 extern QEMUMachine ss2_machine;
57 59 extern QEMUMachine ss1000_machine, ss2000_machine;
58 60  
... ...
hw/sun4m.c
  View file @a526a31
... ... @@ -891,6 +891,216 @@ static const struct hwdef hwdefs[] = {
891 891 .max_mem = 0x10000000,
892 892 .default_cpu_model = "Cypress CY7C601",
893 893 },
  894 + /* Voyager */
  895 + {
  896 + .iommu_base = 0x10000000,
  897 + .tcx_base = 0x50000000,
  898 + .cs_base = -1,
  899 + .slavio_base = 0x70000000,
  900 + .ms_kb_base = 0x71000000,
  901 + .serial_base = 0x71100000,
  902 + .nvram_base = 0x71200000,
  903 + .fd_base = 0x71400000,
  904 + .counter_base = 0x71d00000,
  905 + .intctl_base = 0x71e00000,
  906 + .idreg_base = 0x78000000,
  907 + .dma_base = 0x78400000,
  908 + .esp_base = 0x78800000,
  909 + .le_base = 0x78c00000,
  910 + .apc_base = 0x71300000, // pmc
  911 + .aux1_base = 0x71900000,
  912 + .aux2_base = 0x71910000,
  913 + .ecc_base = -1,
  914 + .sun4c_intctl_base = -1,
  915 + .sun4c_counter_base = -1,
  916 + .vram_size = 0x00100000,
  917 + .nvram_size = 0x2000,
  918 + .esp_irq = 18,
  919 + .le_irq = 16,
  920 + .clock_irq = 7,
  921 + .clock1_irq = 19,
  922 + .ms_kb_irq = 14,
  923 + .ser_irq = 15,
  924 + .fd_irq = 22,
  925 + .me_irq = 30,
  926 + .cs_irq = -1,
  927 + .machine_id = 0x80,
  928 + .iommu_version = 0x05000000,
  929 + .intbit_to_level = {
  930 + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
  931 + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
  932 + },
  933 + .max_mem = 0x10000000,
  934 + .default_cpu_model = "Fujitsu MB86904",
  935 + },
  936 + /* LX */
  937 + {
  938 + .iommu_base = 0x10000000,
  939 + .tcx_base = 0x50000000,
  940 + .cs_base = -1,
  941 + .slavio_base = 0x70000000,
  942 + .ms_kb_base = 0x71000000,
  943 + .serial_base = 0x71100000,
  944 + .nvram_base = 0x71200000,
  945 + .fd_base = 0x71400000,
  946 + .counter_base = 0x71d00000,
  947 + .intctl_base = 0x71e00000,
  948 + .idreg_base = 0x78000000,
  949 + .dma_base = 0x78400000,
  950 + .esp_base = 0x78800000,
  951 + .le_base = 0x78c00000,
  952 + .apc_base = -1,
  953 + .aux1_base = 0x71900000,
  954 + .aux2_base = 0x71910000,
  955 + .ecc_base = -1,
  956 + .sun4c_intctl_base = -1,
  957 + .sun4c_counter_base = -1,
  958 + .vram_size = 0x00100000,
  959 + .nvram_size = 0x2000,
  960 + .esp_irq = 18,
  961 + .le_irq = 16,
  962 + .clock_irq = 7,
  963 + .clock1_irq = 19,
  964 + .ms_kb_irq = 14,
  965 + .ser_irq = 15,
  966 + .fd_irq = 22,
  967 + .me_irq = 30,
  968 + .cs_irq = -1,
  969 + .machine_id = 0x80,
  970 + .iommu_version = 0x04000000,
  971 + .intbit_to_level = {
  972 + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
  973 + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
  974 + },
  975 + .max_mem = 0x10000000,
  976 + .default_cpu_model = "TI MicroSparc I",
  977 + },
  978 + /* SS-4 */
  979 + {
  980 + .iommu_base = 0x10000000,
  981 + .tcx_base = 0x50000000,
  982 + .cs_base = 0x6c000000,
  983 + .slavio_base = 0x70000000,
  984 + .ms_kb_base = 0x71000000,
  985 + .serial_base = 0x71100000,
  986 + .nvram_base = 0x71200000,
  987 + .fd_base = 0x71400000,
  988 + .counter_base = 0x71d00000,
  989 + .intctl_base = 0x71e00000,
  990 + .idreg_base = 0x78000000,
  991 + .dma_base = 0x78400000,
  992 + .esp_base = 0x78800000,
  993 + .le_base = 0x78c00000,
  994 + .apc_base = 0x6a000000,
  995 + .aux1_base = 0x71900000,
  996 + .aux2_base = 0x71910000,
  997 + .ecc_base = -1,
  998 + .sun4c_intctl_base = -1,
  999 + .sun4c_counter_base = -1,
  1000 + .vram_size = 0x00100000,
  1001 + .nvram_size = 0x2000,
  1002 + .esp_irq = 18,
  1003 + .le_irq = 16,
  1004 + .clock_irq = 7,
  1005 + .clock1_irq = 19,
  1006 + .ms_kb_irq = 14,
  1007 + .ser_irq = 15,
  1008 + .fd_irq = 22,
  1009 + .me_irq = 30,
  1010 + .cs_irq = 5,
  1011 + .machine_id = 0x80,
  1012 + .iommu_version = 0x05000000,
  1013 + .intbit_to_level = {
  1014 + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
  1015 + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
  1016 + },
  1017 + .max_mem = 0x10000000,
  1018 + .default_cpu_model = "Fujitsu MB86904",
  1019 + },
  1020 + /* SPARCClassic */
  1021 + {
  1022 + .iommu_base = 0x10000000,
  1023 + .tcx_base = 0x50000000,
  1024 + .cs_base = -1,
  1025 + .slavio_base = 0x70000000,
  1026 + .ms_kb_base = 0x71000000,
  1027 + .serial_base = 0x71100000,
  1028 + .nvram_base = 0x71200000,
  1029 + .fd_base = 0x71400000,
  1030 + .counter_base = 0x71d00000,
  1031 + .intctl_base = 0x71e00000,
  1032 + .idreg_base = 0x78000000,
  1033 + .dma_base = 0x78400000,
  1034 + .esp_base = 0x78800000,
  1035 + .le_base = 0x78c00000,
  1036 + .apc_base = 0x6a000000,
  1037 + .aux1_base = 0x71900000,
  1038 + .aux2_base = 0x71910000,
  1039 + .ecc_base = -1,
  1040 + .sun4c_intctl_base = -1,
  1041 + .sun4c_counter_base = -1,
  1042 + .vram_size = 0x00100000,
  1043 + .nvram_size = 0x2000,
  1044 + .esp_irq = 18,
  1045 + .le_irq = 16,
  1046 + .clock_irq = 7,
  1047 + .clock1_irq = 19,
  1048 + .ms_kb_irq = 14,
  1049 + .ser_irq = 15,
  1050 + .fd_irq = 22,
  1051 + .me_irq = 30,
  1052 + .cs_irq = -1,
  1053 + .machine_id = 0x80,
  1054 + .iommu_version = 0x05000000,
  1055 + .intbit_to_level = {
  1056 + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
  1057 + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
  1058 + },
  1059 + .max_mem = 0x10000000,
  1060 + .default_cpu_model = "TI MicroSparc I",
  1061 + },
  1062 + /* SPARCbook */
  1063 + {
  1064 + .iommu_base = 0x10000000,
  1065 + .tcx_base = 0x50000000, // XXX
  1066 + .cs_base = -1,
  1067 + .slavio_base = 0x70000000,
  1068 + .ms_kb_base = 0x71000000,
  1069 + .serial_base = 0x71100000,
  1070 + .nvram_base = 0x71200000,
  1071 + .fd_base = 0x71400000,
  1072 + .counter_base = 0x71d00000,
  1073 + .intctl_base = 0x71e00000,
  1074 + .idreg_base = 0x78000000,
  1075 + .dma_base = 0x78400000,
  1076 + .esp_base = 0x78800000,
  1077 + .le_base = 0x78c00000,
  1078 + .apc_base = 0x6a000000,
  1079 + .aux1_base = 0x71900000,
  1080 + .aux2_base = 0x71910000,
  1081 + .ecc_base = -1,
  1082 + .sun4c_intctl_base = -1,
  1083 + .sun4c_counter_base = -1,
  1084 + .vram_size = 0x00100000,
  1085 + .nvram_size = 0x2000,
  1086 + .esp_irq = 18,
  1087 + .le_irq = 16,
  1088 + .clock_irq = 7,
  1089 + .clock1_irq = 19,
  1090 + .ms_kb_irq = 14,
  1091 + .ser_irq = 15,
  1092 + .fd_irq = 22,
  1093 + .me_irq = 30,
  1094 + .cs_irq = -1,
  1095 + .machine_id = 0x80,
  1096 + .iommu_version = 0x05000000,
  1097 + .intbit_to_level = {
  1098 + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
  1099 + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
  1100 + },
  1101 + .max_mem = 0x10000000,
  1102 + .default_cpu_model = "TI MicroSparc I",
  1103 + },
894 1104 };
895 1105  
896 1106 /* SPARCstation 5 hardware initialisation */
... ... @@ -943,6 +1153,56 @@ static void ss2_init(int RAM_size, int vga_ram_size,
943 1153 kernel_cmdline, initrd_filename, cpu_model);
944 1154 }
945 1155  
  1156 +/* SPARCstation Voyager hardware initialisation */
  1157 +static void vger_init(int RAM_size, int vga_ram_size,
  1158 + const char *boot_device, DisplayState *ds,
  1159 + const char *kernel_filename, const char *kernel_cmdline,
  1160 + const char *initrd_filename, const char *cpu_model)
  1161 +{
  1162 + sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
  1163 + kernel_cmdline, initrd_filename, cpu_model);
  1164 +}
  1165 +
  1166 +/* SPARCstation LX hardware initialisation */
  1167 +static void ss_lx_init(int RAM_size, int vga_ram_size,
  1168 + const char *boot_device, DisplayState *ds,
  1169 + const char *kernel_filename, const char *kernel_cmdline,
  1170 + const char *initrd_filename, const char *cpu_model)
  1171 +{
  1172 + sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
  1173 + kernel_cmdline, initrd_filename, cpu_model);
  1174 +}
  1175 +
  1176 +/* SPARCstation 4 hardware initialisation */
  1177 +static void ss4_init(int RAM_size, int vga_ram_size,
  1178 + const char *boot_device, DisplayState *ds,
  1179 + const char *kernel_filename, const char *kernel_cmdline,
  1180 + const char *initrd_filename, const char *cpu_model)
  1181 +{
  1182 + sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
  1183 + kernel_cmdline, initrd_filename, cpu_model);
  1184 +}
  1185 +
  1186 +/* SPARCClassic hardware initialisation */
  1187 +static void scls_init(int RAM_size, int vga_ram_size,
  1188 + const char *boot_device, DisplayState *ds,
  1189 + const char *kernel_filename, const char *kernel_cmdline,
  1190 + const char *initrd_filename, const char *cpu_model)
  1191 +{
  1192 + sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
  1193 + kernel_cmdline, initrd_filename, cpu_model);
  1194 +}
  1195 +
  1196 +/* SPARCbook hardware initialisation */
  1197 +static void sbook_init(int RAM_size, int vga_ram_size,
  1198 + const char *boot_device, DisplayState *ds,
  1199 + const char *kernel_filename, const char *kernel_cmdline,
  1200 + const char *initrd_filename, const char *cpu_model)
  1201 +{
  1202 + sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
  1203 + kernel_cmdline, initrd_filename, cpu_model);
  1204 +}
  1205 +
946 1206 QEMUMachine ss5_machine = {
947 1207 "SS-5",
948 1208 "Sun4m platform, SPARCstation 5",
... ... @@ -973,6 +1233,36 @@ QEMUMachine ss2_machine = {
973 1233 ss2_init,
974 1234 };
975 1235  
  1236 +QEMUMachine voyager_machine = {
  1237 + "Voyager",
  1238 + "Sun4m platform, SPARCstation Voyager",
  1239 + vger_init,
  1240 +};
  1241 +
  1242 +QEMUMachine ss_lx_machine = {
  1243 + "LX",
  1244 + "Sun4m platform, SPARCstation LX",
  1245 + ss_lx_init,
  1246 +};
  1247 +
  1248 +QEMUMachine ss4_machine = {
  1249 + "SS-4",
  1250 + "Sun4m platform, SPARCstation 4",
  1251 + ss4_init,
  1252 +};
  1253 +
  1254 +QEMUMachine scls_machine = {
  1255 + "SPARCClassic",
  1256 + "Sun4m platform, SPARCClassic",
  1257 + scls_init,
  1258 +};
  1259 +
  1260 +QEMUMachine sbook_machine = {
  1261 + "SPARCbook",
  1262 + "Sun4m platform, SPARCbook",
  1263 + sbook_init,
  1264 +};
  1265 +
976 1266 static const struct sun4d_hwdef sun4d_hwdefs[] = {
977 1267 /* SS-1000 */
978 1268 {
... ...
... ... @@ -7988,6 +7988,11 @@ static void register_machines(void)
7988 7988 qemu_register_machine(&ss600mp_machine);
7989 7989 qemu_register_machine(&ss20_machine);
7990 7990 qemu_register_machine(&ss2_machine);
  7991 + qemu_register_machine(&voyager_machine);
  7992 + qemu_register_machine(&ss_lx_machine);
  7993 + qemu_register_machine(&ss4_machine);
  7994 + qemu_register_machine(&scls_machine);
  7995 + qemu_register_machine(&sbook_machine);
7991 7996 qemu_register_machine(&ss1000_machine);
7992 7997 qemu_register_machine(&ss2000_machine);
7993 7998 #endif
... ...