gwj / at91sam9263 · Commits

Commit c68ea7043f2ed4c631d1e3a4f35afe247d5ca063

Authored by bellard
1 parent 173d6cfe

cpu_single_env usage fix 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1644 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 15 changed files with 129 additions and 88 deletions
hw/dma.c
  View file @c68ea70
... ... @@ -427,7 +427,9 @@ int DMA_write_memory (int nchan, void *buf, int pos, int len)
427 427 /* request the emulator to transfer a new DMA memory block ASAP */
428 428 void DMA_schedule(int nchan)
429 429 {
430   - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
  430 + CPUState *env = cpu_single_env;
  431 + if (env)
  432 + cpu_interrupt(env, CPU_INTERRUPT_EXIT);
431 433 }
432 434  
433 435 static void dma_reset(void *opaque)
... ...
hw/heathrow_pic.c
  View file @c68ea70
... ... @@ -45,9 +45,9 @@ static inline int check_irq(HeathrowPIC *pic)
45 45 static void heathrow_pic_update(HeathrowPICS *s)
46 46 {
47 47 if (check_irq(&s->pics[0]) || check_irq(&s->pics[1])) {
48   - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  48 + cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
49 49 } else {
50   - cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  50 + cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
51 51 }
52 52 }
53 53  
... ...
hw/mips_r4k.c
  View file @c68ea70
... ... @@ -11,12 +11,13 @@ static PITState *pit;
11 11  
12 12 static void pic_irq_request(void *opaque, int level)
13 13 {
  14 + CPUState *env = first_cpu;
14 15 if (level) {
15   - cpu_single_env->CP0_Cause |= 0x00000400;
16   - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  16 + env->CP0_Cause |= 0x00000400;
  17 + cpu_interrupt(env, CPU_INTERRUPT_HARD);
17 18 } else {
18   - cpu_single_env->CP0_Cause &= ~0x00000400;
19   - cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  19 + env->CP0_Cause &= ~0x00000400;
  20 + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
20 21 }
21 22 }
22 23  
... ... @@ -74,8 +75,8 @@ void cpu_mips_store_count (CPUState *env, uint32_t value)
74 75 void cpu_mips_store_compare (CPUState *env, uint32_t value)
75 76 {
76 77 cpu_mips_update_count(env, cpu_mips_get_count(env), value);
77   - cpu_single_env->CP0_Cause &= ~0x00008000;
78   - cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  78 + env->CP0_Cause &= ~0x00008000;
  79 + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
79 80 }
80 81  
81 82 static void mips_timer_cb (void *opaque)
... ... @@ -89,8 +90,8 @@ static void mips_timer_cb (void *opaque)
89 90 }
90 91 #endif
91 92 cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
92   - cpu_single_env->CP0_Cause |= 0x00008000;
93   - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  93 + env->CP0_Cause |= 0x00008000;
  94 + cpu_interrupt(env, CPU_INTERRUPT_HARD);
94 95 }
95 96  
96 97 void cpu_mips_clock_init (CPUState *env)
... ... @@ -181,9 +182,14 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
181 182 int io_memory;
182 183 int linux_boot;
183 184 int ret;
  185 + CPUState *env;
184 186  
185 187 printf("%s: start\n", __func__);
186 188 linux_boot = (kernel_filename != NULL);
  189 +
  190 + env = cpu_init();
  191 + register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
  192 +
187 193 /* allocate RAM */
188 194 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
189 195 bios_offset = ram_size + vga_ram_size;
... ... @@ -198,9 +204,9 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
198 204 BIOS_SIZE, bios_offset | IO_MEM_ROM);
199 205 #if 0
200 206 memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE);
201   - cpu_single_env->PC = 0x80010004;
  207 + env->PC = 0x80010004;
202 208 #else
203   - cpu_single_env->PC = 0xBFC00004;
  209 + env->PC = 0xBFC00004;
204 210 #endif
205 211 if (linux_boot) {
206 212 kernel_base = KERNEL_LOAD_ADDR;
... ... @@ -226,7 +232,7 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
226 232 initrd_base = 0;
227 233 initrd_size = 0;
228 234 }
229   - cpu_single_env->PC = KERNEL_LOAD_ADDR;
  235 + env->PC = KERNEL_LOAD_ADDR;
230 236 } else {
231 237 kernel_base = 0;
232 238 kernel_size = 0;
... ... @@ -235,7 +241,7 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
235 241 }
236 242  
237 243 /* Init internal devices */
238   - cpu_mips_clock_init(cpu_single_env);
  244 + cpu_mips_clock_init(env);
239 245 cpu_mips_irqctrl_init();
240 246  
241 247 /* Register 64 KB of ISA IO space at 0x14000000 */
... ... @@ -243,7 +249,7 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
243 249 cpu_register_physical_memory(0x14000000, 0x00010000, io_memory);
244 250 isa_mem_base = 0x10000000;
245 251  
246   - isa_pic = pic_init(pic_irq_request, cpu_single_env);
  252 + isa_pic = pic_init(pic_irq_request, env);
247 253 pit = pit_init(0x40, 0);
248 254 serial_init(0x3f8, 4, serial_hds[0]);
249 255 vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
... ...
hw/openpic.c
  View file @c68ea70
... ... @@ -265,7 +265,8 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
265 265 if (priority > dst->raised.priority) {
266 266 IRQ_get_next(opp, &dst->raised);
267 267 DPRINTF("Raise CPU IRQ\n");
268   - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  268 + /* XXX: choose the correct cpu */
  269 + cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
269 270 }
270 271 }
271 272  
... ... @@ -532,7 +533,7 @@ static void openpic_gbl_write (void *opaque, uint32_t addr, uint32_t val)
532 533 /* XXX: Should be able to reset any CPU */
533 534 if (val & 1) {
534 535 DPRINTF("Reset CPU IRQ\n");
535   - // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
  536 + // cpu_interrupt(first_cpu, CPU_INTERRUPT_RESET);
536 537 }
537 538 break;
538 539 #if MAX_IPI > 0
... ... @@ -781,7 +782,8 @@ static void openpic_cpu_write (void *opaque, uint32_t addr, uint32_t val)
781 782 src = &opp->src[n_IRQ];
782 783 if (IPVP_PRIORITY(src->ipvp) > dst->servicing.priority) {
783 784 DPRINTF("Raise CPU IRQ\n");
784   - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  785 + /* XXX: choose cpu */
  786 + cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
785 787 }
786 788 }
787 789 break;
... ...
hw/pci.c
  View file @c68ea70
... ... @@ -1616,32 +1616,32 @@ void pci_info(void)
1616 1616  
1617 1617 static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
1618 1618 {
1619   - return cpu_inb(cpu_single_env, addr);
  1619 + return cpu_inb(NULL, addr);
1620 1620 }
1621 1621  
1622 1622 static void isa_outb(uint32_t val, uint32_t addr)
1623 1623 {
1624   - cpu_outb(cpu_single_env, addr, val);
  1624 + cpu_outb(NULL, addr, val);
1625 1625 }
1626 1626  
1627 1627 static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
1628 1628 {
1629   - return cpu_inw(cpu_single_env, addr);
  1629 + return cpu_inw(NULL, addr);
1630 1630 }
1631 1631  
1632 1632 static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
1633 1633 {
1634   - cpu_outw(cpu_single_env, addr, val);
  1634 + cpu_outw(NULL, addr, val);
1635 1635 }
1636 1636  
1637 1637 static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
1638 1638 {
1639   - return cpu_inl(cpu_single_env, addr);
  1639 + return cpu_inl(NULL, addr);
1640 1640 }
1641 1641  
1642 1642 static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
1643 1643 {
1644   - cpu_outl(cpu_single_env, addr, val);
  1644 + cpu_outl(NULL, addr, val);
1645 1645 }
1646 1646  
1647 1647 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
... ...
hw/pckbd.c
  View file @c68ea70
... ... @@ -254,7 +254,7 @@ static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
254 254 case KBD_CCMD_READ_OUTPORT:
255 255 /* XXX: check that */
256 256 #ifdef TARGET_I386
257   - val = 0x01 | (((cpu_single_env->a20_mask >> 20) & 1) << 1);
  257 + val = 0x01 | (ioport_get_a20() << 1);
258 258 #else
259 259 val = 0x01;
260 260 #endif
... ... @@ -266,10 +266,10 @@ static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
266 266 break;
267 267 #ifdef TARGET_I386
268 268 case KBD_CCMD_ENABLE_A20:
269   - cpu_x86_set_a20(cpu_single_env, 1);
  269 + ioport_set_a20(1);
270 270 break;
271 271 case KBD_CCMD_DISABLE_A20:
272   - cpu_x86_set_a20(cpu_single_env, 0);
  272 + ioport_set_a20(0);
273 273 break;
274 274 #endif
275 275 case KBD_CCMD_RESET:
... ... @@ -611,7 +611,7 @@ void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
611 611 break;
612 612 case KBD_CCMD_WRITE_OUTPORT:
613 613 #ifdef TARGET_I386
614   - cpu_x86_set_a20(cpu_single_env, (val >> 1) & 1);
  614 + ioport_set_a20((val >> 1) & 1);
615 615 #endif
616 616 if (!(val & 1)) {
617 617 qemu_system_reset_request();
... ...
hw/ppc_chrp.c
  View file @c68ea70
... ... @@ -300,6 +300,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
300 300 const char *initrd_filename,
301 301 int is_heathrow)
302 302 {
  303 + CPUState *env;
303 304 char buf[1024];
304 305 SetIRQFunc *set_irq;
305 306 void *pic;
... ... @@ -315,6 +316,36 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
315 316  
316 317 linux_boot = (kernel_filename != NULL);
317 318  
  319 + /* init CPUs */
  320 + env = cpu_init();
  321 + register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
  322 +
  323 + /* Register CPU as a 74x/75x */
  324 + /* XXX: CPU model (or PVR) should be provided on command line */
  325 + // ppc_find_by_name("750gx", &def); // Linux boot OK
  326 + // ppc_find_by_name("750fx", &def); // Linux boot OK
  327 + /* Linux does not boot on 750cxe (and probably other 750cx based)
  328 + * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
  329 + */
  330 + // ppc_find_by_name("750cxe", &def);
  331 + // ppc_find_by_name("750p", &def);
  332 + // ppc_find_by_name("740p", &def);
  333 + ppc_find_by_name("750", &def);
  334 + // ppc_find_by_name("740", &def);
  335 + // ppc_find_by_name("G3", &def);
  336 + // ppc_find_by_name("604r", &def);
  337 + // ppc_find_by_name("604e", &def);
  338 + // ppc_find_by_name("604", &def);
  339 + if (def == NULL) {
  340 + cpu_abort(env, "Unable to find PowerPC CPU definition\n");
  341 + }
  342 + cpu_ppc_register(env, def);
  343 +
  344 + /* Set time-base frequency to 100 Mhz */
  345 + cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
  346 +
  347 + env->osi_call = vga_osi_call;
  348 +
318 349 /* allocate RAM */
319 350 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
320 351  
... ... @@ -381,31 +412,6 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
381 412 initrd_base = 0;
382 413 initrd_size = 0;
383 414 }
384   - /* Register CPU as a 74x/75x */
385   - /* XXX: CPU model (or PVR) should be provided on command line */
386   - // ppc_find_by_name("750gx", &def); // Linux boot OK
387   - // ppc_find_by_name("750fx", &def); // Linux boot OK
388   - /* Linux does not boot on 750cxe (and probably other 750cx based)
389   - * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
390   - */
391   - // ppc_find_by_name("750cxe", &def);
392   - // ppc_find_by_name("750p", &def);
393   - // ppc_find_by_name("740p", &def);
394   - ppc_find_by_name("750", &def);
395   - // ppc_find_by_name("740", &def);
396   - // ppc_find_by_name("G3", &def);
397   - // ppc_find_by_name("604r", &def);
398   - // ppc_find_by_name("604e", &def);
399   - // ppc_find_by_name("604", &def);
400   - if (def == NULL) {
401   - cpu_abort(cpu_single_env, "Unable to find PowerPC CPU definition\n");
402   - }
403   - cpu_ppc_register(cpu_single_env, def);
404   -
405   - /* Set time-base frequency to 100 Mhz */
406   - cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
407   -
408   - cpu_single_env->osi_call = vga_osi_call;
409 415  
410 416 if (is_heathrow) {
411 417 isa_mem_base = 0x80000000;
... ...
hw/ppc_prep.c
  View file @c68ea70
... ... @@ -99,9 +99,9 @@ static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
99 99 static void pic_irq_request(void *opaque, int level)
100 100 {
101 101 if (level)
102   - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  102 + cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
103 103 else
104   - cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  104 + cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
105 105 }
106 106  
107 107 /* PCI intack register */
... ... @@ -294,7 +294,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
294 294 /* Special port 92 */
295 295 /* Check soft reset asked */
296 296 if (val & 0x01) {
297   - // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
  297 + // cpu_interrupt(first_cpu, CPU_INTERRUPT_RESET);
298 298 }
299 299 /* Check LE mode */
300 300 if (val & 0x02) {
... ... @@ -331,7 +331,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
331 331 break;
332 332 case 0x0814:
333 333 /* L2 invalidate register */
334   - // tlb_flush(cpu_single_env, 1);
  334 + // tlb_flush(first_cpu, 1);
335 335 break;
336 336 case 0x081C:
337 337 /* system control register */
... ... @@ -523,6 +523,7 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
523 523 const char *kernel_filename, const char *kernel_cmdline,
524 524 const char *initrd_filename)
525 525 {
  526 + CPUState *env;
526 527 char buf[1024];
527 528 m48t59_t *nvram;
528 529 int PPC_io_memory;
... ... @@ -537,6 +538,23 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
537 538 return;
538 539  
539 540 linux_boot = (kernel_filename != NULL);
  541 +
  542 + /* init CPUs */
  543 +
  544 + env = cpu_init();
  545 + register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
  546 +
  547 + /* Register CPU as a 604 */
  548 + /* XXX: CPU model (or PVR) should be provided on command line */
  549 + // ppc_find_by_name("604r", &def);
  550 + // ppc_find_by_name("604e", &def);
  551 + ppc_find_by_name("604", &def);
  552 + if (def == NULL) {
  553 + cpu_abort(env, "Unable to find PowerPC CPU definition\n");
  554 + }
  555 + cpu_ppc_register(env, def);
  556 + /* Set time-base frequency to 100 Mhz */
  557 + cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
540 558  
541 559 /* allocate RAM */
542 560 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
... ... @@ -584,18 +602,6 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
584 602 initrd_size = 0;
585 603 }
586 604  
587   - /* Register CPU as a 604 */
588   - /* XXX: CPU model (or PVR) should be provided on command line */
589   - // ppc_find_by_name("604r", &def);
590   - // ppc_find_by_name("604e", &def);
591   - ppc_find_by_name("604", &def);
592   - if (def == NULL) {
593   - cpu_abort(cpu_single_env, "Unable to find PowerPC CPU definition\n");
594   - }
595   - cpu_ppc_register(cpu_single_env, def);
596   - /* Set time-base frequency to 100 Mhz */
597   - cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
598   -
599 605 isa_mem_base = 0xc0000000;
600 606 pci_bus = pci_prep_init();
601 607 // pci_bus = i440fx_init();
... ... @@ -609,7 +615,7 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
609 615 vga_ram_size, 0, 0);
610 616 rtc_init(0x70, 8);
611 617 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
612   - isa_pic = pic_init(pic_irq_request, cpu_single_env);
  618 + isa_pic = pic_init(pic_irq_request, first_cpu);
613 619 // pit = pit_init(0x40, 0);
614 620  
615 621 serial_init(0x3f8, 4, serial_hds[0]);
... ...
hw/slavio_intctl.c
  View file @c68ea70
... ... @@ -213,6 +213,7 @@ static const uint32_t intbit_to_level[32] = {
213 213  
214 214 static void slavio_check_interrupts(void *opaque)
215 215 {
  216 + CPUState *env;
216 217 SLAVIO_INTCTLState *s = opaque;
217 218 uint32_t pending = s->intregm_pending;
218 219 unsigned int i, max = 0;
... ... @@ -226,16 +227,17 @@ static void slavio_check_interrupts(void *opaque)
226 227 max = intbit_to_level[i];
227 228 }
228 229 }
229   - if (cpu_single_env->interrupt_index == 0) {
  230 + env = first_cpu;
  231 + if (env->interrupt_index == 0) {
230 232 DPRINTF("Triggered pil %d\n", max);
231 233 #ifdef DEBUG_IRQ_COUNT
232 234 s->irq_count[max]++;
233 235 #endif
234   - cpu_single_env->interrupt_index = TT_EXTINT | max;
235   - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
  236 + env->interrupt_index = TT_EXTINT | max;
  237 + cpu_interrupt(env, CPU_INTERRUPT_HARD);
236 238 }
237 239 else
238   - DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, cpu_single_env->interrupt_index);
  240 + DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
239 241 }
240 242 else
241 243 DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
... ...
hw/sun4m.c
  View file @c68ea70
... ... @@ -210,12 +210,19 @@ void qemu_system_powerdown(void)
210 210 slavio_set_power_fail(slavio_misc, 1);
211 211 }
212 212  
  213 +static void main_cpu_reset(void *opaque)
  214 +{
  215 + CPUState *env = opaque;
  216 + cpu_reset(env);
  217 +}
  218 +
213 219 /* Sun4m hardware initialisation */
214 220 static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
215 221 DisplayState *ds, const char **fd_filename, int snapshot,
216 222 const char *kernel_filename, const char *kernel_cmdline,
217 223 const char *initrd_filename)
218 224 {
  225 + CPUState *env;
219 226 char buf[1024];
220 227 int ret, linux_boot;
221 228 unsigned int i;
... ... @@ -223,6 +230,10 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
223 230  
224 231 linux_boot = (kernel_filename != NULL);
225 232  
  233 + env = cpu_init();
  234 + register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
  235 + qemu_register_reset(main_cpu_reset, env);
  236 +
226 237 /* allocate RAM */
227 238 cpu_register_physical_memory(0, ram_size, 0);
228 239  
... ...
hw/sun4u.c
  View file @c68ea70
... ... @@ -235,6 +235,12 @@ void qemu_system_powerdown(void)
235 235 {
236 236 }
237 237  
  238 +static void main_cpu_reset(void *opaque)
  239 +{
  240 + CPUState *env = opaque;
  241 + cpu_reset(env);
  242 +}
  243 +
238 244 static const int ide_iobase[2] = { 0x1f0, 0x170 };
239 245 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
240 246 static const int ide_irq[2] = { 14, 15 };
... ... @@ -253,6 +259,7 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
253 259 const char *kernel_filename, const char *kernel_cmdline,
254 260 const char *initrd_filename)
255 261 {
  262 + CPUState *env;
256 263 char buf[1024];
257 264 m48t59_t *nvram;
258 265 int ret, linux_boot;
... ... @@ -262,6 +269,10 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
262 269  
263 270 linux_boot = (kernel_filename != NULL);
264 271  
  272 + env = cpu_init();
  273 + register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
  274 + qemu_register_reset(main_cpu_reset, env);
  275 +
265 276 /* allocate RAM */
266 277 cpu_register_physical_memory(0, ram_size, 0);
267 278  
... ...
linux-user/main.c
  View file @c68ea70
... ... @@ -997,8 +997,6 @@ void usage(void)
997 997  
998 998 /* XXX: currently only used for async signals (see signal.c) */
999 999 CPUState *global_env;
1000   -/* used only if single thread */
1001   -CPUState *cpu_single_env = NULL;
1002 1000  
1003 1001 /* used to free thread contexts */
1004 1002 TaskState *first_task_state;
... ... @@ -1228,10 +1226,10 @@ int main(int argc, char **argv)
1228 1226 // ppc_find_by_name("604e", &def);
1229 1227 // ppc_find_by_name("604", &def);
1230 1228 if (def == NULL) {
1231   - cpu_abort(cpu_single_env,
  1229 + cpu_abort(env,
1232 1230 "Unable to find PowerPC CPU definition\n");
1233 1231 }
1234   - cpu_ppc_register(cpu_single_env, def);
  1232 + cpu_ppc_register(env, def);
1235 1233  
1236 1234 for (i = 0; i < 32; i++) {
1237 1235 if (i != 12 && i != 6 && i != 13)
... ...
target-sparc/op_helper.c
  View file @c68ea70
... ... @@ -942,7 +942,7 @@ void do_interrupt(int intno)
942 942 #endif
943 943 #if !defined(CONFIG_USER_ONLY)
944 944 if (env->tl == MAXTL) {
945   - cpu_abort(cpu_single_env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
  945 + cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
946 946 return;
947 947 }
948 948 #endif
... ... @@ -996,7 +996,7 @@ void do_interrupt(int intno)
996 996 #endif
997 997 #if !defined(CONFIG_USER_ONLY)
998 998 if (env->psret == 0) {
999   - cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
  999 + cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
1000 1000 return;
1001 1001 }
1002 1002 #endif
... ...
target-sparc/translate.c
  View file @c68ea70
... ... @@ -2672,11 +2672,10 @@ CPUSPARCState *cpu_sparc_init(void)
2672 2672 {
2673 2673 CPUSPARCState *env;
2674 2674  
2675   - cpu_exec_init();
2676   -
2677   - if (!(env = malloc(sizeof(CPUSPARCState))))
2678   - return (NULL);
2679   - cpu_single_env = env;
  2675 + env = qemu_mallocz(sizeof(CPUSPARCState));
  2676 + if (!env)
  2677 + return NULL;
  2678 + cpu_exec_init(env);
2680 2679 cpu_reset(env);
2681 2680 return (env);
2682 2681 }
... ...
tests/qruncom.c
  View file @c68ea70
... ... @@ -15,8 +15,6 @@
15 15  
16 16 //#define SIGTEST
17 17  
18   -CPUState *cpu_single_env = NULL;
19   -
20 18 void cpu_outb(CPUState *env, int addr, int val)
21 19 {
22 20 fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val);
... ...