gwj / at91sam9263 · Commits

Commit 5aca8c3b2fbada188ff86781fba24685d346cef9

Authored by blueswir1
1 parent db7b5426

Split DMA controller in two 

Fix register size related bugs


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2869 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 10 changed files with 87 additions and 82 deletions
hw/cs4231.c
  View file @5aca8c3
... ... @@ -30,6 +30,7 @@
30 30 * In addition to Crystal CS4231 there is a DMA controller on Sparc.
31 31 */
32 32 #define CS_MAXADDR 0x3f
  33 +#define CS_SIZE (CS_MAXADDR + 1)
33 34 #define CS_REGS 16
34 35 #define CS_DREGS 32
35 36 #define CS_MAXDREG (CS_DREGS - 1)
... ... @@ -173,7 +174,7 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl)
173 174 return;
174 175  
175 176 cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
176   - cpu_register_physical_memory(base, CS_MAXADDR, cs_io_memory);
  177 + cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
177 178 register_savevm("cs4231", base, 1, cs_save, cs_load, s);
178 179 qemu_register_reset(cs_reset, s);
179 180 cs_reset(s);
... ...
hw/esp.c
  View file @5aca8c3
... ... @@ -41,7 +41,9 @@ do { printf("ESP: " fmt , ##args); } while (0)
41 41 #define DPRINTF(fmt, args...)
42 42 #endif
43 43  
44   -#define ESP_MAXREG 0x3f
  44 +#define ESP_MASK 0x3f
  45 +#define ESP_REGS 16
  46 +#define ESP_SIZE (ESP_REGS * 4)
45 47 #define TI_BUFSZ 32
46 48 /* The HBA is ID 7, so for simplicitly limit to 7 devices. */
47 49 #define ESP_MAX_DEVS 7
... ... @@ -50,8 +52,8 @@ typedef struct ESPState ESPState;
50 52  
51 53 struct ESPState {
52 54 BlockDriverState **bd;
53   - uint8_t rregs[ESP_MAXREG];
54   - uint8_t wregs[ESP_MAXREG];
  55 + uint8_t rregs[ESP_REGS];
  56 + uint8_t wregs[ESP_REGS];
55 57 int32_t ti_size;
56 58 uint32_t ti_rptr, ti_wptr;
57 59 uint8_t ti_buf[TI_BUFSZ];
... ... @@ -327,12 +329,12 @@ static void handle_ti(ESPState *s)
327 329 }
328 330 }
329 331  
330   -void esp_reset(void *opaque)
  332 +static void esp_reset(void *opaque)
331 333 {
332 334 ESPState *s = opaque;
333 335  
334   - memset(s->rregs, 0, ESP_MAXREG);
335   - memset(s->wregs, 0, ESP_MAXREG);
  336 + memset(s->rregs, 0, ESP_REGS);
  337 + memset(s->wregs, 0, ESP_REGS);
336 338 s->rregs[0x0e] = 0x4; // Indicate fas100a
337 339 s->ti_size = 0;
338 340 s->ti_rptr = 0;
... ... @@ -346,7 +348,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
346 348 ESPState *s = opaque;
347 349 uint32_t saddr;
348 350  
349   - saddr = (addr & ESP_MAXREG) >> 2;
  351 + saddr = (addr & ESP_MASK) >> 2;
350 352 DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
351 353 switch (saddr) {
352 354 case 2:
... ... @@ -384,7 +386,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
384 386 ESPState *s = opaque;
385 387 uint32_t saddr;
386 388  
387   - saddr = (addr & ESP_MAXREG) >> 2;
  389 + saddr = (addr & ESP_MASK) >> 2;
388 390 DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
389 391 switch (saddr) {
390 392 case 0:
... ... @@ -501,8 +503,8 @@ static void esp_save(QEMUFile *f, void *opaque)
501 503 {
502 504 ESPState *s = opaque;
503 505  
504   - qemu_put_buffer(f, s->rregs, ESP_MAXREG);
505   - qemu_put_buffer(f, s->wregs, ESP_MAXREG);
  506 + qemu_put_buffer(f, s->rregs, ESP_REGS);
  507 + qemu_put_buffer(f, s->wregs, ESP_REGS);
506 508 qemu_put_be32s(f, &s->ti_size);
507 509 qemu_put_be32s(f, &s->ti_rptr);
508 510 qemu_put_be32s(f, &s->ti_wptr);
... ... @@ -523,8 +525,8 @@ static int esp_load(QEMUFile *f, void *opaque, int version_id)
523 525 if (version_id != 3)
524 526 return -EINVAL; // Cannot emulate 2
525 527  
526   - qemu_get_buffer(f, s->rregs, ESP_MAXREG);
527   - qemu_get_buffer(f, s->wregs, ESP_MAXREG);
  528 + qemu_get_buffer(f, s->rregs, ESP_REGS);
  529 + qemu_get_buffer(f, s->wregs, ESP_REGS);
528 530 qemu_get_be32s(f, &s->ti_size);
529 531 qemu_get_be32s(f, &s->ti_rptr);
530 532 qemu_get_be32s(f, &s->ti_wptr);
... ... @@ -574,9 +576,10 @@ void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
574 576  
575 577 s->bd = bd;
576 578 s->dma_opaque = dma_opaque;
  579 + sparc32_dma_set_reset_data(dma_opaque, esp_reset, s);
577 580  
578 581 esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
579   - cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
  582 + cpu_register_physical_memory(espaddr, ESP_SIZE, esp_io_memory);
580 583  
581 584 esp_reset(s);
582 585  
... ...
hw/pcnet.c
  View file @5aca8c3
... ... @@ -1554,7 +1554,7 @@ static uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap)
1554 1554 return val;
1555 1555 }
1556 1556  
1557   -void pcnet_h_reset(void *opaque)
  1557 +static void pcnet_h_reset(void *opaque)
1558 1558 {
1559 1559 PCNetState *s = opaque;
1560 1560 int i;
... ... @@ -2032,6 +2032,8 @@ void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
2032 2032 cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);
2033 2033  
2034 2034 d->dma_opaque = dma_opaque;
  2035 + sparc32_dma_set_reset_data(dma_opaque, pcnet_h_reset, d);
  2036 +
2035 2037 cpu_register_physical_memory(leaddr, 4, lance_io_memory);
2036 2038  
2037 2039 d->irq = irq;
... ...
hw/slavio_intctl.c
  View file @5aca8c3
... ... @@ -58,7 +58,9 @@ typedef struct SLAVIO_INTCTLState {
58 58 } SLAVIO_INTCTLState;
59 59  
60 60 #define INTCTL_MAXADDR 0xf
  61 +#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
61 62 #define INTCTLM_MAXADDR 0x13
  63 +#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
62 64 #define INTCTLM_MASK 0x1f
63 65 static void slavio_check_interrupts(void *opaque);
64 66  
... ... @@ -386,11 +388,12 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
386 388 s->intbit_to_level = intbit_to_level;
387 389 for (i = 0; i < MAX_CPUS; i++) {
388 390 slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
389   - cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
  391 + cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
  392 + slavio_intctl_io_memory);
390 393 }
391 394  
392 395 slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
393   - cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);
  396 + cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
394 397  
395 398 register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
396 399 qemu_register_reset(slavio_intctl_reset, s);
... ...
hw/slavio_misc.c
  View file @5aca8c3
... ... @@ -47,7 +47,7 @@ typedef struct MiscState {
47 47 uint8_t diag, mctrl, sysctrl;
48 48 } MiscState;
49 49  
50   -#define MISC_MAXADDR 1
  50 +#define MISC_SIZE 1
51 51  
52 52 static void slavio_misc_update_irq(void *opaque)
53 53 {
... ... @@ -224,19 +224,25 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
224 224  
225 225 slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, slavio_misc_mem_write, s);
226 226 // Slavio control
227   - cpu_register_physical_memory(base + 0x1800000, MISC_MAXADDR, slavio_misc_io_memory);
  227 + cpu_register_physical_memory(base + 0x1800000, MISC_SIZE,
  228 + slavio_misc_io_memory);
228 229 // AUX 1
229   - cpu_register_physical_memory(base + 0x1900000, MISC_MAXADDR, slavio_misc_io_memory);
  230 + cpu_register_physical_memory(base + 0x1900000, MISC_SIZE,
  231 + slavio_misc_io_memory);
230 232 // AUX 2
231   - cpu_register_physical_memory(base + 0x1910000, MISC_MAXADDR, slavio_misc_io_memory);
  233 + cpu_register_physical_memory(base + 0x1910000, MISC_SIZE,
  234 + slavio_misc_io_memory);
232 235 // Diagnostics
233   - cpu_register_physical_memory(base + 0x1a00000, MISC_MAXADDR, slavio_misc_io_memory);
  236 + cpu_register_physical_memory(base + 0x1a00000, MISC_SIZE,
  237 + slavio_misc_io_memory);
234 238 // Modem control
235   - cpu_register_physical_memory(base + 0x1b00000, MISC_MAXADDR, slavio_misc_io_memory);
  239 + cpu_register_physical_memory(base + 0x1b00000, MISC_SIZE,
  240 + slavio_misc_io_memory);
236 241 // System control
237   - cpu_register_physical_memory(base + 0x1f00000, MISC_MAXADDR, slavio_misc_io_memory);
  242 + cpu_register_physical_memory(base + 0x1f00000, MISC_SIZE,
  243 + slavio_misc_io_memory);
238 244 // Power management
239   - cpu_register_physical_memory(power_base, MISC_MAXADDR, slavio_misc_io_memory);
  245 + cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
240 246  
241 247 s->irq = irq;
242 248  
... ...
hw/slavio_serial.c
  View file @5aca8c3
... ... @@ -102,6 +102,7 @@ struct SerialState {
102 102 };
103 103  
104 104 #define SERIAL_MAXADDR 7
  105 +#define SERIAL_SIZE (SERIAL_MAXADDR + 1)
105 106  
106 107 static void handle_kbd_command(ChannelState *s, int val);
107 108 static int serial_can_receive(void *opaque);
... ... @@ -178,7 +179,7 @@ static void slavio_serial_reset_chn(ChannelState *s)
178 179 int i;
179 180  
180 181 s->reg = 0;
181   - for (i = 0; i < SERIAL_MAXADDR; i++) {
  182 + for (i = 0; i < SERIAL_SIZE; i++) {
182 183 s->rregs[i] = 0;
183 184 s->wregs[i] = 0;
184 185 }
... ... @@ -598,7 +599,7 @@ SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
598 599 return NULL;
599 600  
600 601 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
601   - cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);
  602 + cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory);
602 603  
603 604 s->chn[0].chr = chr1;
604 605 s->chn[1].chr = chr2;
... ... @@ -723,7 +724,7 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq)
723 724 s->chn[1].type = kbd;
724 725  
725 726 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
726   - cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);
  727 + cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory);
727 728  
728 729 qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, "QEMU Sun Mouse");
729 730 qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
... ...
hw/slavio_timer.c
  View file @5aca8c3
... ... @@ -59,6 +59,7 @@ typedef struct SLAVIO_TIMERState {
59 59 } SLAVIO_TIMERState;
60 60  
61 61 #define TIMER_MAXADDR 0x1f
  62 +#define TIMER_SIZE (TIMER_MAXADDR + 1)
62 63  
63 64 // Update count, set irq, update expire_time
64 65 // Convert from ptimer countdown units
... ... @@ -260,7 +261,7 @@ void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
260 261  
261 262 slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
262 263 slavio_timer_mem_write, s);
263   - cpu_register_physical_memory(addr, TIMER_MAXADDR, slavio_timer_io_memory);
  264 + cpu_register_physical_memory(addr, TIMER_SIZE, slavio_timer_io_memory);
264 265 register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
265 266 qemu_register_reset(slavio_timer_reset, s);
266 267 slavio_timer_reset(s);
... ...
hw/sparc32_dma.c
  View file @5aca8c3
... ... @@ -41,22 +41,25 @@ do { printf(&quot;DMA: &quot; fmt , ##args); } while (0)
41 41 #define DPRINTF(fmt, args...)
42 42 #endif
43 43  
44   -#define DMA_REGS 8
45   -#define DMA_MAXADDR (DMA_REGS * 4 - 1)
  44 +#define DMA_REGS 4
  45 +#define DMA_SIZE (4 * sizeof(uint32_t))
  46 +#define DMA_MAXADDR (DMA_SIZE - 1)
46 47  
47 48 #define DMA_VER 0xa0000000
48 49 #define DMA_INTR 1
49 50 #define DMA_INTREN 0x10
50 51 #define DMA_WRITE_MEM 0x100
51 52 #define DMA_LOADED 0x04000000
  53 +#define DMA_DRAIN_FIFO 0x40
52 54 #define DMA_RESET 0x80
53 55  
54 56 typedef struct DMAState DMAState;
55 57  
56 58 struct DMAState {
57 59 uint32_t dmaregs[DMA_REGS];
58   - qemu_irq espirq, leirq;
59   - void *iommu, *esp_opaque, *lance_opaque;
  60 + qemu_irq irq;
  61 + void *iommu, *dev_opaque;
  62 + void (*dev_reset)(void *dev_opaque);
60 63 qemu_irq *pic;
61 64 };
62 65  
... ... @@ -69,7 +72,7 @@ void ledma_memory_read(void *opaque, target_phys_addr_t addr,
69 72  
70 73 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
71 74 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
72   - addr |= s->dmaregs[7];
  75 + addr |= s->dmaregs[3];
73 76 if (do_bswap) {
74 77 sparc_iommu_memory_read(s->iommu, addr, buf, len);
75 78 } else {
... ... @@ -91,7 +94,7 @@ void ledma_memory_write(void *opaque, target_phys_addr_t addr,
91 94  
92 95 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
93 96 s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
94   - addr |= s->dmaregs[7];
  97 + addr |= s->dmaregs[3];
95 98 if (do_bswap) {
96 99 sparc_iommu_memory_write(s->iommu, addr, buf, len);
97 100 } else {
... ... @@ -118,7 +121,7 @@ void espdma_raise_irq(void *opaque)
118 121  
119 122 DPRINTF("Raise ESP IRQ\n");
120 123 s->dmaregs[0] |= DMA_INTR;
121   - qemu_irq_raise(s->espirq);
  124 + qemu_irq_raise(s->irq);
122 125 }
123 126  
124 127 void espdma_clear_irq(void *opaque)
... ... @@ -127,7 +130,7 @@ void espdma_clear_irq(void *opaque)
127 130  
128 131 s->dmaregs[0] &= ~DMA_INTR;
129 132 DPRINTF("Lower ESP IRQ\n");
130   - qemu_irq_lower(s->espirq);
  133 + qemu_irq_lower(s->irq);
131 134 }
132 135  
133 136 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
... ... @@ -158,7 +161,8 @@ static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
158 161 uint32_t saddr;
159 162  
160 163 saddr = (addr & DMA_MAXADDR) >> 2;
161   - DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->dmaregs[saddr]);
  164 + DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
  165 + s->dmaregs[saddr]);
162 166  
163 167 return s->dmaregs[saddr];
164 168 }
... ... @@ -169,37 +173,26 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
169 173 uint32_t saddr;
170 174  
171 175 saddr = (addr & DMA_MAXADDR) >> 2;
172   - DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->dmaregs[saddr], val);
  176 + DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
  177 + s->dmaregs[saddr], val);
173 178 switch (saddr) {
174 179 case 0:
175 180 if (!(val & DMA_INTREN)) {
176   - DPRINTF("Lower ESP IRQ\n");
177   - qemu_irq_lower(s->espirq);
  181 + DPRINTF("Lower IRQ\n");
  182 + qemu_irq_lower(s->irq);
178 183 }
179 184 if (val & DMA_RESET) {
180   - esp_reset(s->esp_opaque);
181   - } else if (val & 0x40) {
182   - val &= ~0x40;
  185 + s->dev_reset(s->dev_opaque);
  186 + } else if (val & DMA_DRAIN_FIFO) {
  187 + val &= ~DMA_DRAIN_FIFO;
183 188 } else if (val == 0)
184   - val = 0x40;
  189 + val = DMA_DRAIN_FIFO;
185 190 val &= 0x0fffffff;
186 191 val |= DMA_VER;
187 192 break;
188 193 case 1:
189 194 s->dmaregs[0] |= DMA_LOADED;
190 195 break;
191   - case 4:
192   - /* ??? Should this mask out the lance IRQ? The NIC may re-assert
193   - this IRQ unexpectedly. */
194   - if (!(val & DMA_INTREN)) {
195   - DPRINTF("Lower Lance IRQ\n");
196   - qemu_irq_lower(s->leirq);
197   - }
198   - if (val & DMA_RESET)
199   - pcnet_h_reset(s->lance_opaque);
200   - val &= 0x0fffffff;
201   - val |= DMA_VER;
202   - break;
203 196 default:
204 197 break;
205 198 }
... ... @@ -222,9 +215,8 @@ static void dma_reset(void *opaque)
222 215 {
223 216 DMAState *s = opaque;
224 217  
225   - memset(s->dmaregs, 0, DMA_REGS * 4);
  218 + memset(s->dmaregs, 0, DMA_SIZE);
226 219 s->dmaregs[0] = DMA_VER;
227   - s->dmaregs[4] = DMA_VER;
228 220 }
229 221  
230 222 static void dma_save(QEMUFile *f, void *opaque)
... ... @@ -241,7 +233,7 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
241 233 DMAState *s = opaque;
242 234 unsigned int i;
243 235  
244   - if (version_id != 1)
  236 + if (version_id != 2)
245 237 return -EINVAL;
246 238 for (i = 0; i < DMA_REGS; i++)
247 239 qemu_get_be32s(f, &s->dmaregs[i]);
... ... @@ -249,8 +241,7 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
249 241 return 0;
250 242 }
251 243  
252   -void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq espirq,
253   - qemu_irq leirq, void *iommu)
  244 +void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
254 245 {
255 246 DMAState *s;
256 247 int dma_io_memory;
... ... @@ -259,24 +250,23 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq espirq,
259 250 if (!s)
260 251 return NULL;
261 252  
262   - s->espirq = espirq;
263   - s->leirq = leirq;
  253 + s->irq = irq;
264 254 s->iommu = iommu;
265 255  
266 256 dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
267   - cpu_register_physical_memory(daddr, 16 * 2, dma_io_memory);
  257 + cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
268 258  
269   - register_savevm("sparc32_dma", daddr, 1, dma_save, dma_load, s);
  259 + register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
270 260 qemu_register_reset(dma_reset, s);
271 261  
272 262 return s;
273 263 }
274 264  
275   -void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
276   - void *lance_opaque)
  265 +void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
  266 + void *dev_opaque)
277 267 {
278 268 DMAState *s = opaque;
279 269  
280   - s->esp_opaque = esp_opaque;
281   - s->lance_opaque = lance_opaque;
  270 + s->dev_reset = dev_reset;
  271 + s->dev_opaque = dev_opaque;
282 272 }
... ...
hw/sun4m.c
  View file @5aca8c3
... ... @@ -262,7 +262,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
262 262 {
263 263 CPUState *env, *envs[MAX_CPUS];
264 264 unsigned int i;
265   - void *iommu, *dma, *main_esp, *main_lance = NULL;
  265 + void *iommu, *espdma, *ledma, *main_esp, *main_lance = NULL;
266 266 const sparc_def_t *def;
267 267 qemu_irq *slavio_irq;
268 268  
... ... @@ -295,8 +295,10 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
295 295 for(i = 0; i < smp_cpus; i++) {
296 296 slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
297 297 }
298   - dma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
299   - slavio_irq[hwdef->le_irq], iommu);
  298 + espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
  299 + iommu);
  300 + ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
  301 + slavio_irq[hwdef->le_irq], iommu);
300 302  
301 303 if (graphic_depth != 8 && graphic_depth != 24) {
302 304 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
... ... @@ -307,7 +309,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
307 309 if (nd_table[0].vlan) {
308 310 if (nd_table[0].model == NULL
309 311 || strcmp(nd_table[0].model, "lance") == 0) {
310   - main_lance = lance_init(&nd_table[0], hwdef->le_base, dma,
  312 + main_lance = lance_init(&nd_table[0], hwdef->le_base, ledma,
311 313 slavio_irq[hwdef->le_irq]);
312 314 } else {
313 315 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
... ... @@ -329,7 +331,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
329 331 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
330 332 serial_hds[1], serial_hds[0]);
331 333 fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table);
332   - main_esp = esp_init(bs_table, hwdef->esp_base, dma);
  334 + main_esp = esp_init(bs_table, hwdef->esp_base, espdma);
333 335  
334 336 for (i = 0; i < MAX_DISKS; i++) {
335 337 if (bs_table[i]) {
... ... @@ -341,7 +343,6 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
341 343 slavio_irq[hwdef->me_irq]);
342 344 if (hwdef->cs_base != (target_phys_addr_t)-1)
343 345 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
344   - sparc32_dma_set_reset_data(dma, main_esp, main_lance);
345 346 }
346 347  
347 348 static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device,
... ...
... ... @@ -1046,7 +1046,6 @@ void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1046 1046 /* pcnet.c */
1047 1047  
1048 1048 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1049   -void pcnet_h_reset(void *opaque);
1050 1049 void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1051 1050 qemu_irq irq);
1052 1051  
... ... @@ -1265,11 +1264,9 @@ void slavio_set_power_fail(void *opaque, int power_failing);
1265 1264 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1266 1265 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1267 1266 void *dma_opaque);
1268   -void esp_reset(void *opaque);
1269 1267  
1270 1268 /* sparc32_dma.c */
1271   -void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq espirq,
1272   - qemu_irq leirq, void *iommu);
  1269 +void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu);
1273 1270 void ledma_set_irq(void *opaque, int isr);
1274 1271 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1275 1272 uint8_t *buf, int len, int do_bswap);
... ... @@ -1279,8 +1276,8 @@ void espdma_raise_irq(void *opaque);
1279 1276 void espdma_clear_irq(void *opaque);
1280 1277 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1281 1278 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1282   -void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1283   - void *lance_opaque);
  1279 +void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
  1280 + void *dev_opaque);
1284 1281  
1285 1282 /* cs4231.c */
1286 1283 void cs_init(target_phys_addr_t base, int irq, void *intctl);
... ...