gwj / at91sam9263 · Commits

Commit 5dcb6b914e5b99b64243477a23aea7e2a9852d17

Authored by blueswir1
1 parent 36ddb83b

Use full 36-bit physical address space on SS10 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2830 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 18 changed files with 204 additions and 129 deletions
... ... @@ -64,6 +64,8 @@
64 64  
65 65 #if defined(TARGET_SPARC64)
66 66 #define TARGET_PHYS_ADDR_SPACE_BITS 41
  67 +#elif defined(TARGET_SPARC)
  68 +#define TARGET_PHYS_ADDR_SPACE_BITS 36
67 69 #elif defined(TARGET_ALPHA)
68 70 #define TARGET_PHYS_ADDR_SPACE_BITS 42
69 71 #define TARGET_VIRT_ADDR_SPACE_BITS 42
... ...
hw/esp.c
  View file @5dcb6b9
... ... @@ -562,7 +562,8 @@ void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id)
562 562 s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
563 563 }
564 564  
565   -void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque)
  565 +void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
  566 + void *dma_opaque)
566 567 {
567 568 ESPState *s;
568 569 int esp_io_memory;
... ...
hw/fdc.c
  View file @5dcb6b9
... ... @@ -370,7 +370,7 @@ struct fdctrl_t {
370 370 /* HW */
371 371 qemu_irq irq;
372 372 int dma_chann;
373   - uint32_t io_base;
  373 + target_phys_addr_t io_base;
374 374 /* Controller state */
375 375 QEMUTimer *result_timer;
376 376 uint8_t state;
... ... @@ -464,13 +464,13 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
464 464  
465 465 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
466 466 {
467   - return fdctrl_read(opaque, reg);
  467 + return fdctrl_read(opaque, (uint32_t)reg);
468 468 }
469 469  
470 470 static void fdctrl_write_mem (void *opaque,
471 471 target_phys_addr_t reg, uint32_t value)
472 472 {
473   - fdctrl_write(opaque, reg, value);
  473 + fdctrl_write(opaque, (uint32_t)reg, value);
474 474 }
475 475  
476 476 static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
... ... @@ -579,7 +579,7 @@ static void fdctrl_external_reset(void *opaque)
579 579 }
580 580  
581 581 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
582   - uint32_t io_base,
  582 + target_phys_addr_t io_base,
583 583 BlockDriverState **fds)
584 584 {
585 585 fdctrl_t *fdctrl;
... ... @@ -613,10 +613,14 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
613 613 io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write, fdctrl);
614 614 cpu_register_physical_memory(io_base, 0x08, io_mem);
615 615 } else {
616   - register_ioport_read(io_base + 0x01, 5, 1, &fdctrl_read, fdctrl);
617   - register_ioport_read(io_base + 0x07, 1, 1, &fdctrl_read, fdctrl);
618   - register_ioport_write(io_base + 0x01, 5, 1, &fdctrl_write, fdctrl);
619   - register_ioport_write(io_base + 0x07, 1, 1, &fdctrl_write, fdctrl);
  616 + register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
  617 + fdctrl);
  618 + register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
  619 + fdctrl);
  620 + register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
  621 + fdctrl);
  622 + register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
  623 + fdctrl);
620 624 }
621 625 register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
622 626 qemu_register_reset(fdctrl_external_reset, fdctrl);
... ...
hw/iommu.c
  View file @5dcb6b9
... ... @@ -87,15 +87,15 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
87 87 #define PAGE_MASK (PAGE_SIZE - 1)
88 88  
89 89 typedef struct IOMMUState {
90   - uint32_t addr;
  90 + target_phys_addr_t addr;
91 91 uint32_t regs[IOMMU_NREGS];
92   - uint32_t iostart;
  92 + target_phys_addr_t iostart;
93 93 } IOMMUState;
94 94  
95 95 static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
96 96 {
97 97 IOMMUState *s = opaque;
98   - uint32_t saddr;
  98 + target_phys_addr_t saddr;
99 99  
100 100 saddr = (addr - s->addr) >> 2;
101 101 switch (saddr) {
... ... @@ -110,7 +110,7 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
110 110 static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
111 111 {
112 112 IOMMUState *s = opaque;
113   - uint32_t saddr;
  113 + target_phys_addr_t saddr;
114 114  
115 115 saddr = (addr - s->addr) >> 2;
116 116 DPRINTF("write reg[%d] = %x\n", saddr, val);
... ... @@ -118,32 +118,32 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
118 118 case IOMMU_CTRL:
119 119 switch (val & IOMMU_CTRL_RNGE) {
120 120 case IOMMU_RNGE_16MB:
121   - s->iostart = 0xff000000;
  121 + s->iostart = 0xffffffffff000000ULL;
122 122 break;
123 123 case IOMMU_RNGE_32MB:
124   - s->iostart = 0xfe000000;
  124 + s->iostart = 0xfffffffffe000000ULL;
125 125 break;
126 126 case IOMMU_RNGE_64MB:
127   - s->iostart = 0xfc000000;
  127 + s->iostart = 0xfffffffffc000000ULL;
128 128 break;
129 129 case IOMMU_RNGE_128MB:
130   - s->iostart = 0xf8000000;
  130 + s->iostart = 0xfffffffff8000000ULL;
131 131 break;
132 132 case IOMMU_RNGE_256MB:
133   - s->iostart = 0xf0000000;
  133 + s->iostart = 0xfffffffff0000000ULL;
134 134 break;
135 135 case IOMMU_RNGE_512MB:
136   - s->iostart = 0xe0000000;
  136 + s->iostart = 0xffffffffe0000000ULL;
137 137 break;
138 138 case IOMMU_RNGE_1GB:
139   - s->iostart = 0xc0000000;
  139 + s->iostart = 0xffffffffc0000000ULL;
140 140 break;
141 141 default:
142 142 case IOMMU_RNGE_2GB:
143   - s->iostart = 0x80000000;
  143 + s->iostart = 0xffffffff80000000ULL;
144 144 break;
145 145 }
146   - DPRINTF("iostart = %x\n", s->iostart);
  146 + DPRINTF("iostart = %llx\n", s->iostart);
147 147 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
148 148 break;
149 149 case IOMMU_BASE:
... ... @@ -186,7 +186,7 @@ static CPUWriteMemoryFunc *iommu_mem_write[3] = {
186 186 iommu_mem_writew,
187 187 };
188 188  
189   -static uint32_t iommu_page_get_flags(IOMMUState *s, uint32_t addr)
  189 +static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
190 190 {
191 191 uint32_t iopte;
192 192  
... ... @@ -196,21 +196,27 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, uint32_t addr)
196 196 return ldl_phys(iopte);
197 197 }
198 198  
199   -static uint32_t iommu_translate_pa(IOMMUState *s, uint32_t addr, uint32_t pa)
  199 +static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
  200 + target_phys_addr_t addr,
  201 + uint32_t pte)
200 202 {
201 203 uint32_t tmppte;
  204 + target_phys_addr_t pa;
  205 +
  206 + tmppte = pte;
  207 + pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
  208 + DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
  209 + " (iopte = %x)\n", addr, pa, tmppte);
202 210  
203   - tmppte = pa;
204   - pa = ((pa & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
205   - DPRINTF("xlate dva %x => pa %x (iopte = %x)\n", addr, pa, tmppte);
206 211 return pa;
207 212 }
208 213  
209 214 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
210 215 uint8_t *buf, int len, int is_write)
211 216 {
212   - int l, flags;
213   - target_ulong page, phys_addr;
  217 + int l;
  218 + uint32_t flags;
  219 + target_phys_addr_t page, phys_addr;
214 220  
215 221 while (len > 0) {
216 222 page = addr & TARGET_PAGE_MASK;
... ... @@ -239,10 +245,9 @@ static void iommu_save(QEMUFile *f, void *opaque)
239 245 IOMMUState *s = opaque;
240 246 int i;
241 247  
242   - qemu_put_be32s(f, &s->addr);
243 248 for (i = 0; i < IOMMU_NREGS; i++)
244 249 qemu_put_be32s(f, &s->regs[i]);
245   - qemu_put_be32s(f, &s->iostart);
  250 + qemu_put_be64s(f, &s->iostart);
246 251 }
247 252  
248 253 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
... ... @@ -250,13 +255,12 @@ static int iommu_load(QEMUFile *f, void *opaque, int version_id)
250 255 IOMMUState *s = opaque;
251 256 int i;
252 257  
253   - if (version_id != 1)
  258 + if (version_id != 2)
254 259 return -EINVAL;
255 260  
256   - qemu_get_be32s(f, &s->addr);
257 261 for (i = 0; i < IOMMU_NREGS; i++)
258 262 qemu_put_be32s(f, &s->regs[i]);
259   - qemu_get_be32s(f, &s->iostart);
  263 + qemu_get_be64s(f, &s->iostart);
260 264  
261 265 return 0;
262 266 }
... ... @@ -270,7 +274,7 @@ static void iommu_reset(void *opaque)
270 274 s->regs[0] = IOMMU_VERSION;
271 275 }
272 276  
273   -void *iommu_init(uint32_t addr)
  277 +void *iommu_init(target_phys_addr_t addr)
274 278 {
275 279 IOMMUState *s;
276 280 int iommu_io_memory;
... ... @@ -284,7 +288,7 @@ void *iommu_init(uint32_t addr)
284 288 iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
285 289 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
286 290  
287   - register_savevm("iommu", addr, 1, iommu_save, iommu_load, s);
  291 + register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
288 292 qemu_register_reset(iommu_reset, s);
289 293 return s;
290 294 }
... ...
hw/m48t59.c
  View file @5dcb6b9
... ... @@ -43,7 +43,7 @@ struct m48t59_t {
43 43 /* Hardware parameters */
44 44 qemu_irq IRQ;
45 45 int mem_index;
46   - uint32_t mem_base;
  46 + target_phys_addr_t mem_base;
47 47 uint32_t io_base;
48 48 uint16_t size;
49 49 /* RTC management */
... ... @@ -610,12 +610,12 @@ static void m48t59_reset(void *opaque)
610 610 }
611 611  
612 612 /* Initialisation routine */
613   -m48t59_t *m48t59_init (qemu_irq IRQ, target_ulong mem_base,
  613 +m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
614 614 uint32_t io_base, uint16_t size,
615 615 int type)
616 616 {
617 617 m48t59_t *s;
618   - target_ulong save_base;
  618 + target_phys_addr_t save_base;
619 619  
620 620 s = qemu_mallocz(sizeof(m48t59_t));
621 621 if (!s)
... ...
hw/m48t59.h
  View file @5dcb6b9
... ... @@ -6,7 +6,7 @@ typedef struct m48t59_t m48t59_t;
6 6 void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val);
7 7 uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr);
8 8 void m48t59_toggle_lock (m48t59_t *NVRAM, int lock);
9   -m48t59_t *m48t59_init (qemu_irq IRQ, target_ulong mem_base,
  9 +m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
10 10 uint32_t io_base, uint16_t size,
11 11 int type);
12 12  
... ...
hw/pcnet.c
  View file @5dcb6b9
... ... @@ -2018,7 +2018,8 @@ static CPUWriteMemoryFunc *lance_mem_write[3] = {
2018 2018 (CPUWriteMemoryFunc *)&pcnet_ioport_writew,
2019 2019 };
2020 2020  
2021   -void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque, qemu_irq irq)
  2021 +void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
  2022 + qemu_irq irq)
2022 2023 {
2023 2024 PCNetState *d;
2024 2025 int lance_io_memory;
... ...
hw/slavio_intctl.c
  View file @5dcb6b9
... ... @@ -371,7 +371,7 @@ void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
371 371 s->cpu_envs[cpu] = env;
372 372 }
373 373  
374   -void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
  374 +void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
375 375 const uint32_t *intbit_to_level,
376 376 qemu_irq **irq)
377 377 {
... ...
hw/slavio_misc.c
  View file @5dcb6b9
... ... @@ -212,7 +212,8 @@ static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
212 212 return 0;
213 213 }
214 214  
215   -void *slavio_misc_init(uint32_t base, qemu_irq irq)
  215 +void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
  216 + qemu_irq irq)
216 217 {
217 218 int slavio_misc_io_memory;
218 219 MiscState *s;
... ... @@ -235,7 +236,7 @@ void *slavio_misc_init(uint32_t base, qemu_irq irq)
235 236 // System control
236 237 cpu_register_physical_memory(base + 0x1f00000, MISC_MAXADDR, slavio_misc_io_memory);
237 238 // Power management
238   - cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory);
  239 + cpu_register_physical_memory(power_base, MISC_MAXADDR, slavio_misc_io_memory);
239 240  
240 241 s->irq = irq;
241 242  
... ...
hw/slavio_serial.c
  View file @5dcb6b9
... ... @@ -587,8 +587,8 @@ static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id)
587 587  
588 588 }
589 589  
590   -SerialState *slavio_serial_init(int base, qemu_irq irq, CharDriverState *chr1,
591   - CharDriverState *chr2)
  590 +SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
  591 + CharDriverState *chr1, CharDriverState *chr2)
592 592 {
593 593 int slavio_serial_io_memory, i;
594 594 SerialState *s;
... ... @@ -704,7 +704,7 @@ static void sunmouse_event(void *opaque,
704 704 put_queue(s, 0);
705 705 }
706 706  
707   -void slavio_serial_ms_kbd_init(int base, qemu_irq irq)
  707 +void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq)
708 708 {
709 709 int slavio_serial_io_memory, i;
710 710 SerialState *s;
... ...
hw/slavio_timer.c
  View file @5dcb6b9
... ... @@ -264,8 +264,8 @@ static void slavio_timer_reset(void *opaque)
264 264 slavio_timer_irq(s);
265 265 }
266 266  
267   -void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
268   - void *intctl)
  267 +void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
  268 + unsigned int cpu, void *intctl)
269 269 {
270 270 int slavio_timer_io_memory;
271 271 SLAVIO_TIMERState *s;
... ...
hw/sparc32_dma.c
  View file @5dcb6b9
... ... @@ -249,8 +249,8 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
249 249 return 0;
250 250 }
251 251  
252   -void *sparc32_dma_init(uint32_t daddr, qemu_irq espirq, qemu_irq leirq,
253   - void *iommu)
  252 +void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq espirq,
  253 + qemu_irq leirq, void *iommu)
254 254 {
255 255 DMAState *s;
256 256 int dma_io_memory;
... ...
hw/sun4m.c
  View file @5dcb6b9
... ... @@ -48,11 +48,11 @@
48 48 #define MAX_CPUS 16
49 49  
50 50 struct hwdef {
51   - target_ulong iommu_base, slavio_base;
52   - target_ulong intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
53   - target_ulong fd_base;
54   - target_ulong dma_base, esp_base, le_base;
55   - target_ulong tcx_base, cs_base;
  51 + target_phys_addr_t iommu_base, slavio_base;
  52 + target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
  53 + target_phys_addr_t serial_base, fd_base;
  54 + target_phys_addr_t dma_base, esp_base, le_base;
  55 + target_phys_addr_t tcx_base, cs_base, power_base;
56 56 long vram_size, nvram_size;
57 57 // IRQ numbers are not PIL ones, but master interrupt controller register
58 58 // bit numbers
... ... @@ -289,7 +289,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
289 289  
290 290 iommu = iommu_init(hwdef->iommu_base);
291 291 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
292   - hwdef->intctl_base + 0x10000,
  292 + hwdef->intctl_base + 0x10000ULL,
293 293 &hwdef->intbit_to_level[0],
294 294 &slavio_irq);
295 295 for(i = 0; i < smp_cpus; i++) {
... ... @@ -317,10 +317,11 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
317 317 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
318 318 hwdef->nvram_size, 8);
319 319 for (i = 0; i < MAX_CPUS; i++) {
320   - slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE,
  320 + slavio_timer_init(hwdef->counter_base +
  321 + (target_phys_addr_t)(i * TARGET_PAGE_SIZE),
321 322 hwdef->clock_irq, 0, i, slavio_intctl);
322 323 }
323   - slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2,
  324 + slavio_timer_init(hwdef->counter_base + 0x10000ULL, hwdef->clock1_irq, 2,
324 325 (unsigned int)-1, slavio_intctl);
325 326 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);
326 327 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
... ... @@ -336,9 +337,9 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
336 337 }
337 338 }
338 339  
339   - slavio_misc = slavio_misc_init(hwdef->slavio_base,
  340 + slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,
340 341 slavio_irq[hwdef->me_irq]);
341   - if (hwdef->cs_base != (target_ulong)-1)
  342 + if (hwdef->cs_base != (target_phys_addr_t)-1)
342 343 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
343 344 sparc32_dma_set_reset_data(dma, main_esp, main_lance);
344 345 }
... ... @@ -424,6 +425,7 @@ static const struct hwdef hwdefs[] = {
424 425 .dma_base = 0x78400000,
425 426 .esp_base = 0x78800000,
426 427 .le_base = 0x78c00000,
  428 + .power_base = 0x7a000000,
427 429 .vram_size = 0x00100000,
428 430 .nvram_size = 0x2000,
429 431 .esp_irq = 18,
... ... @@ -443,19 +445,20 @@ static const struct hwdef hwdefs[] = {
443 445 },
444 446 /* SS-10 */
445 447 {
446   - .iommu_base = 0xe0000000, // XXX Actually at 0xfe0000000ULL (36 bits)
447   - .tcx_base = 0x20000000, // 0xe20000000ULL,
  448 + .iommu_base = 0xfe0000000ULL,
  449 + .tcx_base = 0xe20000000ULL,
448 450 .cs_base = -1,
449   - .slavio_base = 0xf0000000, // 0xff0000000ULL,
450   - .ms_kb_base = 0xf1000000, // 0xff1000000ULL,
451   - .serial_base = 0xf1100000, // 0xff1100000ULL,
452   - .nvram_base = 0xf1200000, // 0xff1200000ULL,
453   - .fd_base = 0xf1700000, // 0xff1700000ULL,
454   - .counter_base = 0xf1300000, // 0xff1300000ULL,
455   - .intctl_base = 0xf1400000, // 0xff1400000ULL,
456   - .dma_base = 0xf0400000, // 0xef0400000ULL,
457   - .esp_base = 0xf0800000, // 0xef0800000ULL,
458   - .le_base = 0xf0c00000, // 0xef0c00000ULL,
  451 + .slavio_base = 0xff0000000ULL,
  452 + .ms_kb_base = 0xff1000000ULL,
  453 + .serial_base = 0xff1100000ULL,
  454 + .nvram_base = 0xff1200000ULL,
  455 + .fd_base = 0xff1700000ULL,
  456 + .counter_base = 0xff1300000ULL,
  457 + .intctl_base = 0xff1400000ULL,
  458 + .dma_base = 0xef0400000ULL,
  459 + .esp_base = 0xef0800000ULL,
  460 + .le_base = 0xef0c00000ULL,
  461 + .power_base = 0xefa000000ULL,
459 462 .vram_size = 0x00100000,
460 463 .nvram_size = 0x2000,
461 464 .esp_irq = 18,
... ... @@ -480,9 +483,10 @@ static void sun4m_common_init(int ram_size, int boot_device, DisplayState *ds,
480 483 const char *initrd_filename, const char *cpu_model,
481 484 unsigned int machine, int max_ram)
482 485 {
483   - if (ram_size > max_ram) {
  486 + if ((unsigned int)ram_size > (unsigned int)max_ram) {
484 487 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
485   - ram_size / (1024 * 1024), max_ram / (1024 * 1024));
  488 + (unsigned int)ram_size / (1024 * 1024),
  489 + (unsigned int)max_ram / (1024 * 1024));
486 490 exit(1);
487 491 }
488 492 sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model);
... ... @@ -515,7 +519,7 @@ static void ss10_init(int ram_size, int vga_ram_size, int boot_device,
515 519 cpu_model = "TI SuperSparc II";
516 520 sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
517 521 kernel_cmdline, initrd_filename, cpu_model,
518   - 1, 0x20000000); // XXX tcx overlap, actually first 4GB ok
  522 + 1, PROM_ADDR); // XXX prom overlap, actually first 4GB ok
519 523 }
520 524  
521 525 QEMUMachine ss5_machine = {
... ...
hw/tcx.c
  View file @5dcb6b9
... ... @@ -31,7 +31,7 @@
31 31 #define TCX_TEC_NREGS 0x1000
32 32  
33 33 typedef struct TCXState {
34   - uint32_t addr;
  34 + target_phys_addr_t addr;
35 35 DisplayState *ds;
36 36 uint8_t *vram;
37 37 uint32_t *vram24, *cplane;
... ... @@ -359,7 +359,6 @@ static void tcx_save(QEMUFile *f, void *opaque)
359 359 {
360 360 TCXState *s = opaque;
361 361  
362   - qemu_put_be32s(f, (uint32_t *)&s->addr);
363 362 qemu_put_be32s(f, (uint32_t *)&s->vram);
364 363 qemu_put_be32s(f, (uint32_t *)&s->vram24);
365 364 qemu_put_be32s(f, (uint32_t *)&s->cplane);
... ... @@ -377,10 +376,9 @@ static int tcx_load(QEMUFile *f, void *opaque, int version_id)
377 376 {
378 377 TCXState *s = opaque;
379 378  
380   - if (version_id != 2)
  379 + if (version_id != 3)
381 380 return -EINVAL;
382 381  
383   - qemu_get_be32s(f, (uint32_t *)&s->addr);
384 382 qemu_get_be32s(f, (uint32_t *)&s->vram);
385 383 qemu_get_be32s(f, (uint32_t *)&s->vram24);
386 384 qemu_get_be32s(f, (uint32_t *)&s->cplane);
... ... @@ -492,7 +490,7 @@ static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
492 490 tcx_dummy_writel,
493 491 };
494 492  
495   -void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
  493 +void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
496 494 unsigned long vram_offset, int vram_size, int width, int height,
497 495 int depth)
498 496 {
... ... @@ -513,23 +511,23 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
513 511 // 8-bit plane
514 512 s->vram = vram_base;
515 513 size = vram_size;
516   - cpu_register_physical_memory(addr + 0x00800000, size, vram_offset);
  514 + cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
517 515 vram_offset += size;
518 516 vram_base += size;
519 517  
520 518 io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
521   - cpu_register_physical_memory(addr + 0x00200000, TCX_DAC_NREGS, io_memory);
  519 + cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory);
522 520  
523 521 dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
524 522 s);
525   - cpu_register_physical_memory(addr + 0x00700000, TCX_TEC_NREGS,
  523 + cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
526 524 dummy_memory);
527 525 if (depth == 24) {
528 526 // 24-bit plane
529 527 size = vram_size * 4;
530 528 s->vram24 = (uint32_t *)vram_base;
531 529 s->vram24_offset = vram_offset;
532   - cpu_register_physical_memory(addr + 0x02000000, size, vram_offset);
  530 + cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
533 531 vram_offset += size;
534 532 vram_base += size;
535 533  
... ... @@ -537,20 +535,20 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
537 535 size = vram_size * 4;
538 536 s->cplane = (uint32_t *)vram_base;
539 537 s->cplane_offset = vram_offset;
540   - cpu_register_physical_memory(addr + 0x0a000000, size, vram_offset);
  538 + cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
541 539 graphic_console_init(s->ds, tcx24_update_display,
542 540 tcx24_invalidate_display, tcx24_screen_dump, s);
543 541 } else {
544   - cpu_register_physical_memory(addr + 0x00300000, TCX_THC_NREGS_8,
  542 + cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
545 543 dummy_memory);
546 544 graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
547 545 tcx_screen_dump, s);
548 546 }
549 547 // NetBSD writes here even with 8-bit display
550   - cpu_register_physical_memory(addr + 0x00301000, TCX_THC_NREGS_24,
  548 + cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
551 549 dummy_memory);
552 550  
553   - register_savevm("tcx", addr, 1, tcx_save, tcx_load, s);
  551 + register_savevm("tcx", addr, 3, tcx_save, tcx_load, s);
554 552 qemu_register_reset(tcx_reset, s);
555 553 tcx_reset(s);
556 554 dpy_resize(s->ds, width, height);
... ...
target-sparc/cpu.h
  View file @5dcb6b9
... ... @@ -290,7 +290,7 @@ void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
290 290  
291 291 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
292 292 void raise_exception(int tt);
293   -void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
  293 +void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
294 294 int is_asi);
295 295  
296 296 #include "cpu-all.h"
... ...
target-sparc/helper.c
  View file @5dcb6b9
... ... @@ -117,7 +117,7 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
117 117 }
118 118  
119 119 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
120   - *physical = 0xfffff000;
  120 + *physical = 0xffffffffffff0000ULL;
121 121  
122 122 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
123 123 /* Context base + context number */
... ... @@ -203,7 +203,7 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
203 203  
204 204 /* Even if large ptes, we map only one 4KB page in the cache to
205 205 avoid filling it too fast */
206   - *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
  206 + *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
207 207 return error_code;
208 208 }
209 209  
... ... @@ -212,7 +212,7 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
212 212 int is_user, int is_softmmu)
213 213 {
214 214 target_phys_addr_t paddr;
215   - unsigned long vaddr;
  215 + target_ulong vaddr;
216 216 int error_code = 0, prot, ret = 0, access_index;
217 217  
218 218 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
... ... @@ -220,7 +220,8 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
220 220 vaddr = address & TARGET_PAGE_MASK;
221 221 paddr &= TARGET_PAGE_MASK;
222 222 #ifdef DEBUG_MMU
223   - printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
  223 + printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
  224 + TARGET_FMT_lx "\n", address, paddr, vaddr);
224 225 #endif
225 226 ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
226 227 return ret;
... ... @@ -255,7 +256,8 @@ target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
255 256 uint32_t pde;
256 257  
257 258 /* Context base + context number */
258   - pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
  259 + pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
  260 + (env->mmuregs[2] << 2);
259 261 pde = ldl_phys(pde_ptr);
260 262  
261 263 switch (pde & PTE_ENTRYTYPE_MASK) {
... ... @@ -314,30 +316,35 @@ target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
314 316 #ifdef DEBUG_MMU
315 317 void dump_mmu(CPUState *env)
316 318 {
317   - target_ulong va, va1, va2;
318   - unsigned int n, m, o;
319   - target_phys_addr_t pde_ptr, pa;
  319 + target_ulong va, va1, va2;
  320 + unsigned int n, m, o;
  321 + target_phys_addr_t pde_ptr, pa;
320 322 uint32_t pde;
321 323  
322 324 printf("MMU dump:\n");
323 325 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
324 326 pde = ldl_phys(pde_ptr);
325   - printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
  327 + printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
  328 + (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
326 329 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
327   - pde_ptr = mmu_probe(env, va, 2);
328   - if (pde_ptr) {
  330 + pde = mmu_probe(env, va, 2);
  331 + if (pde) {
329 332 pa = cpu_get_phys_page_debug(env, va);
330   - printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
  333 + printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
  334 + " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
331 335 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
332   - pde_ptr = mmu_probe(env, va1, 1);
333   - if (pde_ptr) {
  336 + pde = mmu_probe(env, va1, 1);
  337 + if (pde) {
334 338 pa = cpu_get_phys_page_debug(env, va1);
335   - printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
  339 + printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
  340 + " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
336 341 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
337   - pde_ptr = mmu_probe(env, va2, 0);
338   - if (pde_ptr) {
  342 + pde = mmu_probe(env, va2, 0);
  343 + if (pde) {
339 344 pa = cpu_get_phys_page_debug(env, va2);
340   - printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
  345 + printf(" VA: " TARGET_FMT_lx ", PA: "
  346 + TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
  347 + va2, pa, pde);
341 348 }
342 349 }
343 350 }
... ...
target-sparc/op_helper.c
  View file @5dcb6b9
... ... @@ -223,7 +223,31 @@ void helper_ld_asi(int asi, int size, int sign)
223 223 break;
224 224 }
225 225 break;
226   - case 0x21 ... 0x2f: /* MMU passthrough, unassigned */
  226 + case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
  227 + case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
  228 + switch(size) {
  229 + case 1:
  230 + ret = ldub_phys((target_phys_addr_t)T0
  231 + | ((target_phys_addr_t)(asi & 0xf) << 32));
  232 + break;
  233 + case 2:
  234 + ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
  235 + | ((target_phys_addr_t)(asi & 0xf) << 32));
  236 + break;
  237 + default:
  238 + case 4:
  239 + ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
  240 + | ((target_phys_addr_t)(asi & 0xf) << 32));
  241 + break;
  242 + case 8:
  243 + ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
  244 + | ((target_phys_addr_t)(asi & 0xf) << 32));
  245 + T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3)
  246 + | ((target_phys_addr_t)(asi & 0xf) << 32));
  247 + break;
  248 + }
  249 + break;
  250 + case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
227 251 default:
228 252 do_unassigned_access(T0, 0, 0, 1);
229 253 ret = 0;
... ... @@ -360,12 +384,38 @@ void helper_st_asi(int asi, int size, int sign)
360 384 }
361 385 }
362 386 return;
  387 + case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
  388 + case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
  389 + {
  390 + switch(size) {
  391 + case 1:
  392 + stb_phys((target_phys_addr_t)T0
  393 + | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
  394 + break;
  395 + case 2:
  396 + stw_phys((target_phys_addr_t)(T0 & ~1)
  397 + | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
  398 + break;
  399 + case 4:
  400 + default:
  401 + stl_phys((target_phys_addr_t)(T0 & ~3)
  402 + | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
  403 + break;
  404 + case 8:
  405 + stl_phys((target_phys_addr_t)(T0 & ~3)
  406 + | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
  407 + stl_phys((target_phys_addr_t)((T0 + 4) & ~3)
  408 + | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
  409 + break;
  410 + }
  411 + }
  412 + return;
363 413 case 0x31: /* Ross RT620 I-cache flush */
364 414 case 0x36: /* I-cache flash clear */
365 415 case 0x37: /* D-cache flash clear */
366 416 break;
367 417 case 9: /* Supervisor code access, XXX */
368   - case 0x21 ... 0x2f: /* MMU passthrough, unassigned */
  418 + case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
369 419 default:
370 420 do_unassigned_access(T0, 1, 0, 1);
371 421 return;
... ... @@ -1035,7 +1085,7 @@ void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
1035 1085 #endif
1036 1086  
1037 1087 #ifndef TARGET_SPARC64
1038   -void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
  1088 +void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1039 1089 int is_asi)
1040 1090 {
1041 1091 CPUState *saved_env;
... ... @@ -1058,7 +1108,7 @@ void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
1058 1108 env->mmuregs[4] = addr; /* Fault address register */
1059 1109 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1060 1110 #ifdef DEBUG_UNASSIGNED
1061   - printf("Unassigned mem access to " TARGET_FMT_lx " from " TARGET_FMT_lx
  1111 + printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
1062 1112 "\n", addr, env->pc);
1063 1113 #endif
1064 1114 raise_exception(TT_DATA_ACCESS);
... ... @@ -1066,7 +1116,7 @@ void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
1066 1116 env = saved_env;
1067 1117 }
1068 1118 #else
1069   -void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
  1119 +void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1070 1120 int is_asi)
1071 1121 {
1072 1122 #ifdef DEBUG_UNASSIGNED
... ... @@ -1076,7 +1126,7 @@ void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
1076 1126 generated code */
1077 1127 saved_env = env;
1078 1128 env = cpu_single_env;
1079   - printf("Unassigned mem access to " TARGET_FMT_lx " from " TARGET_FMT_lx "\n",
  1129 + printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
1080 1130 addr, env->pc);
1081 1131 env = saved_env;
1082 1132 #endif
... ...
... ... @@ -1024,7 +1024,7 @@ extern BlockDriverState *fd_table[MAX_FD];
1024 1024 typedef struct fdctrl_t fdctrl_t;
1025 1025  
1026 1026 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1027   - uint32_t io_base,
  1027 + target_phys_addr_t io_base,
1028 1028 BlockDriverState **fds);
1029 1029 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1030 1030  
... ... @@ -1047,7 +1047,8 @@ void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1047 1047  
1048 1048 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1049 1049 void pcnet_h_reset(void *opaque);
1050   -void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque, qemu_irq irq);
  1050 +void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
  1051 + qemu_irq irq);
1051 1052  
1052 1053 /* vmmouse.c */
1053 1054 void *vmmouse_init(void *m);
... ... @@ -1208,7 +1209,7 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1208 1209 extern QEMUMachine ss5_machine, ss10_machine;
1209 1210  
1210 1211 /* iommu.c */
1211   -void *iommu_init(uint32_t addr);
  1212 +void *iommu_init(target_phys_addr_t addr);
1212 1213 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1213 1214 uint8_t *buf, int len, int is_write);
1214 1215 static inline void sparc_iommu_memory_read(void *opaque,
... ... @@ -1226,13 +1227,13 @@ static inline void sparc_iommu_memory_write(void *opaque,
1226 1227 }
1227 1228  
1228 1229 /* tcx.c */
1229   -void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
1230   - unsigned long vram_offset, int vram_size, int width, int height,
  1230 +void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
  1231 + unsigned long vram_offset, int vram_size, int width, int height,
1231 1232 int depth);
1232 1233  
1233 1234 /* slavio_intctl.c */
1234 1235 void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
1235   -void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
  1236 +void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1236 1237 const uint32_t *intbit_to_level,
1237 1238 qemu_irq **irq);
1238 1239 void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
... ... @@ -1248,26 +1249,28 @@ int load_aout(const char *filename, uint8_t *addr);
1248 1249 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1249 1250  
1250 1251 /* slavio_timer.c */
1251   -void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
1252   - void *intctl);
  1252 +void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
  1253 + unsigned int cpu, void *intctl);
1253 1254  
1254 1255 /* slavio_serial.c */
1255   -SerialState *slavio_serial_init(int base, qemu_irq irq, CharDriverState *chr1,
1256   - CharDriverState *chr2);
1257   -void slavio_serial_ms_kbd_init(int base, qemu_irq);
  1256 +SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
  1257 + CharDriverState *chr1, CharDriverState *chr2);
  1258 +void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1258 1259  
1259 1260 /* slavio_misc.c */
1260   -void *slavio_misc_init(uint32_t base, qemu_irq irq);
  1261 +void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
  1262 + qemu_irq irq);
1261 1263 void slavio_set_power_fail(void *opaque, int power_failing);
1262 1264  
1263 1265 /* esp.c */
1264 1266 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1265   -void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
  1267 +void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
  1268 + void *dma_opaque);
1266 1269 void esp_reset(void *opaque);
1267 1270  
1268 1271 /* sparc32_dma.c */
1269   -void *sparc32_dma_init(uint32_t daddr, qemu_irq espirq, qemu_irq leirq,
1270   - void *iommu);
  1272 +void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq espirq,
  1273 + qemu_irq leirq, void *iommu);
1271 1274 void ledma_set_irq(void *opaque, int isr);
1272 1275 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1273 1276 uint8_t *buf, int len, int do_bswap);
... ...