gwj / at91sam9263 · Commits

Commit e42c20b41a698ceb51f90afb25f1062b333b1913

Authored by blueswir1
1 parent a4fc08ff

Give ECC controller an IRQ (Robert Reif) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3923 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 11 additions and 5 deletions
hw/eccmemctl.c
  View file @e42c20b
... ... @@ -68,7 +68,7 @@
68 68 #define ECC_FAR0_TYPE 0x000000f0 /* Transaction type */
69 69 #define ECC_FAR0_SIZE 0x00000700 /* Transaction size */
70 70 #define ECC_FAR0_CACHE 0x00000800 /* Mapped cacheable */
71   -#define ECC_FAR0_LOCK 0x00001000 /* Error occurred in attomic cycle */
  71 +#define ECC_FAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */
72 72 #define ECC_FAR0_BMODE 0x00002000 /* Boot mode */
73 73 #define ECC_FAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
74 74 #define ECC_FAR0_S 0x08000000 /* Supervisor mode */
... ... @@ -90,6 +90,7 @@
90 90 #define ECC_ADDR_MASK (ECC_SIZE - 1)
91 91  
92 92 typedef struct ECCState {
  93 + qemu_irq irq;
93 94 uint32_t regs[ECC_NREGS];
94 95 } ECCState;
95 96  
... ... @@ -222,7 +223,7 @@ static void ecc_reset(void *opaque)
222 223 s->regs[i] = 0;
223 224 }
224 225  
225   -void * ecc_init(target_phys_addr_t base, uint32_t version)
  226 +void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
226 227 {
227 228 int ecc_io_memory;
228 229 ECCState *s;
... ... @@ -232,6 +233,7 @@ void * ecc_init(target_phys_addr_t base, uint32_t version)
232 233 return NULL;
233 234  
234 235 s->regs[0] = version;
  236 + s->irq = irq;
235 237  
236 238 ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
237 239 cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
... ...
hw/sun4m.c
  View file @e42c20b
... ... @@ -91,7 +91,7 @@ struct hwdef {
91 91 // IRQ numbers are not PIL ones, but master interrupt controller
92 92 // register bit numbers
93 93 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
94   - int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
  94 + int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
95 95 int machine_id; // For NVRAM
96 96 uint32_t iommu_version;
97 97 uint32_t intbit_to_level[32];
... ... @@ -528,7 +528,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
528 528 graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
529 529  
530 530 if (hwdef->ecc_base != (target_phys_addr_t)-1)
531   - ecc_init(hwdef->ecc_base, hwdef->ecc_version);
  531 + ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
  532 + hwdef->ecc_version);
532 533 }
533 534  
534 535 static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
... ... @@ -742,6 +743,7 @@ static const struct hwdef hwdefs[] = {
742 743 .fd_irq = 22,
743 744 .me_irq = 30,
744 745 .cs_irq = -1,
  746 + .ecc_irq = 28,
745 747 .machine_id = 0x72,
746 748 .iommu_version = 0x03000000,
747 749 .intbit_to_level = {
... ... @@ -783,6 +785,7 @@ static const struct hwdef hwdefs[] = {
783 785 .fd_irq = 22,
784 786 .me_irq = 30,
785 787 .cs_irq = -1,
  788 + .ecc_irq = 28,
786 789 .machine_id = 0x71,
787 790 .iommu_version = 0x01000000,
788 791 .intbit_to_level = {
... ... @@ -824,6 +827,7 @@ static const struct hwdef hwdefs[] = {
824 827 .fd_irq = 22,
825 828 .me_irq = 30,
826 829 .cs_irq = -1,
  830 + .ecc_irq = 28,
827 831 .machine_id = 0x72,
828 832 .iommu_version = 0x13000000,
829 833 .intbit_to_level = {
... ...
hw/sun4m.h
  View file @e42c20b
... ... @@ -81,6 +81,6 @@ void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
81 81 qemu_irq irq, qemu_irq *reset);
82 82  
83 83 /* eccmemctl.c */
84   -void *ecc_init(target_phys_addr_t base, uint32_t version);
  84 +void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version);
85 85  
86 86 #endif
... ...