gwj / at91sam9263 · Commits

Commit 0019ad5346509406e93373b58d3066868ea30b96

Authored by blueswir1
1 parent 67e42751

Rearrange slavio_misc code to prepare for different addresses 

Pass first env instead of using cpu_single_env directly
Add Aux1 to Sun4c


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3934 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 175 additions and 80 deletions
hw/slavio_misc.c
  View file @0019ad5
... ... @@ -50,7 +50,7 @@ typedef struct MiscState {
50 50 uint8_t diag, mctrl;
51 51 uint32_t sysctrl;
52 52 uint16_t leds;
53   - target_phys_addr_t power_base;
  53 + CPUState *env;
54 54 } MiscState;
55 55  
56 56 #define MISC_SIZE 1
... ... @@ -62,8 +62,6 @@ typedef struct MiscState {
62 62 #define MISC_MASK 0x0fff0000
63 63 #define MISC_LEDS 0x01600000
64 64 #define MISC_CFG 0x01800000
65   -#define MISC_AUX1 0x01900000
66   -#define MISC_AUX2 0x01910000
67 65 #define MISC_DIAG 0x01a00000
68 66 #define MISC_MDM 0x01b00000
69 67 #define MISC_SYS 0x01f00000
... ... @@ -122,21 +120,6 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
122 120 s->config = val & 0xff;
123 121 slavio_misc_update_irq(s);
124 122 break;
125   - case MISC_AUX1:
126   - MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
127   - s->aux1 = val & 0xff;
128   - break;
129   - case MISC_AUX2:
130   - val &= AUX2_PWRINTCLR | AUX2_PWROFF;
131   - MISC_DPRINTF("Write aux2 %2.2x\n", val);
132   - val |= s->aux2 & AUX2_PWRFAIL;
133   - if (val & AUX2_PWRINTCLR) // Clear Power Fail int
134   - val &= AUX2_PWROFF;
135   - s->aux2 = val;
136   - if (val & AUX2_PWROFF)
137   - qemu_system_shutdown_request();
138   - slavio_misc_update_irq(s);
139   - break;
140 123 case MISC_DIAG:
141 124 MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
142 125 s->diag = val & 0xff;
... ... @@ -146,10 +129,6 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
146 129 s->mctrl = val & 0xff;
147 130 break;
148 131 default:
149   - if (addr == s->power_base) {
150   - MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
151   - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
152   - }
153 132 break;
154 133 }
155 134 }
... ... @@ -164,14 +143,6 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
164 143 ret = s->config;
165 144 MISC_DPRINTF("Read config %2.2x\n", ret);
166 145 break;
167   - case MISC_AUX1:
168   - ret = s->aux1;
169   - MISC_DPRINTF("Read aux1 %2.2x\n", ret);
170   - break;
171   - case MISC_AUX2:
172   - ret = s->aux2;
173   - MISC_DPRINTF("Read aux2 %2.2x\n", ret);
174   - break;
175 146 case MISC_DIAG:
176 147 ret = s->diag;
177 148 MISC_DPRINTF("Read diag %2.2x\n", ret);
... ... @@ -181,9 +152,6 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
181 152 MISC_DPRINTF("Read modem control %2.2x\n", ret);
182 153 break;
183 154 default:
184   - if (addr == s->power_base) {
185   - MISC_DPRINTF("Read power management %2.2x\n", ret);
186   - }
187 155 break;
188 156 }
189 157 return ret;
... ... @@ -201,6 +169,105 @@ static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
201 169 NULL,
202 170 };
203 171  
  172 +static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
  173 + uint32_t val)
  174 +{
  175 + MiscState *s = opaque;
  176 +
  177 + MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
  178 + s->aux1 = val & 0xff;
  179 +}
  180 +
  181 +static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
  182 +{
  183 + MiscState *s = opaque;
  184 + uint32_t ret = 0;
  185 +
  186 + ret = s->aux1;
  187 + MISC_DPRINTF("Read aux1 %2.2x\n", ret);
  188 +
  189 + return ret;
  190 +}
  191 +
  192 +static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
  193 + slavio_aux1_mem_readb,
  194 + NULL,
  195 + NULL,
  196 +};
  197 +
  198 +static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
  199 + slavio_aux1_mem_writeb,
  200 + NULL,
  201 + NULL,
  202 +};
  203 +
  204 +static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
  205 + uint32_t val)
  206 +{
  207 + MiscState *s = opaque;
  208 +
  209 + val &= AUX2_PWRINTCLR | AUX2_PWROFF;
  210 + MISC_DPRINTF("Write aux2 %2.2x\n", val);
  211 + val |= s->aux2 & AUX2_PWRFAIL;
  212 + if (val & AUX2_PWRINTCLR) // Clear Power Fail int
  213 + val &= AUX2_PWROFF;
  214 + s->aux2 = val;
  215 + if (val & AUX2_PWROFF)
  216 + qemu_system_shutdown_request();
  217 + slavio_misc_update_irq(s);
  218 +}
  219 +
  220 +static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
  221 +{
  222 + MiscState *s = opaque;
  223 + uint32_t ret = 0;
  224 +
  225 + ret = s->aux2;
  226 + MISC_DPRINTF("Read aux2 %2.2x\n", ret);
  227 +
  228 + return ret;
  229 +}
  230 +
  231 +static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
  232 + slavio_aux2_mem_readb,
  233 + NULL,
  234 + NULL,
  235 +};
  236 +
  237 +static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
  238 + slavio_aux2_mem_writeb,
  239 + NULL,
  240 + NULL,
  241 +};
  242 +
  243 +static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  244 +{
  245 + MiscState *s = opaque;
  246 +
  247 + MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
  248 + cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
  249 +}
  250 +
  251 +static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
  252 +{
  253 + uint32_t ret = 0;
  254 +
  255 + MISC_DPRINTF("Read power management %2.2x\n", ret);
  256 + return ret;
  257 +}
  258 +
  259 +static CPUReadMemoryFunc *apc_mem_read[3] = {
  260 + apc_mem_readb,
  261 + NULL,
  262 + NULL,
  263 +};
  264 +
  265 +static CPUWriteMemoryFunc *apc_mem_write[3] = {
  266 + apc_mem_writeb,
  267 + NULL,
  268 + NULL,
  269 +};
  270 +
204 271 static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
205 272 {
206 273 MiscState *s = opaque;
... ... @@ -338,57 +405,68 @@ static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
338 405 }
339 406  
340 407 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
341   - qemu_irq irq)
  408 + target_phys_addr_t aux1_base,
  409 + target_phys_addr_t aux2_base, qemu_irq irq,
  410 + CPUState *env)
342 411 {
343   - int slavio_misc_io_memory;
  412 + int io;
344 413 MiscState *s;
345 414  
346 415 s = qemu_mallocz(sizeof(MiscState));
347 416 if (!s)
348 417 return NULL;
349 418  
350   - /* 8 bit registers */
351   - slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
352   - slavio_misc_mem_write, s);
353   - // Slavio control
354   - cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE,
355   - slavio_misc_io_memory);
356   - // AUX 1
357   - cpu_register_physical_memory(base + MISC_AUX1, MISC_SIZE,
358   - slavio_misc_io_memory);
359   - // AUX 2
360   - cpu_register_physical_memory(base + MISC_AUX2, MISC_SIZE,
361   - slavio_misc_io_memory);
362   - // Diagnostics
363   - cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE,
364   - slavio_misc_io_memory);
365   - // Modem control
366   - cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE,
367   - slavio_misc_io_memory);
368   - // Power management
369   - cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
370   - s->power_base = power_base;
371   -
372   - /* 16 bit registers */
373   - slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read,
374   - slavio_led_mem_write, s);
375   - /* ss600mp diag LEDs */
376   - cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE,
377   - slavio_misc_io_memory);
378   -
379   - /* 32 bit registers */
380   - slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
381   - slavio_sysctrl_mem_write,
382   - s);
383   - // System control
384   - cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE,
385   - slavio_misc_io_memory);
  419 + if (base) {
  420 + /* 8 bit registers */
  421 + io = cpu_register_io_memory(0, slavio_misc_mem_read,
  422 + slavio_misc_mem_write, s);
  423 + // Slavio control
  424 + cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
  425 + // Diagnostics
  426 + cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
  427 + // Modem control
  428 + cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
  429 +
  430 + /* 16 bit registers */
  431 + io = cpu_register_io_memory(0, slavio_led_mem_read,
  432 + slavio_led_mem_write, s);
  433 + /* ss600mp diag LEDs */
  434 + cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);
  435 +
  436 + /* 32 bit registers */
  437 + io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
  438 + slavio_sysctrl_mem_write, s);
  439 + // System control
  440 + cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
  441 + }
  442 +
  443 + // AUX 1 (Misc System Functions)
  444 + if (aux1_base) {
  445 + io = cpu_register_io_memory(0, slavio_aux1_mem_read,
  446 + slavio_aux1_mem_write, s);
  447 + cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
  448 + }
  449 +
  450 + // AUX 2 (Software Powerdown Control)
  451 + if (aux2_base) {
  452 + io = cpu_register_io_memory(0, slavio_aux2_mem_read,
  453 + slavio_aux2_mem_write, s);
  454 + cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
  455 + }
  456 +
  457 + // Power management (APC) XXX: not a Slavio device
  458 + if (power_base) {
  459 + io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
  460 + cpu_register_physical_memory(power_base, MISC_SIZE, io);
  461 + }
386 462  
387 463 s->irq = irq;
  464 + s->env = env;
388 465  
389 466 register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
390 467 s);
391 468 qemu_register_reset(slavio_misc_reset, s);
392 469 slavio_misc_reset(s);
  470 +
393 471 return s;
394 472 }
... ...
hw/sun4m.c
  View file @0019ad5
... ... @@ -83,7 +83,7 @@ struct hwdef {
83 83 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
84 84 target_phys_addr_t serial_base, fd_base;
85 85 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
86   - target_phys_addr_t tcx_base, cs_base, power_base;
  86 + target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
87 87 target_phys_addr_t ecc_base;
88 88 uint32_t ecc_version;
89 89 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
... ... @@ -515,8 +515,9 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
515 515 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
516 516 }
517 517  
518   - slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,
519   - slavio_irq[hwdef->me_irq]);
  518 + slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
  519 + hwdef->aux1_base, hwdef->aux2_base,
  520 + slavio_irq[hwdef->me_irq], envs[0]);
520 521 if (hwdef->cs_base != (target_phys_addr_t)-1)
521 522 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
522 523  
... ... @@ -662,6 +663,10 @@ static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
662 663 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
663 664 }
664 665  
  666 + slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
  667 + hwdef->aux1_base, hwdef->aux2_base,
  668 + slavio_irq[hwdef->me_irq], env);
  669 +
665 670 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
666 671 initrd_filename);
667 672  
... ... @@ -687,7 +692,9 @@ static const struct hwdef hwdefs[] = {
687 692 .dma_base = 0x78400000,
688 693 .esp_base = 0x78800000,
689 694 .le_base = 0x78c00000,
690   - .power_base = 0x7a000000,
  695 + .apc_base = 0x7a000000, // XXX 0x6a000000,
  696 + .aux1_base = 0x71900000,
  697 + .aux2_base = 0x71910000,
691 698 .ecc_base = -1,
692 699 .sun4c_intctl_base = -1,
693 700 .sun4c_counter_base = -1,
... ... @@ -727,7 +734,9 @@ static const struct hwdef hwdefs[] = {
727 734 .dma_base = 0xef0400000ULL,
728 735 .esp_base = 0xef0800000ULL,
729 736 .le_base = 0xef0c00000ULL,
730   - .power_base = 0xefa000000ULL,
  737 + .apc_base = 0xefa000000ULL, // XXX should not exist
  738 + .aux1_base = 0xff1900000ULL, // XXX 0xff1800000ULL,
  739 + .aux2_base = 0xff1910000ULL, // XXX 0xff1a01000ULL,
731 740 .ecc_base = 0xf00000000ULL,
732 741 .ecc_version = 0x10000000, // version 0, implementation 1
733 742 .sun4c_intctl_base = -1,
... ... @@ -769,7 +778,9 @@ static const struct hwdef hwdefs[] = {
769 778 .dma_base = 0xef0081000ULL,
770 779 .esp_base = 0xef0080000ULL,
771 780 .le_base = 0xef0060000ULL,
772   - .power_base = 0xefa000000ULL,
  781 + .apc_base = 0xefa000000ULL, // XXX should not exist
  782 + .aux1_base = 0xff1900000ULL, // XXX 0xff1800000ULL,
  783 + .aux2_base = 0xff1910000ULL, // XXX should not exist
773 784 .ecc_base = 0xf00000000ULL,
774 785 .ecc_version = 0x00000000, // version 0, implementation 0
775 786 .sun4c_intctl_base = -1,
... ... @@ -811,7 +822,9 @@ static const struct hwdef hwdefs[] = {
811 822 .dma_base = 0xef0400000ULL,
812 823 .esp_base = 0xef0800000ULL,
813 824 .le_base = 0xef0c00000ULL,
814   - .power_base = 0xefa000000ULL,
  825 + .apc_base = 0xefa000000ULL, // XXX should not exist
  826 + .aux1_base = 0xff1900000ULL, // XXX 0xff1800000ULL,
  827 + .aux2_base = 0xff1910000ULL, // XXX 0xff1a01000ULL,
815 828 .ecc_base = 0xf00000000ULL,
816 829 .ecc_version = 0x20000000, // version 0, implementation 2
817 830 .sun4c_intctl_base = -1,
... ... @@ -852,7 +865,9 @@ static const struct hwdef hwdefs[] = {
852 865 .dma_base = 0xf8400000,
853 866 .esp_base = 0xf8800000,
854 867 .le_base = 0xf8c00000,
855   - .power_base = -1,
  868 + .apc_base = -1,
  869 + .aux1_base = 0xf7400003,
  870 + .aux2_base = -1,
856 871 .sun4c_intctl_base = 0xf5000000,
857 872 .sun4c_counter_base = 0xf3000000,
858 873 .vram_size = 0x00100000,
... ...
hw/sun4m.h
  View file @0019ad5
... ... @@ -54,7 +54,9 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
54 54  
55 55 /* slavio_misc.c */
56 56 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
57   - qemu_irq irq);
  57 + target_phys_addr_t aux1_base,
  58 + target_phys_addr_t aux2_base, qemu_irq irq,
  59 + CPUState *env);
58 60 void slavio_set_power_fail(void *opaque, int power_failing);
59 61  
60 62 /* esp.c */
... ...