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Add support for constant propagation to TCG. This has to be paired with the liveness analysis to remove the dead code. Not all possible operations are covered, but the most common ones are. This improves the code generation for several ARM instructions, like MVN (immediate), and it may help other targets as well. v1 -> v2: Added profiling code and hopefully fixed for 64-bit TCG targets. v2 -> v3: Another attempt at fixing the support for 64-bit TCG targets. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Since no target uses ICOUNT_TEMP anymore there's no reason to keep it. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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The goal is eventually to get rid of all cpu_T register usage and to use just short-lived tmp/tmp2 registers. This patch converts all the places where cpu_T was used in the Thumb code and replaces it with explicit TCG register allocation. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Uninitialized register was used instead of proper TCG variable. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16 helpers used fixed registers to return values. This patch replaces that with TCG code, so T0/T1 is no longer directly used by the helper functions. Bugs in the gen_neon_unzip register load code were also fixed. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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The encoding of 'IA' and 'DB' conditions was swapped. SRS instruction must store banked SPSR instead of CPSR at the specific address. Missing 'return' statement at the end of RFE handling. Fixed write-back code to reference correct registers. From: Hyeonsung Jang <hsjang@ok-labs.com> Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Signed-off-by: Filip Navara <filip.navara@gmail.com>
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The temporary variable cache in no longer need since tcg_temp_free was introduced. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Currently each read/write of ARM register involves a LD/ST TCG operation. This patch uses TCG memory-backed registers to represent the ARM register set. With memory-backed registers the LD/ST operations are transparently generated by TCG and host registers could be used to optimize the generated code. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Only very simple emulation of the LCD controller is included. The controller features the standard HD44780 interface and supports character output on four lines using a static 5x7 font and optional backlight controlled by signal on a separate pin. Capabilities such as custom characters, cursor and 5x10 fonts are not implemented. Saving/loading of device state is not implemented either. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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The board scheme is available at http://support.dce.felk.cvut.cz/e-kurzy/file.php/19/cviceni/Schema.pdf Only the AT91SAM7X microcontroller, rotary encoder, matrix keyboard and their connections are implemented. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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The Ethernet controller is implemented as a device on the system bus. It uses DMA to read and write data from the main memory for packet queues. Most of the controller features are implemented with the following exceptions: - Statistics and related registers - Support of VLAN tags - Support for transmitting jumbo frames - Recognizing of MAC addresses by a hash function The emulation is based on the AT91SAM7X specification and also supports registers present in the older AT91RM9200 controller - notably the TAR register for sending a single frame by writing a physical memory address into it. EMAC also provides management interface for directly talking to the PHY chip. The emulation of PHY chip is currently hard-coded in the EMAC emulation and behaves as a DM9161 chip. Only few registers of the PHY chip are implemented. Nevertheless it's enough to run the Atmel examples and even FreeRTOS demos. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Only the timer part of the the Timer/Counter block is implemented since there is no interface for connection of external clocks in QEMU, so there is nothing to measure. The minimal implementation is done using host timers and an internal counter. This implementation is sufficient for running the Atmel examples, but leaves a lot to be desired. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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The system controller in AT91 is composed of several devices and they are all connected to single IRQ pin on the Advanced Interrupt Controller. This pseudo- device allows multiplexing an IRQ pin by sending logic OR of all the inputs to a single output pin. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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This patch introduces emulation of the AT91 reset controller. The behavior and external interface to the reset controller is not emulated though and only the features necessary to start the system are implemented. Internal registers are maintained and partially emulated. The NRST status bit is always asserted, even if a command to de-assert it is written to the control register. This emulation is sufficient to support running FreeRTOS and a sample code from Atmel. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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This patch implements the RTT used on AT91 microcontrollers. All documented features are implemented. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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This patch implements the PIT used on AT91 microcontrollers. All documented features are implemented. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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This patch implements the GPIO controller used in the AT91 microcontrollers. PIO controller is implemented as a device on the system bus with 3 sets of 32 input/output pins and one IRQ pin. The first set of the 32 I/O pins is used for connections to external devices and the other two are used for pass-through connections of external pins to internal peripherals. Internal pull-up resistors are implemented by simulating the input value of 1 for every input pins where the value of the pin is unknown (a device is not connected) or where explicit -1 constant was sent by the external device emulation (a device is connected, but the wire is not) on the GPIO pin. Unimplemented features are correct emulation of open-drain mode and glitch-filter. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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The debug unit is implemented as serial character device hosted on the system bus. Only the most basic features are emulated to allow capturing the output and receiving external input. No actual timing is emulated based on the baud rate register, although the information is passed to the backend driver using the qemu_chr_ioctl API. A two-byte FIFO transmission register, channel mode (normal, local feedback, remote feedback) and in-circuit emulator (ICE) pins are not emulated. Emulating the first two features would be straightforward. Emulating the ICE communication is possible, but changes to CPU emulation are required to accomplish it. The benefits for debugging would probably not be very high since the built-in QEMU debugger is much more powerful. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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The isolated behavior of PMC is emulated completely, but the effects on other parts of the system are not. Since QEMU lacks any API for proper modeling of the system and peripheral clocks, the actual enabling and disabling of clocks has no effect on the emulated system. The master clock frequency is exposed using a global variable for use by other system components, such as timers. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Emulation of AIC has 32 input pins corresponding to the input interrupt sources and two output pins corresponding to the IRQ and FIQ pins on the processor. All features of the controller with the exception of external interrupt handling are emulated according to the documentation. This includes emulation of the debug register, edge and level triggered interrupts, software interrupts and interrupt nesting. External interrupt handling is not implemented because it differs between various AT91 family microcontrollers in the number of externally exposed pins. The only feature of the external interrupt processing that is not implemented is inverting the level of input signal. Should the need arise, adding proper implementation of external interrupt logic shouldn't be hard. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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This patch introduces an emulation of the standard 4x4 matrix keyboard that could be connected to GPIO controller. It doesn't emulate any pull-up resistors connected to the wires and depends on the GPIO controller for their emulation. This requires the GPIO controller to support the notion of special -1 value on the GPIO pins, which signals that the wire is currently disconnected. The emulation of keys is implemented through standard QEMU keyboard emulation capabilities. An individual key mapping is specified using a device property "keys", which should be set to array of 16 bytes where each byte corresponds to scan code of the key. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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This patch introduces an emulation of the rotary encoder that could be connected to GPIO controller. An internal state is maintained with the values of the output pins. When a key is pressed the state is modified accordingly and the information is signaled on the output pins. Key mappings are specified by the "key-left" and "key-left-alt" properties for a counter-clockwise direction and "key-right" and "key-right-alt" for a clockwise direction. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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While most of the ARMv5 instructions are backward compatible with ARMv4, there are few important differences. Most notably the stack pop and load instructions ignore the lowest bit, which is used by ARMv5 to switch to Thumb mode. A base-updated data-abort model is used on ARM7TDMI, CP15 coprocessor is not present and several instructions of later architectures are not implemented. This patch introduces flags for the V5, CP15 and ABORT_BU (base-updated abort model) features. When V5 feature is not set the bit 0 on POP, LD and LDM of PC register is ignored and doesn't swith to/from Thumb mode and several instructions are treated as unimplemented (BLX, PLD, BKPT, LDRD, STRD). Based on patch by Ulrich Hecht <uli@suse.de>. Signed-off-by: Filip Navara <filip.navara@gmail.com>
