Commit 6767d33340994593840f23e56b54ee4d5f1562bc
1 parent
5df3a524
Ger rid of regs_to_env and env_to_regs, since they are they are no longer used.
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11 changed files
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0 additions
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139 deletions
cpu-exec.c
... | ... | @@ -56,9 +56,6 @@ int qemu_cpu_has_work(CPUState *env) |
56 | 56 | |
57 | 57 | void cpu_loop_exit(void) |
58 | 58 | { |
59 | - /* NOTE: the register at this point must be saved by hand because | |
60 | - longjmp restore them */ | |
61 | - regs_to_env(); | |
62 | 59 | longjmp(env->jmp_env, 1); |
63 | 60 | } |
64 | 61 | |
... | ... | @@ -130,8 +127,6 @@ static TranslationBlock *tb_find_slow(target_ulong pc, |
130 | 127 | |
131 | 128 | tb_invalidated_flag = 0; |
132 | 129 | |
133 | - regs_to_env(); /* XXX: do it just before cpu_gen_code() */ | |
134 | - | |
135 | 130 | /* find translated block using physical mappings */ |
136 | 131 | phys_pc = get_phys_addr_code(env, pc); |
137 | 132 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
... | ... | @@ -230,7 +225,6 @@ int cpu_exec(CPUState *env1) |
230 | 225 | #include "hostregs_helper.h" |
231 | 226 | env = env1; |
232 | 227 | |
233 | - env_to_regs(); | |
234 | 228 | #if defined(TARGET_I386) |
235 | 229 | /* put eflags in CPU temporary format */ |
236 | 230 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
... | ... | @@ -571,7 +565,6 @@ int cpu_exec(CPUState *env1) |
571 | 565 | #ifdef CONFIG_DEBUG_EXEC |
572 | 566 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { |
573 | 567 | /* restore flags in standard format */ |
574 | - regs_to_env(); | |
575 | 568 | #if defined(TARGET_I386) |
576 | 569 | env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
577 | 570 | log_cpu_state(env, X86_DUMP_CCOP); |
... | ... | @@ -689,8 +682,6 @@ int cpu_exec(CPUState *env1) |
689 | 682 | } |
690 | 683 | #endif |
691 | 684 | } /* for(;;) */ |
692 | - } else { | |
693 | - env_to_regs(); | |
694 | 685 | } |
695 | 686 | } /* for(;;) */ |
696 | 687 | ... | ... |
target-alpha/exec.h
... | ... | @@ -39,14 +39,6 @@ register struct CPUAlphaState *env asm(AREG0); |
39 | 39 | #include "softmmu_exec.h" |
40 | 40 | #endif /* !defined(CONFIG_USER_ONLY) */ |
41 | 41 | |
42 | -static always_inline void env_to_regs(void) | |
43 | -{ | |
44 | -} | |
45 | - | |
46 | -static always_inline void regs_to_env(void) | |
47 | -{ | |
48 | -} | |
49 | - | |
50 | 42 | static always_inline int cpu_has_work(CPUState *env) |
51 | 43 | { |
52 | 44 | return (env->interrupt_request & CPU_INTERRUPT_HARD); | ... | ... |
target-arm/exec.h
... | ... | @@ -26,14 +26,6 @@ register struct CPUARMState *env asm(AREG0); |
26 | 26 | #include "cpu.h" |
27 | 27 | #include "exec-all.h" |
28 | 28 | |
29 | -static inline void env_to_regs(void) | |
30 | -{ | |
31 | -} | |
32 | - | |
33 | -static inline void regs_to_env(void) | |
34 | -{ | |
35 | -} | |
36 | - | |
37 | 29 | static inline int cpu_has_work(CPUState *env) |
38 | 30 | { |
39 | 31 | return (env->interrupt_request & | ... | ... |
target-cris/exec.h
... | ... | @@ -24,14 +24,6 @@ register struct CPUCRISState *env asm(AREG0); |
24 | 24 | #include "cpu.h" |
25 | 25 | #include "exec-all.h" |
26 | 26 | |
27 | -static inline void env_to_regs(void) | |
28 | -{ | |
29 | -} | |
30 | - | |
31 | -static inline void regs_to_env(void) | |
32 | -{ | |
33 | -} | |
34 | - | |
35 | 27 | #if !defined(CONFIG_USER_ONLY) |
36 | 28 | #include "softmmu_exec.h" |
37 | 29 | #endif | ... | ... |
target-i386/exec.h
... | ... | @@ -281,62 +281,6 @@ static inline void load_eflags(int eflags, int update_mask) |
281 | 281 | (eflags & update_mask) | 0x2; |
282 | 282 | } |
283 | 283 | |
284 | -static inline void env_to_regs(void) | |
285 | -{ | |
286 | -#ifdef reg_EAX | |
287 | - EAX = env->regs[R_EAX]; | |
288 | -#endif | |
289 | -#ifdef reg_ECX | |
290 | - ECX = env->regs[R_ECX]; | |
291 | -#endif | |
292 | -#ifdef reg_EDX | |
293 | - EDX = env->regs[R_EDX]; | |
294 | -#endif | |
295 | -#ifdef reg_EBX | |
296 | - EBX = env->regs[R_EBX]; | |
297 | -#endif | |
298 | -#ifdef reg_ESP | |
299 | - ESP = env->regs[R_ESP]; | |
300 | -#endif | |
301 | -#ifdef reg_EBP | |
302 | - EBP = env->regs[R_EBP]; | |
303 | -#endif | |
304 | -#ifdef reg_ESI | |
305 | - ESI = env->regs[R_ESI]; | |
306 | -#endif | |
307 | -#ifdef reg_EDI | |
308 | - EDI = env->regs[R_EDI]; | |
309 | -#endif | |
310 | -} | |
311 | - | |
312 | -static inline void regs_to_env(void) | |
313 | -{ | |
314 | -#ifdef reg_EAX | |
315 | - env->regs[R_EAX] = EAX; | |
316 | -#endif | |
317 | -#ifdef reg_ECX | |
318 | - env->regs[R_ECX] = ECX; | |
319 | -#endif | |
320 | -#ifdef reg_EDX | |
321 | - env->regs[R_EDX] = EDX; | |
322 | -#endif | |
323 | -#ifdef reg_EBX | |
324 | - env->regs[R_EBX] = EBX; | |
325 | -#endif | |
326 | -#ifdef reg_ESP | |
327 | - env->regs[R_ESP] = ESP; | |
328 | -#endif | |
329 | -#ifdef reg_EBP | |
330 | - env->regs[R_EBP] = EBP; | |
331 | -#endif | |
332 | -#ifdef reg_ESI | |
333 | - env->regs[R_ESI] = ESI; | |
334 | -#endif | |
335 | -#ifdef reg_EDI | |
336 | - env->regs[R_EDI] = EDI; | |
337 | -#endif | |
338 | -} | |
339 | - | |
340 | 284 | static inline int cpu_has_work(CPUState *env) |
341 | 285 | { |
342 | 286 | int work; | ... | ... |
target-m68k/exec.h
... | ... | @@ -24,14 +24,6 @@ register struct CPUM68KState *env asm(AREG0); |
24 | 24 | #include "cpu.h" |
25 | 25 | #include "exec-all.h" |
26 | 26 | |
27 | -static inline void env_to_regs(void) | |
28 | -{ | |
29 | -} | |
30 | - | |
31 | -static inline void regs_to_env(void) | |
32 | -{ | |
33 | -} | |
34 | - | |
35 | 27 | #if !defined(CONFIG_USER_ONLY) |
36 | 28 | #include "softmmu_exec.h" |
37 | 29 | #endif | ... | ... |
target-microblaze/exec.h
... | ... | @@ -23,14 +23,6 @@ register struct CPUMBState *env asm(AREG0); |
23 | 23 | #include "cpu.h" |
24 | 24 | #include "exec-all.h" |
25 | 25 | |
26 | -static inline void env_to_regs(void) | |
27 | -{ | |
28 | -} | |
29 | - | |
30 | -static inline void regs_to_env(void) | |
31 | -{ | |
32 | -} | |
33 | - | |
34 | 26 | #if !defined(CONFIG_USER_ONLY) |
35 | 27 | #include "softmmu_exec.h" |
36 | 28 | #endif | ... | ... |
target-mips/exec.h
... | ... | @@ -25,14 +25,6 @@ void fpu_dump_state(CPUState *env, FILE *f, |
25 | 25 | void cpu_mips_clock_init (CPUState *env); |
26 | 26 | void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
27 | 27 | |
28 | -static inline void env_to_regs(void) | |
29 | -{ | |
30 | -} | |
31 | - | |
32 | -static inline void regs_to_env(void) | |
33 | -{ | |
34 | -} | |
35 | - | |
36 | 28 | static inline int cpu_has_work(CPUState *env) |
37 | 29 | { |
38 | 30 | return (env->interrupt_request & | ... | ... |
target-ppc/exec.h
... | ... | @@ -35,14 +35,6 @@ register struct CPUPPCState *env asm(AREG0); |
35 | 35 | #include "softmmu_exec.h" |
36 | 36 | #endif /* !defined(CONFIG_USER_ONLY) */ |
37 | 37 | |
38 | -static always_inline void env_to_regs (void) | |
39 | -{ | |
40 | -} | |
41 | - | |
42 | -static always_inline void regs_to_env (void) | |
43 | -{ | |
44 | -} | |
45 | - | |
46 | 38 | static always_inline int cpu_has_work(CPUState *env) |
47 | 39 | { |
48 | 40 | return (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)); | ... | ... |
target-sh4/exec.h
... | ... | @@ -47,14 +47,4 @@ static inline int cpu_halted(CPUState *env) { |
47 | 47 | #include "softmmu_exec.h" |
48 | 48 | #endif |
49 | 49 | |
50 | -static inline void regs_to_env(void) | |
51 | -{ | |
52 | - /* XXXXX */ | |
53 | -} | |
54 | - | |
55 | -static inline void env_to_regs(void) | |
56 | -{ | |
57 | - /* XXXXX */ | |
58 | -} | |
59 | - | |
60 | 50 | #endif /* _EXEC_SH4_H */ | ... | ... |
target-sparc/exec.h
... | ... | @@ -13,14 +13,6 @@ register struct CPUSPARCState *env asm(AREG0); |
13 | 13 | #include "cpu.h" |
14 | 14 | #include "exec-all.h" |
15 | 15 | |
16 | -static inline void env_to_regs(void) | |
17 | -{ | |
18 | -} | |
19 | - | |
20 | -static inline void regs_to_env(void) | |
21 | -{ | |
22 | -} | |
23 | - | |
24 | 16 | /* op_helper.c */ |
25 | 17 | void do_interrupt(CPUState *env); |
26 | 18 | ... | ... |