gwj / at91sam9263 · Commits

Commit a699b51a5afba1cd6e6ecdd7ec32c368febc2cc4

Authored by Filip Navara
1 parent dc5acc23

Convert disas_dsp_insn not use cpu_T. 

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Inline Side-by-side
Showing 1 changed file with 20 additions and 39 deletions
target-arm/translate.c
  View file @a699b51
... ... @@ -1302,21 +1302,6 @@ IWMMXT_OP_ENV(packsw)
1302 1302 IWMMXT_OP_ENV(packsl)
1303 1303 IWMMXT_OP_ENV(packsq)
1304 1304  
1305   -static inline void gen_op_iwmmxt_muladdsl_M0_T0_T1(void)
1306   -{
1307   - gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
1308   -}
1309   -
1310   -static inline void gen_op_iwmmxt_muladdsw_M0_T0_T1(void)
1311   -{
1312   - gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
1313   -}
1314   -
1315   -static inline void gen_op_iwmmxt_muladdswl_M0_T0_T1(void)
1316   -{
1317   - gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
1318   -}
1319   -
1320 1305 static inline void gen_op_iwmmxt_align_M0_T0_wRn(int rn)
1321 1306 {
1322 1307 iwmmxt_load_reg(cpu_V1, rn);
... ... @@ -1381,7 +1366,6 @@ static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1381 1366 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1382 1367 }
1383 1368  
1384   -
1385 1369 static void gen_iwmmxt_movl_T0_T1_wRn(int rn)
1386 1370 {
1387 1371 iwmmxt_load_reg(cpu_V0, rn);
... ... @@ -2382,12 +2366,12 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
2382 2366 case 0x0: /* TMIA */
2383 2367 gen_movl_T0_reg(s, rd0);
2384 2368 gen_movl_T1_reg(s, rd1);
2385   - gen_op_iwmmxt_muladdsl_M0_T0_T1();
  2369 + gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
2386 2370 break;
2387 2371 case 0x8: /* TMIAPH */
2388 2372 gen_movl_T0_reg(s, rd0);
2389 2373 gen_movl_T1_reg(s, rd1);
2390   - gen_op_iwmmxt_muladdsw_M0_T0_T1();
  2374 + gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
2391 2375 break;
2392 2376 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2393 2377 gen_movl_T1_reg(s, rd0);
... ... @@ -2397,7 +2381,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
2397 2381 gen_movl_T1_reg(s, rd1);
2398 2382 if (insn & (1 << 17))
2399 2383 gen_op_shrl_T1_im(16);
2400   - gen_op_iwmmxt_muladdswl_M0_T0_T1();
  2384 + gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
2401 2385 break;
2402 2386 default:
2403 2387 return 1;
... ... @@ -2417,6 +2401,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
2417 2401 static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2418 2402 {
2419 2403 int acc, rd0, rd1, rdhi, rdlo;
  2404 + TCGv tmp, tmp2;
2420 2405  
2421 2406 if ((insn & 0x0ff00f10) == 0x0e200010) {
2422 2407 /* Multiply with Internal Accumulate Format */
... ... @@ -2427,33 +2412,30 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2427 2412 if (acc != 0)
2428 2413 return 1;
2429 2414  
  2415 + tmp = load_reg(s, rd0);
  2416 + tmp2 = load_reg(s, rd1);
2430 2417 switch ((insn >> 16) & 0xf) {
2431 2418 case 0x0: /* MIA */
2432   - gen_movl_T0_reg(s, rd0);
2433   - gen_movl_T1_reg(s, rd1);
2434   - gen_op_iwmmxt_muladdsl_M0_T0_T1();
  2419 + gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2435 2420 break;
2436 2421 case 0x8: /* MIAPH */
2437   - gen_movl_T0_reg(s, rd0);
2438   - gen_movl_T1_reg(s, rd1);
2439   - gen_op_iwmmxt_muladdsw_M0_T0_T1();
  2422 + gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2440 2423 break;
2441 2424 case 0xc: /* MIABB */
2442 2425 case 0xd: /* MIABT */
2443 2426 case 0xe: /* MIATB */
2444 2427 case 0xf: /* MIATT */
2445   - gen_movl_T1_reg(s, rd0);
2446 2428 if (insn & (1 << 16))
2447   - gen_op_shrl_T1_im(16);
2448   - gen_op_movl_T0_T1();
2449   - gen_movl_T1_reg(s, rd1);
  2429 + tcg_gen_shri_i32(tmp, tmp, 16);
2450 2430 if (insn & (1 << 17))
2451   - gen_op_shrl_T1_im(16);
2452   - gen_op_iwmmxt_muladdswl_M0_T0_T1();
  2431 + tcg_gen_shri_i32(tmp2, tmp2, 16);
  2432 + gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2453 2433 break;
2454 2434 default:
2455 2435 return 1;
2456 2436 }
  2437 + dead_tmp(tmp2);
  2438 + dead_tmp(tmp);
2457 2439  
2458 2440 gen_op_iwmmxt_movq_wRn_M0(acc);
2459 2441 return 0;
... ... @@ -2469,15 +2451,14 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2469 2451 return 1;
2470 2452  
2471 2453 if (insn & ARM_CP_RW_BIT) { /* MRA */
2472   - gen_iwmmxt_movl_T0_T1_wRn(acc);
2473   - gen_movl_reg_T0(s, rdlo);
2474   - gen_op_movl_T0_im((1 << (40 - 32)) - 1);
2475   - gen_op_andl_T0_T1();
2476   - gen_movl_reg_T0(s, rdhi);
  2454 + iwmmxt_load_reg(cpu_V0, acc);
  2455 + tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
  2456 + tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
  2457 + tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
  2458 + tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
2477 2459 } else { /* MAR */
2478   - gen_movl_T0_reg(s, rdlo);
2479   - gen_movl_T1_reg(s, rdhi);
2480   - gen_iwmmxt_movl_wRn_T0_T1(acc);
  2460 + tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
  2461 + iwmmxt_store_reg(cpu_V0, acc);
2481 2462 }
2482 2463 return 0;
2483 2464 }
... ...