gwj / at91sam9263 · Commits

Commit dc5acc23943d5f81bdc09e1512d2364404151144

Authored by Filip Navara
1 parent fb951ff5

Convert disas_neon_ls_insn not to use cpu_T. 

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Inline Side-by-side
Showing 1 changed file with 35 additions and 34 deletions
target-arm/translate.c
  View file @dc5acc2
... ... @@ -3767,6 +3767,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3767 3767 int load;
3768 3768 int shift;
3769 3769 int n;
  3770 + TCGv addr;
3770 3771 TCGv tmp;
3771 3772 TCGv tmp2;
3772 3773  
... ... @@ -3776,6 +3777,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3776 3777 rn = (insn >> 16) & 0xf;
3777 3778 rm = insn & 0xf;
3778 3779 load = (insn & (1 << 21)) != 0;
  3780 + addr = new_tmp();
3779 3781 if ((insn & (1 << 23)) == 0) {
3780 3782 /* Load store all elements. */
3781 3783 op = (insn >> 8) & 0xf;
... ... @@ -3784,32 +3786,30 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3784 3786 return 1;
3785 3787 nregs = neon_ls_element_type[op].nregs;
3786 3788 interleave = neon_ls_element_type[op].interleave;
3787   - gen_movl_T1_reg(s, rn);
  3789 + tcg_gen_mov_i32(addr, cpu_R[rn]);
3788 3790 stride = (1 << size) * interleave;
3789 3791 for (reg = 0; reg < nregs; reg++) {
3790 3792 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
3791   - gen_movl_T1_reg(s, rn);
3792   - gen_op_addl_T1_im((1 << size) * reg);
  3793 + tcg_gen_add_i32(addr, cpu_R[rn], (1 << size) * reg);
3793 3794 } else if (interleave == 2 && nregs == 4 && reg == 2) {
3794   - gen_movl_T1_reg(s, rn);
3795   - gen_op_addl_T1_im(1 << size);
  3795 + tcg_gen_add_i32(addr, cpu_R[rn], 1 << size);
3796 3796 }
3797 3797 for (pass = 0; pass < 2; pass++) {
3798 3798 if (size == 2) {
3799 3799 if (load) {
3800   - tmp = gen_ld32(cpu_T[1], IS_USER(s));
  3800 + tmp = gen_ld32(addr, IS_USER(s));
3801 3801 neon_store_reg(rd, pass, tmp);
3802 3802 } else {
3803 3803 tmp = neon_load_reg(rd, pass);
3804   - gen_st32(tmp, cpu_T[1], IS_USER(s));
  3804 + gen_st32(tmp, addr, IS_USER(s));
3805 3805 }
3806   - gen_op_addl_T1_im(stride);
  3806 + tcg_gen_addi_i32(addr, addr, stride);
3807 3807 } else if (size == 1) {
3808 3808 if (load) {
3809   - tmp = gen_ld16u(cpu_T[1], IS_USER(s));
3810   - gen_op_addl_T1_im(stride);
3811   - tmp2 = gen_ld16u(cpu_T[1], IS_USER(s));
3812   - gen_op_addl_T1_im(stride);
  3809 + tmp = gen_ld16u(addr, IS_USER(s));
  3810 + tcg_gen_addi_i32(addr, addr, stride);
  3811 + tmp2 = gen_ld16u(addr, IS_USER(s));
  3812 + tcg_gen_addi_i32(addr, addr, stride);
3813 3813 gen_bfi(tmp, tmp, tmp2, 16, 0xffff);
3814 3814 dead_tmp(tmp2);
3815 3815 neon_store_reg(rd, pass, tmp);
... ... @@ -3817,17 +3817,17 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3817 3817 tmp = neon_load_reg(rd, pass);
3818 3818 tmp2 = new_tmp();
3819 3819 tcg_gen_shri_i32(tmp2, tmp, 16);
3820   - gen_st16(tmp, cpu_T[1], IS_USER(s));
3821   - gen_op_addl_T1_im(stride);
3822   - gen_st16(tmp2, cpu_T[1], IS_USER(s));
3823   - gen_op_addl_T1_im(stride);
  3820 + gen_st16(tmp, addr, IS_USER(s));
  3821 + tcg_gen_addi_i32(addr, addr, stride);
  3822 + gen_st16(tmp2, addr, IS_USER(s));
  3823 + tcg_gen_addi_i32(addr, addr, stride);
3824 3824 }
3825 3825 } else /* size == 0 */ {
3826 3826 if (load) {
3827 3827 TCGV_UNUSED(tmp2);
3828 3828 for (n = 0; n < 4; n++) {
3829   - tmp = gen_ld8u(cpu_T[1], IS_USER(s));
3830   - gen_op_addl_T1_im(stride);
  3829 + tmp = gen_ld8u(addr, IS_USER(s));
  3830 + tcg_gen_addi_i32(addr, addr, stride);
3831 3831 if (n == 0) {
3832 3832 tmp2 = tmp;
3833 3833 } else {
... ... @@ -3845,8 +3845,8 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3845 3845 } else {
3846 3846 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3847 3847 }
3848   - gen_st8(tmp, cpu_T[1], IS_USER(s));
3849   - gen_op_addl_T1_im(stride);
  3848 + gen_st8(tmp, addr, IS_USER(s));
  3849 + tcg_gen_addi_i32(addr, addr, stride);
3850 3850 }
3851 3851 dead_tmp(tmp2);
3852 3852 }
... ... @@ -3854,7 +3854,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3854 3854 }
3855 3855 rd += neon_ls_element_type[op].spacing;
3856 3856 }
3857   - stride = nregs * 8;
  3857 + stride = nregs * 8;
3858 3858 } else {
3859 3859 size = (insn >> 10) & 3;
3860 3860 if (size == 3) {
... ... @@ -3864,26 +3864,26 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3864 3864 size = (insn >> 6) & 3;
3865 3865 nregs = ((insn >> 8) & 3) + 1;
3866 3866 stride = (insn & (1 << 5)) ? 2 : 1;
3867   - gen_movl_T1_reg(s, rn);
  3867 + tcg_gen_mov_i32(addr, cpu_R[rn]);
3868 3868 for (reg = 0; reg < nregs; reg++) {
3869 3869 switch (size) {
3870 3870 case 0:
3871   - tmp = gen_ld8u(cpu_T[1], IS_USER(s));
  3871 + tmp = gen_ld8u(addr, IS_USER(s));
3872 3872 gen_neon_dup_u8(tmp, 0);
3873 3873 break;
3874 3874 case 1:
3875   - tmp = gen_ld16u(cpu_T[1], IS_USER(s));
  3875 + tmp = gen_ld16u(addr, IS_USER(s));
3876 3876 gen_neon_dup_low16(tmp);
3877 3877 break;
3878 3878 case 2:
3879   - tmp = gen_ld32(cpu_T[0], IS_USER(s));
  3879 + tmp = gen_ld32(addr, IS_USER(s));
3880 3880 break;
3881 3881 case 3:
3882 3882 return 1;
3883 3883 default: /* Avoid compiler warnings. */
3884 3884 abort();
3885 3885 }
3886   - gen_op_addl_T1_im(1 << size);
  3886 + tcg_gen_addi_i32(addr, addr, 1 << size);
3887 3887 tmp2 = new_tmp();
3888 3888 tcg_gen_mov_i32(tmp2, tmp);
3889 3889 neon_store_reg(rd, 0, tmp2);
... ... @@ -3911,18 +3911,18 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3911 3911 abort();
3912 3912 }
3913 3913 nregs = ((insn >> 8) & 3) + 1;
3914   - gen_movl_T1_reg(s, rn);
  3914 + tcg_gen_mov_i32(addr, cpu_R[rn]);
3915 3915 for (reg = 0; reg < nregs; reg++) {
3916 3916 if (load) {
3917 3917 switch (size) {
3918 3918 case 0:
3919   - tmp = gen_ld8u(cpu_T[1], IS_USER(s));
  3919 + tmp = gen_ld8u(addr, IS_USER(s));
3920 3920 break;
3921 3921 case 1:
3922   - tmp = gen_ld16u(cpu_T[1], IS_USER(s));
  3922 + tmp = gen_ld16u(addr, IS_USER(s));
3923 3923 break;
3924 3924 case 2:
3925   - tmp = gen_ld32(cpu_T[1], IS_USER(s));
  3925 + tmp = gen_ld32(addr, IS_USER(s));
3926 3926 break;
3927 3927 default: /* Avoid compiler warnings. */
3928 3928 abort();
... ... @@ -3939,22 +3939,23 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3939 3939 tcg_gen_shri_i32(tmp, tmp, shift);
3940 3940 switch (size) {
3941 3941 case 0:
3942   - gen_st8(tmp, cpu_T[1], IS_USER(s));
  3942 + gen_st8(tmp, addr, IS_USER(s));
3943 3943 break;
3944 3944 case 1:
3945   - gen_st16(tmp, cpu_T[1], IS_USER(s));
  3945 + gen_st16(tmp, addr, IS_USER(s));
3946 3946 break;
3947 3947 case 2:
3948   - gen_st32(tmp, cpu_T[1], IS_USER(s));
  3948 + gen_st32(tmp, addr, IS_USER(s));
3949 3949 break;
3950 3950 }
3951 3951 }
3952 3952 rd += stride;
3953   - gen_op_addl_T1_im(1 << size);
  3953 + tcg_gen_addi_i32(addr, addr, 1 << size);
3954 3954 }
3955 3955 stride = nregs * (1 << size);
3956 3956 }
3957 3957 }
  3958 + dead_tmp(addr);
3958 3959 if (rm != 15) {
3959 3960 TCGv base;
3960 3961  
... ...