gwj / at91sam9263 · Commits

Commit d700004360b8e0d89c3d99962a11fc9dba3be22d

Authored by Filip Navara
1 parent bd8938c2

AT91 Power Management Controller 

The isolated behavior of PMC is emulated completely, but the effects on other
parts of the system are not. Since QEMU lacks any API for proper modeling of
the system and peripheral clocks, the actual enabling and disabling of clocks
has no effect on the emulated system.

The master clock frequency is exposed using a global variable for use by other
system components, such as timers.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Showing 3 changed files with 331 additions and 1 deletions
Makefile.target
  View file @d700004
... ... @@ -431,7 +431,7 @@ obj-arm-y += framebuffer.o
431 431 obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
432 432 obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
433 433 obj-arm-y += syborg_virtio.o
434   -obj-arm-y += at91_aic.o
  434 +obj-arm-y += at91_aic.o at91_pmc.o
435 435 obj-arm-y += gpio_rotary.o gpio_keypad.o
436 436  
437 437 ifeq ($(TARGET_BASE_ARCH), arm)
... ...
hw/at91.h 0 → 100644
  View file @d700004
  1 +/*
  2 + * AT91 Miscellaneous Definitions
  3 + *
  4 + * Copyright (c) 2009 Filip Navara
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +
  25 +#ifndef AT91_H
  26 +#define AT91_H 1
  27 +
  28 +/* Frequency of the master clock as programmed by the Power Management
  29 + Controller. */
  30 +extern int at91_master_clock_frequency;
  31 +
  32 +#endif /* !AT91_H */
... ...
hw/at91_pmc.c 0 → 100644
  View file @d700004
  1 +/*
  2 + * AT91 Power Management Controller
  3 + *
  4 + * Copyright (c) 2009 Filip Navara
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +
  25 +#include "sysbus.h"
  26 +#include "qemu-timer.h"
  27 +#include "at91.h"
  28 +
  29 +#define PMC_SIZE 0x70
  30 +
  31 +#define PMC_SCER 0x00 /* System Clock Enable Register */
  32 +#define PMC_SCDR 0x04 /* System Clock Disable Register */
  33 +#define PMC_SCSR 0x08 /* System Clock Status Register */
  34 +#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */
  35 +#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
  36 +#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */
  37 +#define PMC_MOR 0x20 /* Main Oscillator Register */
  38 +#define PMC_MCFR 0x24 /* Main Clock Frequency Register */
  39 +#define PMC_PLLA 0x28 /* PLL A Register */
  40 +#define PMC_PLLB 0x2c /* PLL B Register */
  41 +#define PMC_MCKR 0x30 /* Master Clock Register */
  42 +#define PMC_PCKR 0x40 /* Programmable Clock Register */
  43 +#define PMC_IER 0x60 /* Interrupt Enable Register */
  44 +#define PMC_IDR 0x64 /* Interrupt Disable Register */
  45 +#define PMC_IMR 0x6c /* Interrupt Mask Register */
  46 +#define PMC_SR 0x68 /* Status Register */
  47 +
  48 +#define SR_MOSCS 0x01
  49 +#define SR_LOCKA 0x02
  50 +#define SR_LOCKB 0x04
  51 +#define SR_MCKRDY 0x08
  52 +#define SR_PCK0RDY 0x100
  53 +#define SR_PCK1RDY 0x200
  54 +#define SR_PCK2RDY 0x400
  55 +#define SR_PCK3RDY 0x800
  56 +
  57 +#define SO_FREQ 32768
  58 +#define MO_FREQ 9216000
  59 +
  60 +int at91_master_clock_frequency = SO_FREQ;
  61 +
  62 +typedef struct PMCState {
  63 + SysBusDevice busdev;
  64 + qemu_irq parent_irq;
  65 + uint32_t scsr;
  66 + uint32_t pcsr;
  67 + uint32_t mor;
  68 + uint32_t plla;
  69 + uint32_t pllb;
  70 + uint32_t mckr;
  71 + uint32_t pckr[4];
  72 + uint32_t sr;
  73 + uint32_t imr;
  74 + uint32_t mck_freq;
  75 +} PMCState;
  76 +
  77 +static void at91_pmc_update_irq(PMCState *s)
  78 +{
  79 + qemu_set_irq(s->parent_irq, !!(s->sr & s->imr));
  80 +}
  81 +
  82 +static void at91_update_master_clock(PMCState *s)
  83 +{
  84 + int mck_freq = MO_FREQ;
  85 +
  86 + /* Clock selection */
  87 + switch (s->mckr & 3) {
  88 + case 0: /* Slow */
  89 + mck_freq = SO_FREQ;
  90 + break;
  91 + case 1: /* Main */
  92 + if (!(s->sr & SR_MOSCS))
  93 + mck_freq = 0;
  94 + break;
  95 + case 2: /* PLL A */
  96 + if ((s->plla & 0xff) != 0 &&
  97 + (s->plla & 0x3ff80) != 0) {
  98 + mck_freq /= s->plla & 0xff;
  99 + mck_freq *= ((s->plla >> 16) & 0x7ff) + 1;
  100 + } else {
  101 + mck_freq = 0;
  102 + }
  103 + break;
  104 + case 3: /* PLL B */
  105 + if ((s->pllb & 0xff) != 0 &&
  106 + (s->pllb & 0x3ff80) != 0) {
  107 + mck_freq /= s->pllb & 0xff;
  108 + mck_freq *= ((s->pllb >> 16) & 0x7ff) + 1;
  109 + } else {
  110 + mck_freq = 0;
  111 + }
  112 + break;
  113 + }
  114 +
  115 + if (mck_freq != 0) {
  116 + mck_freq /= 1 << ((s->mckr >> 2) & 7);
  117 + mck_freq /= 1 << ((s->mckr >> 8) & 3);
  118 + s->mck_freq = mck_freq;
  119 + at91_master_clock_frequency = mck_freq;
  120 + s->sr |= SR_MCKRDY;
  121 + } else {
  122 + s->sr &= ~SR_MCKRDY;
  123 + }
  124 +}
  125 +
  126 +static uint32_t at91_pmc_mem_read(void *opaque, target_phys_addr_t offset)
  127 +{
  128 + PMCState *s = opaque;
  129 +
  130 + switch (offset) {
  131 + case PMC_SCSR:
  132 + return s->scsr;
  133 + case PMC_PCSR:
  134 + return s->pcsr;
  135 + case PMC_MOR:
  136 + return s->mor;
  137 + case PMC_MCFR:
  138 + if (s->mor & 1)
  139 + return (1 << 16) | (MO_FREQ / SO_FREQ / 16);
  140 + return 0;
  141 + case PMC_PCKR ... PMC_PCKR + 15:
  142 + return s->pckr[(offset - PMC_PCKR) >> 2];
  143 + case PMC_SR:
  144 + return s->sr;
  145 + case PMC_IMR:
  146 + return s->imr;
  147 + default:
  148 + return 0;
  149 + }
  150 +}
  151 +
  152 +static void at91_pmc_mem_write(void *opaque, target_phys_addr_t offset,
  153 + uint32_t value)
  154 +{
  155 + PMCState *s = opaque;
  156 +
  157 + switch (offset) {
  158 + case PMC_SCER:
  159 + s->scsr |= value & 0xf80;
  160 + break;
  161 + case PMC_SCDR:
  162 + s->scsr &= ~(value & 0xf80);
  163 + break;
  164 + case PMC_PCER:
  165 + s->pcsr |= value & ~3;
  166 + break;
  167 + case PMC_PCDR:
  168 + s->pcsr &= ~(value & ~3);
  169 + break;
  170 + case PMC_MOR:
  171 + /* Main Oscillator bypassing is not supported, so first two
  172 + bits are ignored. Bits 8-15 specify the OSCOUNT, which is
  173 + also currently ignored. */
  174 + s->mor = value;
  175 + s->sr |= SR_MOSCS;
  176 + break;
  177 + case PMC_PLLA:
  178 + s->plla = value;
  179 + /* OUTA, PLLACOUNT ignored for now */
  180 + s->sr |= SR_LOCKA;
  181 + break;
  182 + case PMC_PLLB:
  183 + s->pllb = value;
  184 + /* OUTB, PLLBCOUNT ignored for now */
  185 + s->sr |= SR_LOCKB;
  186 + break;
  187 + case PMC_MCKR:
  188 + s->mckr = value;
  189 + break;
  190 + case PMC_PCKR ... PMC_PCKR + 15:
  191 + s->pckr[(offset - PMC_PCKR) >> 2] = value;
  192 + break;
  193 + case PMC_IER:
  194 + s->imr |= value;
  195 + break;
  196 + case PMC_IDR:
  197 + s->imr &= ~value;
  198 + break;
  199 + default:
  200 + return;
  201 + }
  202 +
  203 + at91_update_master_clock(s);
  204 + at91_pmc_update_irq(s);
  205 +}
  206 +
  207 +static CPUReadMemoryFunc *at91_pmc_readfn[] = {
  208 + at91_pmc_mem_read,
  209 + at91_pmc_mem_read,
  210 + at91_pmc_mem_read,
  211 +};
  212 +
  213 +static CPUWriteMemoryFunc *at91_pmc_writefn[] = {
  214 + at91_pmc_mem_write,
  215 + at91_pmc_mem_write,
  216 + at91_pmc_mem_write,
  217 +};
  218 +
  219 +static void at91_pmc_save(QEMUFile *f, void *opaque)
  220 +{
  221 + PMCState *s = opaque;
  222 + int i;
  223 +
  224 + qemu_put_be32(f, s->scsr);
  225 + qemu_put_be32(f, s->pcsr);
  226 + qemu_put_be32(f, s->mor);
  227 + qemu_put_be32(f, s->plla);
  228 + qemu_put_be32(f, s->pllb);
  229 + qemu_put_be32(f, s->mckr);
  230 + for (i = 0; i < 4; i++) {
  231 + qemu_put_be32(f, s->pckr[i]);
  232 + }
  233 + qemu_put_be32(f, s->sr);
  234 + qemu_put_be32(f, s->imr);
  235 +}
  236 +
  237 +static int at91_pmc_load(QEMUFile *f, void *opaque, int version_id)
  238 +{
  239 + PMCState *s = opaque;
  240 + int i;
  241 +
  242 + if (version_id != 1)
  243 + return -EINVAL;
  244 +
  245 + s->scsr = qemu_get_be32(f);
  246 + s->pcsr = qemu_get_be32(f);
  247 + s->mor = qemu_get_be32(f);
  248 + s->plla = qemu_get_be32(f);
  249 + s->pllb = qemu_get_be32(f);
  250 + s->mckr = qemu_get_be32(f);
  251 + for (i = 0; i < 4; i++) {
  252 + s->pckr[i] = qemu_get_be32(f);
  253 + }
  254 + s->sr = qemu_get_be32(f);
  255 + s->imr = qemu_get_be32(f);
  256 +
  257 + at91_update_master_clock(s);
  258 +
  259 + return 0;
  260 +}
  261 +
  262 +static void at91_pmc_reset(void *opaque)
  263 +{
  264 + PMCState *s = opaque;
  265 +
  266 + s->scsr = 1;
  267 + s->pcsr = 0;
  268 + s->mor = 0;
  269 + s->plla = s->pllb = 0x3f00;
  270 + s->mckr = 0;
  271 + s->pckr[0] = s->pckr[1] = s->pckr[2] = s->pckr[3] = 0;
  272 + s->sr = 8;
  273 + s->imr = 0;
  274 + s->mck_freq = SO_FREQ;
  275 +}
  276 +
  277 +static void at91_pmc_init(SysBusDevice *dev)
  278 +{
  279 + PMCState *s = FROM_SYSBUS(typeof (*s), dev);
  280 + int pmc_regs;
  281 +
  282 + sysbus_init_irq(dev, &s->parent_irq);
  283 +
  284 + pmc_regs = cpu_register_io_memory(at91_pmc_readfn, at91_pmc_writefn, s);
  285 + sysbus_init_mmio(dev, PMC_SIZE, pmc_regs);
  286 +
  287 + at91_pmc_reset(s);
  288 + qemu_register_reset(at91_pmc_reset, s);
  289 +
  290 + register_savevm("at91_pmc", -1, 1, at91_pmc_save, at91_pmc_load, s);
  291 +}
  292 +
  293 +static void at91_pmc_register(void)
  294 +{
  295 + sysbus_register_dev("at91,pmc", sizeof(PMCState), at91_pmc_init);
  296 +}
  297 +
  298 +device_init(at91_pmc_register)
... ...