gwj / at91sam9263 · Commits

Commit 10ef1a662fc233561ab9171ac3abad684722043e

Authored by Filip Navara
1 parent 42fe8e59

AT91 Timer/Counter 

Only the timer part of the the Timer/Counter block is implemented since there
is no interface for connection of external clocks in QEMU, so there is nothing
to measure. The minimal implementation is done using host timers and an
internal counter.

This implementation is sufficient for running the Atmel examples,
but leaves a lot to be desired.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
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Showing 2 changed files with 311 additions and 1 deletions
Makefile.target
  View file @10ef1a6
... ... @@ -432,7 +432,7 @@ obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
432 432 obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
433 433 obj-arm-y += syborg_virtio.o
434 434 obj-arm-y += at91_aic.o at91_dbgu.o at91_pio.o at91_pit.o at91_pmc.o at91_rtt.o
435   -obj-arm-y += at91_rstc.o at91_intor.o
  435 +obj-arm-y += at91_rstc.o at91_intor.o at91_tc.o
436 436 obj-arm-y += gpio_rotary.o gpio_keypad.o
437 437  
438 438 ifeq ($(TARGET_BASE_ARCH), arm)
... ...
hw/at91_tc.c 0 → 100644
  View file @10ef1a6
  1 +/*
  2 + * AT91 Timer Counter
  3 + *
  4 + * Copyright (c) 2009 Filip Navara
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +
  25 +#include "sysbus.h"
  26 +#include "qemu-timer.h"
  27 +#include "at91.h"
  28 +
  29 +#define TC_SIZE 0x4000
  30 +
  31 +#define TC_CCR 0x00 /* Channel Control Register */
  32 +#define TC_CMR 0x04 /* Channel Mode Register */
  33 +#define TC_CV 0x10 /* Counter Value Register */
  34 +#define TC_RA 0x14 /* Register A */
  35 +#define TC_RB 0x18 /* Register B */
  36 +#define TC_RC 0x1c /* Register C */
  37 +#define TC_SR 0x20 /* Status Register */
  38 +#define TC_IER 0x24 /* Interrupt Enable Register */
  39 +#define TC_IDR 0x28 /* Interrupt Disable Register */
  40 +#define TC_IMR 0x2c /* Interrupt Mask Register */
  41 +#define TC_BCR 0xc0 /* Block Control Register */
  42 +#define TC_BMR 0xc4 /* Block Mode Register */
  43 +
  44 +#define MR_CLKI 0x08 /* Clock Invert */
  45 +#define MR_CPCSTOP 0x40 /* Counter Clock Stopped with RC Compare */
  46 +#define MR_CPCDIS 0x80 /* Counter Clock Disable with RC Compare */
  47 +#define MR_RCTRIG 0x4000
  48 +#define MR_WAVE 0x8000
  49 +
  50 +#define SR_CPAS 0x04
  51 +#define SR_CPBS 0x08
  52 +#define SR_CPCS 0x10
  53 +
  54 +typedef struct TCChannelState {
  55 + qemu_irq irq;
  56 + ptimer_state *timer;
  57 + uint32_t mr;
  58 + uint16_t cv;
  59 + uint16_t ra;
  60 + uint16_t rb;
  61 + uint16_t rc;
  62 + uint32_t sr;
  63 + uint32_t imr;
  64 +} TCChannelState;
  65 +
  66 +typedef struct TCState {
  67 + SysBusDevice busdev;
  68 + TCChannelState channels[3];
  69 +} TCState;
  70 +
  71 +static void at91_tc_tick(void *opaque)
  72 +{
  73 + TCChannelState *s = opaque;
  74 +
  75 + s->cv++;
  76 + /* TODO: Overflow check */
  77 + if (s->cv == s->ra) {
  78 + s->sr |= SR_CPAS;
  79 + }
  80 + if (s->cv == s->rb) {
  81 + s->sr |= SR_CPBS;
  82 + }
  83 + if (s->cv == s->rc) {
  84 + s->sr |= SR_CPCS;
  85 + if (s->mr & MR_RCTRIG) {
  86 + s->cv = 0;
  87 + }
  88 + }
  89 + if (s->sr & s->imr) {
  90 + qemu_set_irq(s->irq, 1);
  91 + }
  92 +}
  93 +
  94 +static uint32_t at91_tc_channel_read(TCChannelState *s,
  95 + target_phys_addr_t offset)
  96 +{
  97 + uint32_t sr;
  98 +
  99 + switch (offset) {
  100 + case TC_CMR:
  101 + return s->mr;
  102 + case TC_CV:
  103 + return s->cv;
  104 + case TC_RA:
  105 + return s->ra;
  106 + case TC_RB:
  107 + return s->rb;
  108 + case TC_RC:
  109 + return s->rb;
  110 + case TC_SR:
  111 + sr = s->sr;
  112 + s->sr = 0;
  113 + qemu_set_irq(s->irq, 0);
  114 + return sr;
  115 + case TC_IMR:
  116 + return s->imr;
  117 + default:
  118 + return 0;
  119 + }
  120 +}
  121 +
  122 +static void at91_tc_channel_write(TCChannelState *s,
  123 + target_phys_addr_t offset, uint32_t value)
  124 +{
  125 + int freq;
  126 +
  127 + switch (offset) {
  128 + case TC_CCR:
  129 + if ((value & 3) == 1) {
  130 + if (s->mr & MR_WAVE) {
  131 + s->cv = 0;
  132 + ptimer_run(s->timer, 0);
  133 + }
  134 + /* TODO: Counter mode */
  135 + } else if (value & 2) {
  136 + ptimer_stop(s->timer);
  137 + }
  138 + break;
  139 + case TC_CMR:
  140 + if (value & MR_WAVE) {
  141 + switch (value & 7) {
  142 + case 0: freq = at91_master_clock_frequency / 2; break;
  143 + case 1: freq = at91_master_clock_frequency / 8; break;
  144 + case 2: freq = at91_master_clock_frequency / 32; break;
  145 + case 3: freq = at91_master_clock_frequency / 128; break;
  146 + case 4: freq = at91_master_clock_frequency / 1024; break;
  147 + default: /* TODO: External clocks */
  148 + freq = at91_master_clock_frequency / 16;
  149 + break;
  150 + }
  151 + ptimer_set_freq(s->timer, freq);
  152 + }
  153 + /* TODO: Counter mode */
  154 + s->mr = value;
  155 + break;
  156 + case TC_RA:
  157 + s->ra = value;
  158 + break;
  159 + case TC_RB:
  160 + s->rb = value;
  161 + break;
  162 + case TC_RC:
  163 + s->rc = value;
  164 + break;
  165 + case TC_IER:
  166 + s->imr |= value;
  167 + break;
  168 + case TC_IDR:
  169 + s->imr &= ~value;
  170 + break;
  171 + }
  172 +}
  173 +
  174 +static uint32_t at91_tc_mem_read(void *opaque, target_phys_addr_t offset)
  175 +{
  176 + TCState *s = opaque;
  177 +
  178 + switch (offset) {
  179 + case TC_BMR:
  180 + return 0; /* TODO */
  181 + case 0 ... 0x3f:
  182 + return at91_tc_channel_read(&s->channels[0], offset);
  183 + case 0x40 ... 0x7f:
  184 + return at91_tc_channel_read(&s->channels[1], offset - 0x40);
  185 + case 0x80 ... 0xbf:
  186 + return at91_tc_channel_read(&s->channels[2], offset - 0x80);
  187 + default:
  188 + return 0;
  189 + }
  190 +}
  191 +
  192 +static void at91_tc_mem_write(void *opaque, target_phys_addr_t offset,
  193 + uint32_t value)
  194 +{
  195 + TCState *s = opaque;
  196 +
  197 + switch (offset) {
  198 + case TC_BCR:
  199 + return; /* TODO */
  200 + case TC_BMR:
  201 + return; /* TODO */
  202 + case 0 ... 0x3f:
  203 + at91_tc_channel_write(&s->channels[0], offset, value);
  204 + break;
  205 + case 0x40 ... 0x7f:
  206 + at91_tc_channel_write(&s->channels[1], offset - 0x40, value);
  207 + break;
  208 + case 0x80 ... 0xbf:
  209 + at91_tc_channel_write(&s->channels[2], offset - 0x80, value);
  210 + break;
  211 + }
  212 +}
  213 +
  214 +static CPUReadMemoryFunc *at91_tc_readfn[] = {
  215 + at91_tc_mem_read,
  216 + at91_tc_mem_read,
  217 + at91_tc_mem_read,
  218 +};
  219 +
  220 +static CPUWriteMemoryFunc *at91_tc_writefn[] = {
  221 + at91_tc_mem_write,
  222 + at91_tc_mem_write,
  223 + at91_tc_mem_write,
  224 +};
  225 +
  226 +static void at91_tc_save(QEMUFile *f, void *opaque)
  227 +{
  228 + TCState *s = opaque;
  229 + int channel;
  230 +
  231 + for (channel = 0; channel < 3; channel++) {
  232 + qemu_put_ptimer(f, s->channels[channel].timer);
  233 + qemu_put_be32(f, s->channels[channel].mr);
  234 + qemu_put_be16(f, s->channels[channel].cv);
  235 + qemu_put_be16(f, s->channels[channel].ra);
  236 + qemu_put_be16(f, s->channels[channel].rb);
  237 + qemu_put_be16(f, s->channels[channel].rc);
  238 + qemu_put_be32(f, s->channels[channel].sr);
  239 + qemu_put_be32(f, s->channels[channel].imr);
  240 + }
  241 +}
  242 +
  243 +static int at91_tc_load(QEMUFile *f, void *opaque, int version_id)
  244 +{
  245 + TCState *s = opaque;
  246 + int channel;
  247 +
  248 + if (version_id != 1)
  249 + return -EINVAL;
  250 +
  251 + for (channel = 0; channel < 3; channel++) {
  252 + qemu_get_ptimer(f, s->channels[channel].timer);
  253 + s->channels[channel].mr = qemu_get_be32(f);
  254 + s->channels[channel].cv = qemu_get_be16(f);
  255 + s->channels[channel].ra = qemu_get_be16(f);
  256 + s->channels[channel].rb = qemu_get_be16(f);
  257 + s->channels[channel].rc = qemu_get_be16(f);
  258 + s->channels[channel].sr = qemu_get_be32(f);
  259 + s->channels[channel].imr = qemu_get_be32(f);
  260 + }
  261 +
  262 + return 0;
  263 +}
  264 +
  265 +static void at91_tc_reset(void *opaque)
  266 +{
  267 + TCState *s = opaque;
  268 + int channel;
  269 +
  270 + for (channel = 0; channel < 3; channel++) {
  271 + ptimer_stop(s->channels[channel].timer);
  272 + s->channels[channel].mr = 0;
  273 + s->channels[channel].cv = 0;
  274 + s->channels[channel].ra = 0;
  275 + s->channels[channel].rb = 0;
  276 + s->channels[channel].rc = 0;
  277 + s->channels[channel].sr = 0;
  278 + s->channels[channel].imr = 0;
  279 + }
  280 +}
  281 +
  282 +static void at91_tc_init(SysBusDevice *dev)
  283 +{
  284 + TCState *s = FROM_SYSBUS(typeof (*s), dev);
  285 + QEMUBH *bh;
  286 + int tc_regs;
  287 + int channel;
  288 +
  289 + for (channel = 0; channel < 3; channel++) {
  290 + bh = qemu_bh_new(at91_tc_tick, &s->channels[channel]);
  291 + s->channels[channel].timer = ptimer_init(bh);
  292 + ptimer_set_limit(s->channels[channel].timer, 1, 1);
  293 + sysbus_init_irq(dev, &s->channels[channel].irq);
  294 + }
  295 +
  296 + tc_regs = cpu_register_io_memory(at91_tc_readfn,
  297 + at91_tc_writefn, s);
  298 + sysbus_init_mmio(dev, TC_SIZE, tc_regs);
  299 +
  300 + qemu_register_reset(at91_tc_reset, s);
  301 +
  302 + register_savevm("at91_tc", -1, 1, at91_tc_save, at91_tc_load, s);
  303 +}
  304 +
  305 +static void at91_tc_register(void)
  306 +{
  307 + sysbus_register_dev("at91,tc", sizeof(TCState), at91_tc_init);
  308 +}
  309 +
  310 +device_init(at91_tc_register)
... ...