Commit 44b66891d5ab8a324b7a34d2e941351ca7024851

Authored by Filip Navara
1 parent 39985818

AT91 Reset Controller

This patch introduces emulation of the AT91 reset controller. The behavior
and external interface to the reset controller is not emulated though and
only the features necessary to start the system are implemented.

Internal registers are maintained and partially emulated. The NRST status
bit is always asserted, even if a command to de-assert it is written
to the control register.

This emulation is sufficient to support running FreeRTOS and a sample code
from Atmel.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Makefile.target
... ... @@ -432,6 +432,7 @@ obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
432 432 obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
433 433 obj-arm-y += syborg_virtio.o
434 434 obj-arm-y += at91_aic.o at91_dbgu.o at91_pio.o at91_pit.o at91_pmc.o at91_rtt.o
  435 +obj-arm-y += at91_rstc.o
435 436 obj-arm-y += gpio_rotary.o gpio_keypad.o
436 437  
437 438 ifeq ($(TARGET_BASE_ARCH), arm)
... ...
hw/at91_rstc.c 0 → 100644
  1 +/*
  2 + * AT91 Reset Controller
  3 + *
  4 + * Copyright (c) 2009 Filip Navara
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +
  25 +#include "sysbus.h"
  26 +
  27 +/* #define DEBUG_RSTC */
  28 +
  29 +#define RSTC_SIZE 0x10
  30 +
  31 +#define RSTC_CR 0x00 /* Control Register */
  32 +#define RSTC_SR 0x04 /* Status Register */
  33 +#define RSTC_MR 0x08 /* Mode Register */
  34 +
  35 +#define WRITE_KEY 0xa5
  36 +
  37 +#define CR_PROCRST 0x01 /* Processor Reset */
  38 +#define CR_PERRST 0x04 /* Peripheral Reset */
  39 +#define CR_EXTRST 0x08 /* External Reset */
  40 +
  41 +#define SR_URSTS 0x01 /* User Reset Status */
  42 +#define SR_BODSTS 0x02 /* Brownout Detection Status */
  43 +#define SR_NRSTL 0x10000 /* NRST Level */
  44 +
  45 +typedef struct RSTCState {
  46 + SysBusDevice busdev;
  47 + uint32_t sr;
  48 + uint32_t mr;
  49 +} RSTCState;
  50 +
  51 +static uint32_t at91_rstc_mem_read(void *opaque, target_phys_addr_t offset)
  52 +{
  53 + RSTCState *s = opaque;
  54 +
  55 + offset &= RSTC_SIZE - 1;
  56 + switch (offset) {
  57 + case RSTC_SR:
  58 + return s->sr;
  59 + case RSTC_MR:
  60 + return s->mr;
  61 + default:
  62 + return 0;
  63 + }
  64 +}
  65 +
  66 +static void at91_rstc_mem_write(void *opaque, target_phys_addr_t offset,
  67 + uint32_t value)
  68 +{
  69 + RSTCState *s = opaque;
  70 +
  71 + if ((value >> 24) != WRITE_KEY)
  72 + return;
  73 +
  74 + offset &= RSTC_SIZE - 1;
  75 + switch (offset) {
  76 + case RSTC_CR:
  77 + /* TODO */
  78 + break;
  79 + case RSTC_MR:
  80 + s->mr = value;
  81 + break;
  82 + }
  83 +}
  84 +
  85 +#ifdef DEBUG_RSTC
  86 +static uint32_t at91_rstc_mem_read_dbg(void *opaque, target_phys_addr_t offset)
  87 +{
  88 + uint32_t value = at91_rstc_mem_read(opaque, offset);
  89 + printf("%s offset=%x val=%x\n", __func__, offset, value);
  90 + return value;
  91 +}
  92 +
  93 +static void at91_rstc_mem_write_dbg(void *opaque, target_phys_addr_t offset,
  94 + uint32_t value)
  95 +{
  96 + printf("%s offset=%x val=%x\n", __func__, offset, value);
  97 + at91_rstc_mem_write(opaque, offset, value);
  98 +}
  99 +
  100 +#define at91_rstc_mem_read at91_rstc_mem_read_dbg
  101 +#define at91_rstc_mem_write at91_rstc_mem_write_dbg
  102 +#endif
  103 +
  104 +static CPUReadMemoryFunc *at91_rstc_readfn[] = {
  105 + at91_rstc_mem_read,
  106 + at91_rstc_mem_read,
  107 + at91_rstc_mem_read,
  108 +};
  109 +
  110 +static CPUWriteMemoryFunc *at91_rstc_writefn[] = {
  111 + at91_rstc_mem_write,
  112 + at91_rstc_mem_write,
  113 + at91_rstc_mem_write,
  114 +};
  115 +
  116 +static void at91_rstc_save(QEMUFile *f, void *opaque)
  117 +{
  118 + RSTCState *s = opaque;
  119 +
  120 + qemu_put_be32(f, s->sr);
  121 + qemu_put_be32(f, s->mr);
  122 +}
  123 +
  124 +static int at91_rstc_load(QEMUFile *f, void *opaque, int version_id)
  125 +{
  126 + RSTCState *s = opaque;
  127 +
  128 + if (version_id != 1)
  129 + return -EINVAL;
  130 +
  131 + s->sr = qemu_get_be32(f);
  132 + s->mr = qemu_get_be32(f);
  133 +
  134 + return 0;
  135 +}
  136 +
  137 +static void at91_rstc_reset(void *opaque)
  138 +{
  139 + RSTCState *s = opaque;
  140 +
  141 + s->sr = SR_NRSTL;
  142 + s->mr = 0;
  143 +}
  144 +
  145 +static void at91_rstc_init(SysBusDevice *dev)
  146 +{
  147 + RSTCState *s = FROM_SYSBUS(typeof (*s), dev);
  148 + int rstc_regs;
  149 +
  150 + rstc_regs = cpu_register_io_memory(at91_rstc_readfn, at91_rstc_writefn, s);
  151 + sysbus_init_mmio(dev, RSTC_SIZE, rstc_regs);
  152 +
  153 + at91_rstc_reset(s);
  154 + qemu_register_reset(at91_rstc_reset, s);
  155 +
  156 + register_savevm("at91_rstc", -1, 1, at91_rstc_save, at91_rstc_load, s);
  157 +}
  158 +
  159 +static void at91_rstc_register(void)
  160 +{
  161 + sysbus_register_dev("at91,rstc", sizeof(RSTCState), at91_rstc_init);
  162 +}
  163 +
  164 +device_init(at91_rstc_register)
... ...