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/*
* MIPS emulation for qemu : CPU initialisation routines .
*
* Copyright ( c ) 2004 - 2005 Jocelyn Mayer
* Copyright ( c ) 2007 Herve Poussineau
*
* This library is free software ; you can redistribute it and / or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation ; either
* version 2 of the License , or ( at your option ) any later version .
*
* This library is distributed in the hope that it will be useful ,
* but WITHOUT ANY WARRANTY ; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE . See the GNU
* Lesser General Public License for more details .
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library ; if not , write to the Free Software
19
* Foundation , Inc ., 51 Franklin Street , Fifth Floor , Boston MA 02110 - 1301 USA
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*/
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/* CPU / CPU family specific config register values. */
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/* Have config1, uncached coherency */
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# define MIPS_CONFIG0 \
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(( 1 << CP0C0_M ) | ( 0x2 << CP0C0_K0 ))
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/* Have config2 , no coprocessor2 attached , no MDMX support attached ,
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no performance counters , watch registers present ,
no code compression , EJTAG present , no FPU */
# define MIPS_CONFIG1 \
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(( 1 << CP0C1_M ) | \
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( 0 << CP0C1_C2 ) | ( 0 << CP0C1_MD ) | ( 0 << CP0C1_PC ) | \
( 1 << CP0C1_WR ) | ( 0 << CP0C1_CA ) | ( 1 << CP0C1_EP ) | \
( 0 << CP0C1_FP ))
/* Have config3, no tertiary/secondary caches implemented */
# define MIPS_CONFIG2 \
(( 1 << CP0C2_M ))
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/* No config4 , no DSP ASE , no large physaddr ( PABITS ),
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no external interrupt controller , no vectored interupts ,
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no 1 kb pages , no SmartMIPS ASE , no trace logic */
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# define MIPS_CONFIG3 \
(( 0 << CP0C3_M ) | ( 0 << CP0C3_DSPP ) | ( 0 << CP0C3_LPA ) | \
( 0 << CP0C3_VEIC ) | ( 0 << CP0C3_VInt ) | ( 0 << CP0C3_SP ) | \
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( 0 << CP0C3_SM ) | ( 0 << CP0C3_TL ))
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/* Define a implementation number of 1 .
Define a major version 1 , minor version 0 . */
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# define MIPS_FCR0 (( 0 << FCR0_S ) | ( 0x1 << FCR0_PRID ) | ( 0x10 << FCR0_REV ))
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/* MMU types , the first four entries have the same layout as the
CP0C0_MT field . */
enum mips_mmu_types {
MMU_TYPE_NONE ,
MMU_TYPE_R4000 ,
MMU_TYPE_RESERVED ,
MMU_TYPE_FMT ,
MMU_TYPE_R3000 ,
MMU_TYPE_R6000 ,
MMU_TYPE_R8000
};
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struct mips_def_t {
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const char * name ;
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int32_t CP0_PRid ;
int32_t CP0_Config0 ;
int32_t CP0_Config1 ;
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int32_t CP0_Config2 ;
int32_t CP0_Config3 ;
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int32_t CP0_Config6 ;
int32_t CP0_Config7 ;
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int32_t SYNCI_Step ;
int32_t CCRes ;
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int32_t CP0_Status_rw_bitmask ;
int32_t CP0_TCStatus_rw_bitmask ;
int32_t CP0_SRSCtl ;
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int32_t CP1_fcr0 ;
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int32_t SEGBITS ;
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int32_t PABITS ;
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int32_t CP0_SRSConf0_rw_bitmask ;
int32_t CP0_SRSConf0 ;
int32_t CP0_SRSConf1_rw_bitmask ;
int32_t CP0_SRSConf1 ;
int32_t CP0_SRSConf2_rw_bitmask ;
int32_t CP0_SRSConf2 ;
int32_t CP0_SRSConf3_rw_bitmask ;
int32_t CP0_SRSConf3 ;
int32_t CP0_SRSConf4_rw_bitmask ;
int32_t CP0_SRSConf4 ;
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int insn_flags ;
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enum mips_mmu_types mmu_type ;
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};
/*****************************************************************************/
/* MIPS CPU definitions */
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static const mips_def_t mips_defs [] =
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{
{
. name = "4Kc" ,
. CP0_PRid = 0x00018000 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( MMU_TYPE_R4000 << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 15 << CP0C1_MMU ) |
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( 0 << CP0C1_IS ) | ( 3 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 0 << CP0C1_DS ) | ( 3 << CP0C1_DL ) | ( 1 << CP0C1_DA ),
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. CP0_Config2 = MIPS_CONFIG2 ,
. CP0_Config3 = MIPS_CONFIG3 ,
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. SYNCI_Step = 32 ,
. CCRes = 2 ,
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. CP0_Status_rw_bitmask = 0x1278FF17 ,
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. SEGBITS = 32 ,
. PABITS = 32 ,
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. insn_flags = CPU_MIPS32 | ASE_MIPS16 ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
{
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. name = "4Km" ,
. CP0_PRid = 0x00018300 ,
/* Config1 implemented , fixed mapping MMU ,
no virtual icache , uncached coherency . */
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. CP0_Config0 = MIPS_CONFIG0 | ( MMU_TYPE_FMT << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 |
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( 0 << CP0C1_IS ) | ( 3 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 0 << CP0C1_DS ) | ( 3 << CP0C1_DL ) | ( 1 << CP0C1_DA ),
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. CP0_Config2 = MIPS_CONFIG2 ,
. CP0_Config3 = MIPS_CONFIG3 ,
. SYNCI_Step = 32 ,
. CCRes = 2 ,
. CP0_Status_rw_bitmask = 0x1258FF17 ,
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. SEGBITS = 32 ,
. PABITS = 32 ,
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. insn_flags = CPU_MIPS32 | ASE_MIPS16 ,
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. mmu_type = MMU_TYPE_FMT ,
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},
{
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. name = "4KEcR1" ,
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. CP0_PRid = 0x00018400 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( MMU_TYPE_R4000 << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 15 << CP0C1_MMU ) |
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( 0 << CP0C1_IS ) | ( 3 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 0 << CP0C1_DS ) | ( 3 << CP0C1_DL ) | ( 1 << CP0C1_DA ),
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. CP0_Config2 = MIPS_CONFIG2 ,
. CP0_Config3 = MIPS_CONFIG3 ,
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. SYNCI_Step = 32 ,
. CCRes = 2 ,
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. CP0_Status_rw_bitmask = 0x1278FF17 ,
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. SEGBITS = 32 ,
. PABITS = 32 ,
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. insn_flags = CPU_MIPS32 | ASE_MIPS16 ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
{
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. name = "4KEmR1" ,
. CP0_PRid = 0x00018500 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( MMU_TYPE_FMT << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 |
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( 0 << CP0C1_IS ) | ( 3 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 0 << CP0C1_DS ) | ( 3 << CP0C1_DL ) | ( 1 << CP0C1_DA ),
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. CP0_Config2 = MIPS_CONFIG2 ,
. CP0_Config3 = MIPS_CONFIG3 ,
. SYNCI_Step = 32 ,
. CCRes = 2 ,
. CP0_Status_rw_bitmask = 0x1258FF17 ,
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. SEGBITS = 32 ,
. PABITS = 32 ,
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. insn_flags = CPU_MIPS32 | ASE_MIPS16 ,
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. mmu_type = MMU_TYPE_FMT ,
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},
{
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. name = "4KEc" ,
. CP0_PRid = 0x00019000 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( 0x1 << CP0C0_AR ) |
( MMU_TYPE_R4000 << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 15 << CP0C1_MMU ) |
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( 0 << CP0C1_IS ) | ( 3 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 0 << CP0C1_DS ) | ( 3 << CP0C1_DL ) | ( 1 << CP0C1_DA ),
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. CP0_Config2 = MIPS_CONFIG2 ,
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. CP0_Config3 = MIPS_CONFIG3 | ( 0 << CP0C3_VInt ),
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. SYNCI_Step = 32 ,
. CCRes = 2 ,
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. CP0_Status_rw_bitmask = 0x1278FF17 ,
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. SEGBITS = 32 ,
. PABITS = 32 ,
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. insn_flags = CPU_MIPS32R2 | ASE_MIPS16 ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
{
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. name = "4KEm" ,
. CP0_PRid = 0x00019100 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( 0x1 << CP0C0_AR ) |
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( MMU_TYPE_FMT << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 |
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( 0 << CP0C1_IS ) | ( 3 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 0 << CP0C1_DS ) | ( 3 << CP0C1_DL ) | ( 1 << CP0C1_DA ),
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. CP0_Config2 = MIPS_CONFIG2 ,
. CP0_Config3 = MIPS_CONFIG3 ,
. SYNCI_Step = 32 ,
. CCRes = 2 ,
. CP0_Status_rw_bitmask = 0x1258FF17 ,
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. SEGBITS = 32 ,
. PABITS = 32 ,
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. insn_flags = CPU_MIPS32R2 | ASE_MIPS16 ,
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. mmu_type = MMU_TYPE_FMT ,
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},
{
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. name = "24Kc" ,
. CP0_PRid = 0x00019300 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( 0x1 << CP0C0_AR ) |
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( MMU_TYPE_R4000 << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 15 << CP0C1_MMU ) |
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( 0 << CP0C1_IS ) | ( 3 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 0 << CP0C1_DS ) | ( 3 << CP0C1_DL ) | ( 1 << CP0C1_DA ),
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. CP0_Config2 = MIPS_CONFIG2 ,
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. CP0_Config3 = MIPS_CONFIG3 | ( 0 << CP0C3_VInt ),
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. SYNCI_Step = 32 ,
. CCRes = 2 ,
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/* No DSP implemented. */
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. CP0_Status_rw_bitmask = 0x1278FF1F ,
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. SEGBITS = 32 ,
. PABITS = 32 ,
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. insn_flags = CPU_MIPS32R2 | ASE_MIPS16 ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
{
. name = "24Kf" ,
. CP0_PRid = 0x00019300 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( 0x1 << CP0C0_AR ) |
( MMU_TYPE_R4000 << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 1 << CP0C1_FP ) | ( 15 << CP0C1_MMU ) |
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( 0 << CP0C1_IS ) | ( 3 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 0 << CP0C1_DS ) | ( 3 << CP0C1_DL ) | ( 1 << CP0C1_DA ),
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. CP0_Config2 = MIPS_CONFIG2 ,
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. CP0_Config3 = MIPS_CONFIG3 | ( 0 << CP0C3_VInt ),
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. SYNCI_Step = 32 ,
. CCRes = 2 ,
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/* No DSP implemented. */
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. CP0_Status_rw_bitmask = 0x3678FF1F ,
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. CP1_fcr0 = ( 1 << FCR0_F64 ) | ( 1 << FCR0_L ) | ( 1 << FCR0_W ) |
( 1 << FCR0_D ) | ( 1 << FCR0_S ) | ( 0x93 << FCR0_PRID ),
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. SEGBITS = 32 ,
. PABITS = 32 ,
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. insn_flags = CPU_MIPS32R2 | ASE_MIPS16 ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
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{
. name = "34Kf" ,
. CP0_PRid = 0x00019500 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( 0x1 << CP0C0_AR ) |
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( MMU_TYPE_R4000 << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 1 << CP0C1_FP ) | ( 15 << CP0C1_MMU ) |
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( 0 << CP0C1_IS ) | ( 3 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 0 << CP0C1_DS ) | ( 3 << CP0C1_DL ) | ( 1 << CP0C1_DA ),
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. CP0_Config2 = MIPS_CONFIG2 ,
. CP0_Config3 = MIPS_CONFIG3 | ( 0 << CP0C3_VInt ) | ( 1 << CP0C3_MT ),
. SYNCI_Step = 32 ,
. CCRes = 2 ,
/* No DSP implemented. */
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. CP0_Status_rw_bitmask = 0x3678FF1F ,
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/* No DSP implemented. */
. CP0_TCStatus_rw_bitmask = ( 0 << CP0TCSt_TCU3 ) | ( 0 << CP0TCSt_TCU2 ) |
( 1 << CP0TCSt_TCU1 ) | ( 1 << CP0TCSt_TCU0 ) |
( 0 << CP0TCSt_TMX ) | ( 1 << CP0TCSt_DT ) |
( 1 << CP0TCSt_DA ) | ( 1 << CP0TCSt_A ) |
( 0x3 << CP0TCSt_TKSU ) | ( 1 << CP0TCSt_IXMT ) |
( 0xff << CP0TCSt_TASID ),
. CP1_fcr0 = ( 1 << FCR0_F64 ) | ( 1 << FCR0_L ) | ( 1 << FCR0_W ) |
( 1 << FCR0_D ) | ( 1 << FCR0_S ) | ( 0x95 << FCR0_PRID ),
. CP0_SRSCtl = ( 0xf << CP0SRSCtl_HSS ),
. CP0_SRSConf0_rw_bitmask = 0x3fffffff ,
. CP0_SRSConf0 = ( 1 << CP0SRSC0_M ) | ( 0x3fe << CP0SRSC0_SRS3 ) |
( 0x3fe << CP0SRSC0_SRS2 ) | ( 0x3fe << CP0SRSC0_SRS1 ),
. CP0_SRSConf1_rw_bitmask = 0x3fffffff ,
. CP0_SRSConf1 = ( 1 << CP0SRSC1_M ) | ( 0x3fe << CP0SRSC1_SRS6 ) |
( 0x3fe << CP0SRSC1_SRS5 ) | ( 0x3fe << CP0SRSC1_SRS4 ),
. CP0_SRSConf2_rw_bitmask = 0x3fffffff ,
. CP0_SRSConf2 = ( 1 << CP0SRSC2_M ) | ( 0x3fe << CP0SRSC2_SRS9 ) |
( 0x3fe << CP0SRSC2_SRS8 ) | ( 0x3fe << CP0SRSC2_SRS7 ),
. CP0_SRSConf3_rw_bitmask = 0x3fffffff ,
. CP0_SRSConf3 = ( 1 << CP0SRSC3_M ) | ( 0x3fe << CP0SRSC3_SRS12 ) |
( 0x3fe << CP0SRSC3_SRS11 ) | ( 0x3fe << CP0SRSC3_SRS10 ),
. CP0_SRSConf4_rw_bitmask = 0x3fffffff ,
. CP0_SRSConf4 = ( 0x3fe << CP0SRSC4_SRS15 ) |
( 0x3fe << CP0SRSC4_SRS14 ) | ( 0x3fe << CP0SRSC4_SRS13 ),
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. SEGBITS = 32 ,
. PABITS = 32 ,
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. insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
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# if defined ( TARGET_MIPS64 )
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{
. name = "R4000" ,
. CP0_PRid = 0x00000400 ,
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/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
. CP0_Config0 = ( 1 << 17 ) | ( 0x1 << 9 ) | ( 0x1 << 6 ) | ( 0x2 << CP0C0_K0 ),
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/* Note: Config1 is only used internally, the R4000 has only Config0. */
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. CP0_Config1 = ( 1 << CP0C1_FP ) | ( 47 << CP0C1_MMU ),
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. SYNCI_Step = 16 ,
. CCRes = 2 ,
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. CP0_Status_rw_bitmask = 0x3678FFFF ,
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/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
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. CP1_fcr0 = ( 0x5 << FCR0_PRID ) | ( 0x0 << FCR0_REV ),
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. SEGBITS = 40 ,
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. PABITS = 36 ,
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. insn_flags = CPU_MIPS3 ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
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{
. name = "VR5432" ,
. CP0_PRid = 0x00005400 ,
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
. CP0_Config0 = ( 1 << 17 ) | ( 0x1 << 9 ) | ( 0x1 << 6 ) | ( 0x2 << CP0C0_K0 ),
. CP0_Config1 = ( 1 << CP0C1_FP ) | ( 47 << CP0C1_MMU ),
. SYNCI_Step = 16 ,
. CCRes = 2 ,
. CP0_Status_rw_bitmask = 0x3678FFFF ,
/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
. CP1_fcr0 = ( 0x54 << FCR0_PRID ) | ( 0x0 << FCR0_REV ),
. SEGBITS = 40 ,
. PABITS = 32 ,
. insn_flags = CPU_VR54XX ,
. mmu_type = MMU_TYPE_R4000 ,
},
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{
. name = "5Kc" ,
. CP0_PRid = 0x00018100 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( 0x2 << CP0C0_AT ) |
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( MMU_TYPE_R4000 << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 31 << CP0C1_MMU ) |
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( 1 << CP0C1_IS ) | ( 4 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 1 << CP0C1_DS ) | ( 4 << CP0C1_DL ) | ( 1 << CP0C1_DA ) |
( 1 << CP0C1_PC ) | ( 1 << CP0C1_WR ) | ( 1 << CP0C1_EP ),
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. CP0_Config2 = MIPS_CONFIG2 ,
. CP0_Config3 = MIPS_CONFIG3 ,
. SYNCI_Step = 32 ,
. CCRes = 2 ,
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. CP0_Status_rw_bitmask = 0x32F8FFFF ,
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. SEGBITS = 42 ,
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. PABITS = 36 ,
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. insn_flags = CPU_MIPS64 ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
{
. name = "5Kf" ,
. CP0_PRid = 0x00018100 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( 0x2 << CP0C0_AT ) |
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( MMU_TYPE_R4000 << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 1 << CP0C1_FP ) | ( 31 << CP0C1_MMU ) |
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( 1 << CP0C1_IS ) | ( 4 << CP0C1_IL ) | ( 1 << CP0C1_IA ) |
( 1 << CP0C1_DS ) | ( 4 << CP0C1_DL ) | ( 1 << CP0C1_DA ) |
( 1 << CP0C1_PC ) | ( 1 << CP0C1_WR ) | ( 1 << CP0C1_EP ),
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. CP0_Config2 = MIPS_CONFIG2 ,
. CP0_Config3 = MIPS_CONFIG3 ,
. SYNCI_Step = 32 ,
. CCRes = 2 ,
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. CP0_Status_rw_bitmask = 0x36F8FFFF ,
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/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
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. CP1_fcr0 = ( 1 << FCR0_D ) | ( 1 << FCR0_S ) |
( 0x81 << FCR0_PRID ) | ( 0x0 << FCR0_REV ),
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. SEGBITS = 42 ,
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. PABITS = 36 ,
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. insn_flags = CPU_MIPS64 ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
{
. name = "20Kc" ,
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/* We emulate a later version of the 20 Kc , earlier ones had a broken
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WAIT instruction . */
. CP0_PRid = 0x000182a0 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( 0x2 << CP0C0_AT ) |
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( MMU_TYPE_R4000 << CP0C0_MT ) | ( 1 << CP0C0_VI ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 1 << CP0C1_FP ) | ( 47 << CP0C1_MMU ) |
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( 2 << CP0C1_IS ) | ( 4 << CP0C1_IL ) | ( 3 << CP0C1_IA ) |
( 2 << CP0C1_DS ) | ( 4 << CP0C1_DL ) | ( 3 << CP0C1_DA ) |
( 1 << CP0C1_PC ) | ( 1 << CP0C1_WR ) | ( 1 << CP0C1_EP ),
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. CP0_Config2 = MIPS_CONFIG2 ,
. CP0_Config3 = MIPS_CONFIG3 ,
. SYNCI_Step = 32 ,
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. CCRes = 1 ,
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. CP0_Status_rw_bitmask = 0x36FBFFFF ,
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/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
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. CP1_fcr0 = ( 1 << FCR0_3D ) | ( 1 << FCR0_PS ) |
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( 1 << FCR0_D ) | ( 1 << FCR0_S ) |
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( 0x82 << FCR0_PRID ) | ( 0x0 << FCR0_REV ),
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. SEGBITS = 40 ,
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. PABITS = 36 ,
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. insn_flags = CPU_MIPS64 | ASE_MIPS3D ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
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{
391
/* A generic CPU providing MIPS64 Release 2 features .
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FIXME : Eventually this should be replaced by a real CPU model . */
. name = "MIPS64R2-generic" ,
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. CP0_PRid = 0x00010000 ,
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. CP0_Config0 = MIPS_CONFIG0 | ( 0x1 << CP0C0_AR ) | ( 0x2 << CP0C0_AT ) |
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( MMU_TYPE_R4000 << CP0C0_MT ),
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. CP0_Config1 = MIPS_CONFIG1 | ( 1 << CP0C1_FP ) | ( 63 << CP0C1_MMU ) |
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( 2 << CP0C1_IS ) | ( 4 << CP0C1_IL ) | ( 3 << CP0C1_IA ) |
( 2 << CP0C1_DS ) | ( 4 << CP0C1_DL ) | ( 3 << CP0C1_DA ) |
( 1 << CP0C1_PC ) | ( 1 << CP0C1_WR ) | ( 1 << CP0C1_EP ),
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. CP0_Config2 = MIPS_CONFIG2 ,
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. CP0_Config3 = MIPS_CONFIG3 | ( 1 << CP0C3_LPA ),
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. SYNCI_Step = 32 ,
. CCRes = 2 ,
. CP0_Status_rw_bitmask = 0x36FBFFFF ,
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. CP1_fcr0 = ( 1 << FCR0_F64 ) | ( 1 << FCR0_3D ) | ( 1 << FCR0_PS ) |
( 1 << FCR0_L ) | ( 1 << FCR0_W ) | ( 1 << FCR0_D ) |
( 1 << FCR0_S ) | ( 0x00 << FCR0_PRID ) | ( 0x0 << FCR0_REV ),
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. SEGBITS = 42 ,
/* The architectural limit is 59 , but we have hardcoded 36 bit
in some places ...
. PABITS = 59 , */ /* the architectural limit */
. PABITS = 36 ,
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. insn_flags = CPU_MIPS64R2 | ASE_MIPS3D ,
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. mmu_type = MMU_TYPE_R4000 ,
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},
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# endif
};
420
static const mips_def_t * cpu_mips_find_by_name ( const char * name )
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{
422
int i ;
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for ( i = 0 ; i < ARRAY_SIZE ( mips_defs ); i ++ ) {
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if ( strcasecmp ( name , mips_defs [ i ]. name ) == 0 ) {
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return & mips_defs [ i ];
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}
}
429
return NULL ;
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}
void mips_cpu_list ( FILE * f , int ( * cpu_fprintf )( FILE * f , const char * fmt , ...))
{
int i ;
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for ( i = 0 ; i < ARRAY_SIZE ( mips_defs ); i ++ ) {
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( * cpu_fprintf )( f , "MIPS '%s' \n " ,
mips_defs [ i ]. name );
}
}
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# ifndef CONFIG_USER_ONLY
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static void no_mmu_init ( CPUMIPSState * env , const mips_def_t * def )
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{
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env -> tlb -> nb_tlb = 1 ;
env -> tlb -> map_address = & no_mmu_map_address ;
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}
449
static void fixed_mmu_init ( CPUMIPSState * env , const mips_def_t * def )
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{
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env -> tlb -> nb_tlb = 1 ;
env -> tlb -> map_address = & fixed_mmu_map_address ;
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}
455
static void r4k_mmu_init ( CPUMIPSState * env , const mips_def_t * def )
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{
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env -> tlb -> nb_tlb = 1 + (( def -> CP0_Config1 >> CP0C1_MMU ) & 63 );
env -> tlb -> map_address = & r4k_map_address ;
env -> tlb -> do_tlbwi = r4k_do_tlbwi ;
env -> tlb -> do_tlbwr = r4k_do_tlbwr ;
env -> tlb -> do_tlbp = r4k_do_tlbp ;
env -> tlb -> do_tlbr = r4k_do_tlbr ;
}
465
static void mmu_init ( CPUMIPSState * env , const mips_def_t * def )
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{
env -> tlb = qemu_mallocz ( sizeof ( CPUMIPSTLBContext ));
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switch ( def -> mmu_type ) {
case MMU_TYPE_NONE :
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no_mmu_init ( env , def );
break ;
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case MMU_TYPE_R4000 :
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r4k_mmu_init ( env , def );
break ;
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case MMU_TYPE_FMT :
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fixed_mmu_init ( env , def );
break ;
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case MMU_TYPE_R3000 :
case MMU_TYPE_R6000 :
case MMU_TYPE_R8000 :
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default :
cpu_abort ( env , "MMU type not supported \n " );
}
env -> CP0_Random = env -> tlb -> nb_tlb - 1 ;
env -> tlb -> tlb_in_use = env -> tlb -> nb_tlb ;
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}
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# endif /* CONFIG_USER_ONLY */
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static void fpu_init ( CPUMIPSState * env , const mips_def_t * def )
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{
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int i ;
for ( i = 0 ; i < MIPS_FPU_MAX ; i ++ )
env -> fpus [ i ]. fcr0 = def -> CP1_fcr0 ;
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memcpy ( & env -> active_fpu , & env -> fpus [ 0 ], sizeof ( env -> active_fpu ));
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# if defined ( CONFIG_USER_ONLY )
if ( env -> CP0_Config1 & ( 1 << CP0C1_FP ))
env -> hflags |= MIPS_HFLAG_FPU ;
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# ifdef TARGET_MIPS64
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if ( env -> active_fpu . fcr0 & ( 1 << FCR0_F64 ))
env -> hflags |= MIPS_HFLAG_F64 ;
# endif
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# endif
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}
508
static void mvp_init ( CPUMIPSState * env , const mips_def_t * def )
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{
env -> mvp = qemu_mallocz ( sizeof ( CPUMIPSMVPContext ));
/* MVPConf1 implemented , TLB sharable , no gating storage support ,
programmable cache partitioning implemented , number of allocatable
and sharable TLB entries , MVP has allocatable TCs , 2 VPEs
implemented , 5 TCs implemented . */
env -> mvp -> CP0_MVPConf0 = ( 1 << CP0MVPC0_M ) | ( 1 << CP0MVPC0_TLBS ) |
( 0 << CP0MVPC0_GS ) | ( 1 << CP0MVPC0_PCP ) |
// TODO : actually do 2 VPEs .
// ( 1 << CP0MVPC0_TCA ) | ( 0x1 << CP0MVPC0_PVPE ) |
// ( 0x04 << CP0MVPC0_PTC );
( 1 << CP0MVPC0_TCA ) | ( 0x0 << CP0MVPC0_PVPE ) |
( 0x04 << CP0MVPC0_PTC );
523
# if ! defined ( CONFIG_USER_ONLY )
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/* Usermode has no TLB support */
525
526
env -> mvp -> CP0_MVPConf0 |= ( env -> tlb -> nb_tlb << CP0MVPC0_PTLBE );
# endif
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/* Allocatable CP1 have media extensions , allocatable CP1 have FP support ,
no UDI implemented , no CP2 implemented , 1 CP1 implemented . */
env -> mvp -> CP0_MVPConf1 = ( 1 << CP0MVPC1_CIM ) | ( 1 << CP0MVPC1_CIF ) |
( 0x0 << CP0MVPC1_PCX ) | ( 0x0 << CP0MVPC1_PCP2 ) |
( 0x1 << CP0MVPC1_PCP1 );
}
535
static int cpu_mips_register ( CPUMIPSState * env , const mips_def_t * def )
ths
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{
env -> CP0_PRid = def -> CP0_PRid ;
env -> CP0_Config0 = def -> CP0_Config0 ;
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540
# ifdef TARGET_WORDS_BIGENDIAN
env -> CP0_Config0 |= ( 1 << CP0C0_BE );
ths
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541
# endif
ths
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env -> CP0_Config1 = def -> CP0_Config1 ;
ths
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env -> CP0_Config2 = def -> CP0_Config2 ;
env -> CP0_Config3 = def -> CP0_Config3 ;
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env -> CP0_Config6 = def -> CP0_Config6 ;
env -> CP0_Config7 = def -> CP0_Config7 ;
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env -> SYNCI_Step = def -> SYNCI_Step ;
env -> CCRes = def -> CCRes ;
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env -> CP0_Status_rw_bitmask = def -> CP0_Status_rw_bitmask ;
env -> CP0_TCStatus_rw_bitmask = def -> CP0_TCStatus_rw_bitmask ;
env -> CP0_SRSCtl = def -> CP0_SRSCtl ;
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env -> current_tc = 0 ;
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env -> SEGBITS = def -> SEGBITS ;
env -> SEGMask = ( target_ulong )(( 1ULL << def -> SEGBITS ) - 1 );
ths
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# if defined ( TARGET_MIPS64 )
ths
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if ( def -> insn_flags & ISA_MIPS3 ) {
ths
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env -> hflags |= MIPS_HFLAG_64 ;
ths
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env -> SEGMask |= 3ULL << 62 ;
ths
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}
ths
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# endif
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env -> PABITS = def -> PABITS ;
env -> PAMask = ( target_ulong )(( 1ULL << def -> PABITS ) - 1 );
ths
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env -> CP0_SRSConf0_rw_bitmask = def -> CP0_SRSConf0_rw_bitmask ;
env -> CP0_SRSConf0 = def -> CP0_SRSConf0 ;
env -> CP0_SRSConf1_rw_bitmask = def -> CP0_SRSConf1_rw_bitmask ;
env -> CP0_SRSConf1 = def -> CP0_SRSConf1 ;
env -> CP0_SRSConf2_rw_bitmask = def -> CP0_SRSConf2_rw_bitmask ;
env -> CP0_SRSConf2 = def -> CP0_SRSConf2 ;
env -> CP0_SRSConf3_rw_bitmask = def -> CP0_SRSConf3_rw_bitmask ;
env -> CP0_SRSConf3 = def -> CP0_SRSConf3 ;
env -> CP0_SRSConf4_rw_bitmask = def -> CP0_SRSConf4_rw_bitmask ;
env -> CP0_SRSConf4 = def -> CP0_SRSConf4 ;
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573
env -> insn_flags = def -> insn_flags ;
ths
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574
ths
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575
# ifndef CONFIG_USER_ONLY
576
mmu_init ( env , def );
ths
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577
# endif
ths
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578
579
fpu_init ( env , def );
mvp_init ( env , def );
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580
581
return 0 ;
}