Add support for 5Kc/5Kf/20Kc, based on a patch by Aurelien Jarno.

Note that the F64 flag isn't usable on any of those (and the R4000), so all our 64bit FPU goodness goes out of the window until a shadow capability flag is implemented. :-( git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2910 c046a42c-6fe2-441c-8c8c-71466251a162

Add support for 5Kc/5Kf/20Kc, based on a patch by Aurelien Jarno.
Note that the F64 flag isn't usable on any of those (and the R4000), so all our 64bit FPU goodness goes out of the window until a shadow capability flag is implemented. :-( git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2910 c046a42c-6fe2-441c-8c8c-71466251a162
ths
1 parent 2052caa7
Showing 2 changed files with 51 additions and 3 deletions
hw/mips_malta.c
target-mips/translate_init.c
@@ -784,7 +784,7 @@ void mips_malta_init (int ram_size, int vga_ram_size, int boot_device,
     /* init CPUs */
     if (cpu_model == NULL) {
 #ifdef TARGET_MIPS64
-        cpu_model = "R4000";
+        cpu_model = "20Kc";
 #else
         cpu_model = "24Kf";
 #endif
@@ -146,9 +146,57 @@ static mips_def_t mips_defs[] =
         .SYNCI_Step = 16,
         .CCRes = 2,
         .Status_rw_bitmask = 0x3678FFFF,
-        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+	/* XXX: The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
+        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+    },
+    {
+        .name = "5Kc",
+        .CP0_PRid = 0x00018100,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
+        .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
+		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+		    (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .Status_rw_bitmask = 0x3278FFFF,
+    },
+    {
+        .name = "5Kf",
+        .CP0_PRid = 0x00018100,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
+		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+		    (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .Status_rw_bitmask = 0x3678FFFF,
+	/* XXX: The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
+        .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
+                    (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
+    },
+    {
+        .name = "20Kc",
+        .CP0_PRid = 0x00018200,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
+		    (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+		    (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .Status_rw_bitmask = 0x36FBFFFF,
+	/* XXX: The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
+        .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
                     (1 << FCR0_D) | (1 << FCR0_S) |
-                    (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+                    (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
     },
 #endif
 };