gwj / at91sam9263 · Commits

Commit 8d162c2b68db72623a507069fda0e35ccd1c6b85

Authored by ths
1 parent 082c6681

Add older 4Km variants. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3708 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 34 additions and 0 deletions
target-mips/translate_init.c
  View file @8d162c2
... ... @@ -101,6 +101,23 @@ static mips_def_t mips_defs[] =
101 101 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
102 102 },
103 103 {
  104 + .name = "4Km",
  105 + .CP0_PRid = 0x00018300,
  106 + /* Config1 implemented, fixed mapping MMU,
  107 + no virtual icache, uncached coherency. */
  108 + .CP0_Config0 = (1 << CP0C0_M) |
  109 + (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
  110 + .CP0_Config1 = MIPS_CONFIG1 |
  111 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  112 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  113 + .CP0_Config2 = MIPS_CONFIG2,
  114 + .CP0_Config3 = MIPS_CONFIG3,
  115 + .SYNCI_Step = 32,
  116 + .CCRes = 2,
  117 + .CP0_Status_rw_bitmask = 0x1258FF17,
  118 + .insn_flags = CPU_MIPS32 | ASE_MIPS16,
  119 + },
  120 + {
104 121 .name = "4KEcR1",
105 122 .CP0_PRid = 0x00018400,
106 123 .CP0_Config0 = MIPS_CONFIG0,
... ... @@ -115,6 +132,23 @@ static mips_def_t mips_defs[] =
115 132 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
116 133 },
117 134 {
  135 + .name = "4KEmR1",
  136 + .CP0_PRid = 0x00018500,
  137 + /* Config1 implemented, fixed mapping MMU,
  138 + no virtual icache, uncached coherency. */
  139 + .CP0_Config0 = (1 << CP0C0_M) |
  140 + (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
  141 + .CP0_Config1 = MIPS_CONFIG1 |
  142 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  143 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  144 + .CP0_Config2 = MIPS_CONFIG2,
  145 + .CP0_Config3 = MIPS_CONFIG3,
  146 + .SYNCI_Step = 32,
  147 + .CCRes = 2,
  148 + .CP0_Status_rw_bitmask = 0x1258FF17,
  149 + .insn_flags = CPU_MIPS32 | ASE_MIPS16,
  150 + },
  151 + {
118 152 .name = "4KEc",
119 153 .CP0_PRid = 0x00019000,
120 154 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
... ...