gwj / at91sam9263 · Commits

Commit 2f6445458e5e9eec54c9f47071bbc6ac70c54c02

Authored by ths
1 parent b48cfdff

Make SYNCI_Step and CCRes CPU-specific. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2651 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 16 additions and 3 deletions
target-mips/translate.c
  View file @2f64454
... ... @@ -5435,9 +5435,6 @@ void cpu_reset (CPUMIPSState *env)
5435 5435 env->hflags |= MIPS_HFLAG_UM;
5436 5436 env->user_mode_only = 1;
5437 5437 #endif
5438   - /* XXX some guesswork here, values are CPU specific */
5439   - env->SYNCI_Step = 16;
5440   - env->CCRes = 2;
5441 5438 }
5442 5439  
5443 5440 #include "translate_init.c"
... ...
target-mips/translate_init.c
  View file @2f64454
... ... @@ -67,6 +67,8 @@ struct mips_def_t {
67 67 int32_t CP0_Config3;
68 68 int32_t CP0_Config6;
69 69 int32_t CP0_Config7;
  70 + int32_t SYNCI_Step;
  71 + int32_t CCRes;
70 72 int32_t CP1_fcr0;
71 73 };
72 74  
... ... @@ -82,6 +84,8 @@ static mips_def_t mips_defs[] =
82 84 .CP0_Config1 = MIPS_CONFIG1,
83 85 .CP0_Config2 = MIPS_CONFIG2,
84 86 .CP0_Config3 = MIPS_CONFIG3,
  87 + .SYNCI_Step = 32,
  88 + .CCRes = 2,
85 89 .CP1_fcr0 = MIPS_FCR0,
86 90 },
87 91 {
... ... @@ -91,6 +95,8 @@ static mips_def_t mips_defs[] =
91 95 .CP0_Config1 = MIPS_CONFIG1,
92 96 .CP0_Config2 = MIPS_CONFIG2,
93 97 .CP0_Config3 = MIPS_CONFIG3,
  98 + .SYNCI_Step = 32,
  99 + .CCRes = 2,
94 100 .CP1_fcr0 = MIPS_FCR0,
95 101 },
96 102 {
... ... @@ -100,6 +106,8 @@ static mips_def_t mips_defs[] =
100 106 .CP0_Config1 = MIPS_CONFIG1,
101 107 .CP0_Config2 = MIPS_CONFIG2,
102 108 .CP0_Config3 = MIPS_CONFIG3,
  109 + .SYNCI_Step = 32,
  110 + .CCRes = 2,
103 111 .CP1_fcr0 = MIPS_FCR0,
104 112 },
105 113 {
... ... @@ -109,6 +117,8 @@ static mips_def_t mips_defs[] =
109 117 .CP0_Config1 = MIPS_CONFIG1,
110 118 .CP0_Config2 = MIPS_CONFIG2,
111 119 .CP0_Config3 = MIPS_CONFIG3,
  120 + .SYNCI_Step = 32,
  121 + .CCRes = 2,
112 122 .CP1_fcr0 = MIPS_FCR0,
113 123 },
114 124 {
... ... @@ -118,6 +128,8 @@ static mips_def_t mips_defs[] =
118 128 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
119 129 .CP0_Config2 = MIPS_CONFIG2,
120 130 .CP0_Config3 = MIPS_CONFIG3,
  131 + .SYNCI_Step = 32,
  132 + .CCRes = 2,
121 133 .CP1_fcr0 = MIPS_FCR0,
122 134 },
123 135 #else
... ... @@ -128,6 +140,8 @@ static mips_def_t mips_defs[] =
128 140 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
129 141 .CP0_Config2 = MIPS_CONFIG2,
130 142 .CP0_Config3 = MIPS_CONFIG3,
  143 + .SYNCI_Step = 16,
  144 + .CCRes = 2,
131 145 .CP1_fcr0 = MIPS_FCR0,
132 146 },
133 147 #endif
... ... @@ -175,6 +189,8 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
175 189 env->CP0_Config3 = def->CP0_Config3;
176 190 env->CP0_Config6 = def->CP0_Config6;
177 191 env->CP0_Config7 = def->CP0_Config7;
  192 + env->SYNCI_Step = def->SYNCI_Step;
  193 + env->CCRes = def->CCRes;
178 194 env->fcr0 = def->CP1_fcr0;
179 195 return 0;
180 196 }
... ...