gwj / at91sam9263 · Commits

Commit 34ee2edebb992b5d3f7c383a3d0c34f3e75880c8

Authored by ths
1 parent 3e736bf4

One more bit of mips CPU configuration, and support for early 4KEc 

which implemented only MIPS32R1. Thanks to Stefan Weil to insist he's
right on that. :-)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2533 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 23 additions and 1 deletions
target-mips/translate_init.c
  View file @34ee2ed
... ... @@ -65,6 +65,8 @@ struct mips_def_t {
65 65 int32_t CP0_Config1;
66 66 int32_t CP0_Config2;
67 67 int32_t CP0_Config3;
  68 + int32_t CP0_Config6;
  69 + int32_t CP0_Config7;
68 70 int32_t CP1_fcr0;
69 71 };
70 72  
... ... @@ -83,8 +85,26 @@ static mips_def_t mips_defs[] =
83 85 .CP1_fcr0 = MIPS_FCR0,
84 86 },
85 87 {
86   - .name = "4KEc",
  88 + .name = "4KEcR1",
87 89 .CP0_PRid = 0x00018400,
  90 + .CP0_Config0 = MIPS_CONFIG0,
  91 + .CP0_Config1 = MIPS_CONFIG1,
  92 + .CP0_Config2 = MIPS_CONFIG2,
  93 + .CP0_Config3 = MIPS_CONFIG3,
  94 + .CP1_fcr0 = MIPS_FCR0,
  95 + },
  96 + {
  97 + .name = "4KEc",
  98 + .CP0_PRid = 0x00019000,
  99 + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
  100 + .CP0_Config1 = MIPS_CONFIG1,
  101 + .CP0_Config2 = MIPS_CONFIG2,
  102 + .CP0_Config3 = MIPS_CONFIG3,
  103 + .CP1_fcr0 = MIPS_FCR0,
  104 + },
  105 + {
  106 + .name = "24Kc",
  107 + .CP0_PRid = 0x00019300,
88 108 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
89 109 .CP0_Config1 = MIPS_CONFIG1,
90 110 .CP0_Config2 = MIPS_CONFIG2,
... ... @@ -153,6 +173,8 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
153 173 env->CP0_Config1 = def->CP0_Config1;
154 174 env->CP0_Config2 = def->CP0_Config2;
155 175 env->CP0_Config3 = def->CP0_Config3;
  176 + env->CP0_Config6 = def->CP0_Config6;
  177 + env->CP0_Config7 = def->CP0_Config7;
156 178 env->fcr0 = def->CP1_fcr0;
157 179 return 0;
158 180 }
... ...