gwj / at91sam9263 · Commits

Commit 0eaef5aa01a8e27b57a46217a0b65cc1d30a5d41

Authored by ths
1 parent 477e3edf

Less hardcoding of TARGET_USER_ONLY. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 6 changed files with 287 additions and 390 deletions
target-mips/cpu.h
  View file @0eaef5a
... ... @@ -445,17 +445,12 @@ struct CPUMIPSState {
445 445 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
446 446 int insn_flags; /* Supported instruction set */
447 447  
448   -#ifdef CONFIG_USER_ONLY
449   - target_ulong tls_value;
450   -#endif
  448 + target_ulong tls_value; /* For usermode emulation */
451 449  
452 450 CPU_COMMON
453 451  
454 452 const mips_def_t *cpu_model;
455   -#ifndef CONFIG_USER_ONLY
456 453 void *irq[8];
457   -#endif
458   -
459 454 struct QEMUTimer *timer; /* Internal timer */
460 455 };
461 456  
... ... @@ -494,7 +489,6 @@ static inline int cpu_mmu_index (CPUState *env)
494 489 return env->hflags & MIPS_HFLAG_KSU;
495 490 }
496 491  
497   -#if defined(CONFIG_USER_ONLY)
498 492 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
499 493 {
500 494 if (newsp)
... ... @@ -502,7 +496,6 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
502 496 env->active_tc.gpr[7] = 0;
503 497 env->active_tc.gpr[2] = 0;
504 498 }
505   -#endif
506 499  
507 500 #include "cpu-all.h"
508 501  
... ...
target-mips/helper.c
  View file @0eaef5a
... ... @@ -206,26 +206,23 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
206 206 return ret;
207 207 }
208 208  
209   -#if defined(CONFIG_USER_ONLY)
210 209 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
211 210 {
212   - return addr;
213   -}
214   -#else
215   -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
216   -{
217   - target_ulong phys_addr;
218   - int prot;
  211 + if (env->user_mode_only)
  212 + return addr;
  213 + else {
  214 + target_ulong phys_addr;
  215 + int prot;
219 216  
220   - if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
221   - return -1;
222   - return phys_addr;
  217 + if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
  218 + return -1;
  219 + return phys_addr;
  220 + }
223 221 }
224 222  
225 223 void cpu_mips_init_mmu (CPUState *env)
226 224 {
227 225 }
228   -#endif /* !defined(CONFIG_USER_ONLY) */
229 226  
230 227 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
231 228 int mmu_idx, int is_softmmu)
... ... @@ -318,7 +315,6 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
318 315 return ret;
319 316 }
320 317  
321   -#if !defined(CONFIG_USER_ONLY)
322 318 static const char * const excp_names[EXCP_LAST + 1] = {
323 319 [EXCP_RESET] = "reset",
324 320 [EXCP_SRESET] = "soft reset",
... ... @@ -354,232 +350,230 @@ static const char * const excp_names[EXCP_LAST + 1] = {
354 350 [EXCP_C2E] = "precise coprocessor 2",
355 351 [EXCP_CACHE] = "cache error",
356 352 };
357   -#endif
358 353  
359 354 void do_interrupt (CPUState *env)
360 355 {
361   -#if !defined(CONFIG_USER_ONLY)
362   - target_ulong offset;
363   - int cause = -1;
364   - const char *name;
365   -
366   - if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
367   - if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
368   - name = "unknown";
369   - else
370   - name = excp_names[env->exception_index];
371   -
372   - fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
373   - __func__, env->active_tc.PC, env->CP0_EPC, name);
374   - }
375   - if (env->exception_index == EXCP_EXT_INTERRUPT &&
376   - (env->hflags & MIPS_HFLAG_DM))
377   - env->exception_index = EXCP_DINT;
378   - offset = 0x180;
379   - switch (env->exception_index) {
380   - case EXCP_DSS:
381   - env->CP0_Debug |= 1 << CP0DB_DSS;
382   - /* Debug single step cannot be raised inside a delay slot and
383   - * resume will always occur on the next instruction
384   - * (but we assume the pc has always been updated during
385   - * code translation).
386   - */
387   - env->CP0_DEPC = env->active_tc.PC;
388   - goto enter_debug_mode;
389   - case EXCP_DINT:
390   - env->CP0_Debug |= 1 << CP0DB_DINT;
391   - goto set_DEPC;
392   - case EXCP_DIB:
393   - env->CP0_Debug |= 1 << CP0DB_DIB;
394   - goto set_DEPC;
395   - case EXCP_DBp:
396   - env->CP0_Debug |= 1 << CP0DB_DBp;
397   - goto set_DEPC;
398   - case EXCP_DDBS:
399   - env->CP0_Debug |= 1 << CP0DB_DDBS;
400   - goto set_DEPC;
401   - case EXCP_DDBL:
402   - env->CP0_Debug |= 1 << CP0DB_DDBL;
403   - set_DEPC:
404   - if (env->hflags & MIPS_HFLAG_BMASK) {
405   - /* If the exception was raised from a delay slot,
406   - come back to the jump. */
407   - env->CP0_DEPC = env->active_tc.PC - 4;
408   - env->hflags &= ~MIPS_HFLAG_BMASK;
409   - } else {
410   - env->CP0_DEPC = env->active_tc.PC;
411   - }
412   - enter_debug_mode:
413   - env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
414   - env->hflags &= ~(MIPS_HFLAG_KSU);
415   - /* EJTAG probe trap enable is not implemented... */
416   - if (!(env->CP0_Status & (1 << CP0St_EXL)))
417   - env->CP0_Cause &= ~(1 << CP0Ca_BD);
418   - env->active_tc.PC = (int32_t)0xBFC00480;
419   - break;
420   - case EXCP_RESET:
421   - cpu_reset(env);
422   - break;
423   - case EXCP_SRESET:
424   - env->CP0_Status |= (1 << CP0St_SR);
425   - memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
426   - goto set_error_EPC;
427   - case EXCP_NMI:
428   - env->CP0_Status |= (1 << CP0St_NMI);
429   - set_error_EPC:
430   - if (env->hflags & MIPS_HFLAG_BMASK) {
431   - /* If the exception was raised from a delay slot,
432   - come back to the jump. */
433   - env->CP0_ErrorEPC = env->active_tc.PC - 4;
434   - env->hflags &= ~MIPS_HFLAG_BMASK;
435   - } else {
436   - env->CP0_ErrorEPC = env->active_tc.PC;
437   - }
438   - env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
439   - env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
440   - env->hflags &= ~(MIPS_HFLAG_KSU);
441   - if (!(env->CP0_Status & (1 << CP0St_EXL)))
442   - env->CP0_Cause &= ~(1 << CP0Ca_BD);
443   - env->active_tc.PC = (int32_t)0xBFC00000;
444   - break;
445   - case EXCP_EXT_INTERRUPT:
446   - cause = 0;
447   - if (env->CP0_Cause & (1 << CP0Ca_IV))
448   - offset = 0x200;
449   - goto set_EPC;
450   - case EXCP_LTLBL:
451   - cause = 1;
452   - goto set_EPC;
453   - case EXCP_TLBL:
454   - cause = 2;
455   - if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
456   -#if defined(TARGET_MIPS64)
457   - int R = env->CP0_BadVAddr >> 62;
458   - int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
459   - int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
460   - int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
  356 + if (!env->user_mode_only) {
  357 + target_ulong offset;
  358 + int cause = -1;
  359 + const char *name;
461 360  
462   - if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
463   - offset = 0x080;
  361 + if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
  362 + if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
  363 + name = "unknown";
464 364 else
465   -#endif
466   - offset = 0x000;
467   - }
468   - goto set_EPC;
469   - case EXCP_TLBS:
470   - cause = 3;
471   - if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
472   -#if defined(TARGET_MIPS64)
473   - int R = env->CP0_BadVAddr >> 62;
474   - int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
475   - int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
476   - int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
  365 + name = excp_names[env->exception_index];
477 366  
478   - if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
479   - offset = 0x080;
480   - else
481   -#endif
482   - offset = 0x000;
483   - }
484   - goto set_EPC;
485   - case EXCP_AdEL:
486   - cause = 4;
487   - goto set_EPC;
488   - case EXCP_AdES:
489   - cause = 5;
490   - goto set_EPC;
491   - case EXCP_IBE:
492   - cause = 6;
493   - goto set_EPC;
494   - case EXCP_DBE:
495   - cause = 7;
496   - goto set_EPC;
497   - case EXCP_SYSCALL:
498   - cause = 8;
499   - goto set_EPC;
500   - case EXCP_BREAK:
501   - cause = 9;
502   - goto set_EPC;
503   - case EXCP_RI:
504   - cause = 10;
505   - goto set_EPC;
506   - case EXCP_CpU:
507   - cause = 11;
508   - env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
509   - (env->error_code << CP0Ca_CE);
510   - goto set_EPC;
511   - case EXCP_OVERFLOW:
512   - cause = 12;
513   - goto set_EPC;
514   - case EXCP_TRAP:
515   - cause = 13;
516   - goto set_EPC;
517   - case EXCP_FPE:
518   - cause = 15;
519   - goto set_EPC;
520   - case EXCP_C2E:
521   - cause = 18;
522   - goto set_EPC;
523   - case EXCP_MDMX:
524   - cause = 22;
525   - goto set_EPC;
526   - case EXCP_DWATCH:
527   - cause = 23;
528   - /* XXX: TODO: manage defered watch exceptions */
529   - goto set_EPC;
530   - case EXCP_MCHECK:
531   - cause = 24;
532   - goto set_EPC;
533   - case EXCP_THREAD:
534   - cause = 25;
535   - goto set_EPC;
536   - case EXCP_CACHE:
537   - cause = 30;
538   - if (env->CP0_Status & (1 << CP0St_BEV)) {
539   - offset = 0x100;
540   - } else {
541   - offset = 0x20000100;
  367 + fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
  368 + __func__, env->active_tc.PC, env->CP0_EPC, name);
542 369 }
543   - set_EPC:
544   - if (!(env->CP0_Status & (1 << CP0St_EXL))) {
  370 + if (env->exception_index == EXCP_EXT_INTERRUPT &&
  371 + (env->hflags & MIPS_HFLAG_DM))
  372 + env->exception_index = EXCP_DINT;
  373 + offset = 0x180;
  374 + switch (env->exception_index) {
  375 + case EXCP_DSS:
  376 + env->CP0_Debug |= 1 << CP0DB_DSS;
  377 + /* Debug single step cannot be raised inside a delay slot and
  378 + resume will always occur on the next instruction
  379 + (but we assume the pc has always been updated during
  380 + code translation). */
  381 + env->CP0_DEPC = env->active_tc.PC;
  382 + goto enter_debug_mode;
  383 + case EXCP_DINT:
  384 + env->CP0_Debug |= 1 << CP0DB_DINT;
  385 + goto set_DEPC;
  386 + case EXCP_DIB:
  387 + env->CP0_Debug |= 1 << CP0DB_DIB;
  388 + goto set_DEPC;
  389 + case EXCP_DBp:
  390 + env->CP0_Debug |= 1 << CP0DB_DBp;
  391 + goto set_DEPC;
  392 + case EXCP_DDBS:
  393 + env->CP0_Debug |= 1 << CP0DB_DDBS;
  394 + goto set_DEPC;
  395 + case EXCP_DDBL:
  396 + env->CP0_Debug |= 1 << CP0DB_DDBL;
  397 + set_DEPC:
545 398 if (env->hflags & MIPS_HFLAG_BMASK) {
546 399 /* If the exception was raised from a delay slot,
547 400 come back to the jump. */
548   - env->CP0_EPC = env->active_tc.PC - 4;
549   - env->CP0_Cause |= (1 << CP0Ca_BD);
  401 + env->CP0_DEPC = env->active_tc.PC - 4;
  402 + env->hflags &= ~MIPS_HFLAG_BMASK;
550 403 } else {
551   - env->CP0_EPC = env->active_tc.PC;
  404 + env->CP0_DEPC = env->active_tc.PC;
  405 + }
  406 + enter_debug_mode:
  407 + env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
  408 + env->hflags &= ~(MIPS_HFLAG_KSU);
  409 + /* EJTAG probe trap enable is not implemented... */
  410 + if (!(env->CP0_Status & (1 << CP0St_EXL)))
552 411 env->CP0_Cause &= ~(1 << CP0Ca_BD);
  412 + env->active_tc.PC = (int32_t)0xBFC00480;
  413 + break;
  414 + case EXCP_RESET:
  415 + cpu_reset(env);
  416 + break;
  417 + case EXCP_SRESET:
  418 + env->CP0_Status |= (1 << CP0St_SR);
  419 + memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
  420 + goto set_error_EPC;
  421 + case EXCP_NMI:
  422 + env->CP0_Status |= (1 << CP0St_NMI);
  423 + set_error_EPC:
  424 + if (env->hflags & MIPS_HFLAG_BMASK) {
  425 + /* If the exception was raised from a delay slot,
  426 + come back to the jump. */
  427 + env->CP0_ErrorEPC = env->active_tc.PC - 4;
  428 + env->hflags &= ~MIPS_HFLAG_BMASK;
  429 + } else {
  430 + env->CP0_ErrorEPC = env->active_tc.PC;
553 431 }
554   - env->CP0_Status |= (1 << CP0St_EXL);
  432 + env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
555 433 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
556 434 env->hflags &= ~(MIPS_HFLAG_KSU);
  435 + if (!(env->CP0_Status & (1 << CP0St_EXL)))
  436 + env->CP0_Cause &= ~(1 << CP0Ca_BD);
  437 + env->active_tc.PC = (int32_t)0xBFC00000;
  438 + break;
  439 + case EXCP_EXT_INTERRUPT:
  440 + cause = 0;
  441 + if (env->CP0_Cause & (1 << CP0Ca_IV))
  442 + offset = 0x200;
  443 + goto set_EPC;
  444 + case EXCP_LTLBL:
  445 + cause = 1;
  446 + goto set_EPC;
  447 + case EXCP_TLBL:
  448 + cause = 2;
  449 + if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
  450 +#if defined(TARGET_MIPS64)
  451 + int R = env->CP0_BadVAddr >> 62;
  452 + int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
  453 + int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
  454 + int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
  455 +
  456 + if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
  457 + offset = 0x080;
  458 + else
  459 +#endif
  460 + offset = 0x000;
  461 + }
  462 + goto set_EPC;
  463 + case EXCP_TLBS:
  464 + cause = 3;
  465 + if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
  466 +#if defined(TARGET_MIPS64)
  467 + int R = env->CP0_BadVAddr >> 62;
  468 + int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
  469 + int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
  470 + int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
  471 +
  472 + if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
  473 + offset = 0x080;
  474 + else
  475 +#endif
  476 + offset = 0x000;
  477 + }
  478 + goto set_EPC;
  479 + case EXCP_AdEL:
  480 + cause = 4;
  481 + goto set_EPC;
  482 + case EXCP_AdES:
  483 + cause = 5;
  484 + goto set_EPC;
  485 + case EXCP_IBE:
  486 + cause = 6;
  487 + goto set_EPC;
  488 + case EXCP_DBE:
  489 + cause = 7;
  490 + goto set_EPC;
  491 + case EXCP_SYSCALL:
  492 + cause = 8;
  493 + goto set_EPC;
  494 + case EXCP_BREAK:
  495 + cause = 9;
  496 + goto set_EPC;
  497 + case EXCP_RI:
  498 + cause = 10;
  499 + goto set_EPC;
  500 + case EXCP_CpU:
  501 + cause = 11;
  502 + env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
  503 + (env->error_code << CP0Ca_CE);
  504 + goto set_EPC;
  505 + case EXCP_OVERFLOW:
  506 + cause = 12;
  507 + goto set_EPC;
  508 + case EXCP_TRAP:
  509 + cause = 13;
  510 + goto set_EPC;
  511 + case EXCP_FPE:
  512 + cause = 15;
  513 + goto set_EPC;
  514 + case EXCP_C2E:
  515 + cause = 18;
  516 + goto set_EPC;
  517 + case EXCP_MDMX:
  518 + cause = 22;
  519 + goto set_EPC;
  520 + case EXCP_DWATCH:
  521 + cause = 23;
  522 + /* XXX: TODO: manage defered watch exceptions */
  523 + goto set_EPC;
  524 + case EXCP_MCHECK:
  525 + cause = 24;
  526 + goto set_EPC;
  527 + case EXCP_THREAD:
  528 + cause = 25;
  529 + goto set_EPC;
  530 + case EXCP_CACHE:
  531 + cause = 30;
  532 + if (env->CP0_Status & (1 << CP0St_BEV)) {
  533 + offset = 0x100;
  534 + } else {
  535 + offset = 0x20000100;
  536 + }
  537 + set_EPC:
  538 + if (!(env->CP0_Status & (1 << CP0St_EXL))) {
  539 + if (env->hflags & MIPS_HFLAG_BMASK) {
  540 + /* If the exception was raised from a delay slot,
  541 + come back to the jump. */
  542 + env->CP0_EPC = env->active_tc.PC - 4;
  543 + env->CP0_Cause |= (1 << CP0Ca_BD);
  544 + } else {
  545 + env->CP0_EPC = env->active_tc.PC;
  546 + env->CP0_Cause &= ~(1 << CP0Ca_BD);
  547 + }
  548 + env->CP0_Status |= (1 << CP0St_EXL);
  549 + env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
  550 + env->hflags &= ~(MIPS_HFLAG_KSU);
  551 + }
  552 + env->hflags &= ~MIPS_HFLAG_BMASK;
  553 + if (env->CP0_Status & (1 << CP0St_BEV)) {
  554 + env->active_tc.PC = (int32_t)0xBFC00200;
  555 + } else {
  556 + env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
  557 + }
  558 + env->active_tc.PC += offset;
  559 + env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
  560 + break;
  561 + default:
  562 + if (logfile) {
  563 + fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
  564 + env->exception_index);
  565 + }
  566 + printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
  567 + exit(1);
557 568 }
558   - env->hflags &= ~MIPS_HFLAG_BMASK;
559   - if (env->CP0_Status & (1 << CP0St_BEV)) {
560   - env->active_tc.PC = (int32_t)0xBFC00200;
561   - } else {
562   - env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
563   - }
564   - env->active_tc.PC += offset;
565   - env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
566   - break;
567   - default:
568   - if (logfile) {
569   - fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
570   - env->exception_index);
  569 + if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
  570 + fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
  571 + " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
  572 + __func__, env->active_tc.PC, env->CP0_EPC, cause,
  573 + env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
  574 + env->CP0_DEPC);
571 575 }
572   - printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
573   - exit(1);
574   - }
575   - if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
576   - fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
577   - " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
578   - __func__, env->active_tc.PC, env->CP0_EPC, cause,
579   - env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
580   - env->CP0_DEPC);
581 576 }
582   -#endif /* !defined(CONFIG_USER_ONLY) */
583 577 env->exception_index = EXCP_NONE;
584 578 }
585 579  
... ...
target-mips/helper.h
  View file @0eaef5a
... ... @@ -41,8 +41,8 @@ DEF_HELPER(target_ulong, do_macchiu, (target_ulong t0, target_ulong t1))
41 41 DEF_HELPER(target_ulong, do_msachi, (target_ulong t0, target_ulong t1))
42 42 DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1))
43 43  
44   -/* CP0 helpers */
45 44 #ifndef CONFIG_USER_ONLY
  45 +/* CP0 helpers */
46 46 DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (void))
47 47 DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (void))
48 48 DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (void))
... ... @@ -135,7 +135,6 @@ DEF_HELPER(void, do_mtc0_taglo, (target_ulong t0))
135 135 DEF_HELPER(void, do_mtc0_datalo, (target_ulong t0))
136 136 DEF_HELPER(void, do_mtc0_taghi, (target_ulong t0))
137 137 DEF_HELPER(void, do_mtc0_datahi, (target_ulong t0))
138   -#endif /* !CONFIG_USER_ONLY */
139 138  
140 139 /* MIPS MT functions */
141 140 DEF_HELPER(target_ulong, do_mftgpr, (target_ulong t0, uint32_t sel))
... ... @@ -152,6 +151,7 @@ DEF_HELPER(target_ulong, do_dmt, (target_ulong t0))
152 151 DEF_HELPER(target_ulong, do_emt, (target_ulong t0))
153 152 DEF_HELPER(target_ulong, do_dvpe, (target_ulong t0))
154 153 DEF_HELPER(target_ulong, do_evpe, (target_ulong t0))
  154 +#endif /* !CONFIG_USER_ONLY */
155 155 DEF_HELPER(void, do_fork, (target_ulong t0, target_ulong t1))
156 156 DEF_HELPER(target_ulong, do_yield, (target_ulong t0))
157 157  
... ... @@ -257,10 +257,12 @@ FOP_PROTO(ngt)
257 257 #undef FOP_PROTO
258 258  
259 259 /* Special functions */
  260 +#ifndef CONFIG_USER_ONLY
260 261 DEF_HELPER(target_ulong, do_di, (void))
261 262 DEF_HELPER(target_ulong, do_ei, (void))
262 263 DEF_HELPER(void, do_eret, (void))
263 264 DEF_HELPER(void, do_deret, (void))
  265 +#endif /* !CONFIG_USER_ONLY */
264 266 DEF_HELPER(target_ulong, do_rdhwr_cpunum, (void))
265 267 DEF_HELPER(target_ulong, do_rdhwr_synci_step, (void))
266 268 DEF_HELPER(target_ulong, do_rdhwr_cc, (void))
... ...
target-mips/op_helper.c
  View file @0eaef5a
... ... @@ -596,59 +596,7 @@ void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
596 596 }
597 597 #endif /* TARGET_MIPS64 */
598 598  
599   -#ifdef CONFIG_USER_ONLY
600   -void do_mfc0_random (void)
601   -{
602   - cpu_abort(env, "mfc0 random\n");
603   -}
604   -
605   -void do_mfc0_count (void)
606   -{
607   - cpu_abort(env, "mfc0 count\n");
608   -}
609   -
610   -void cpu_mips_store_count(CPUState *env, uint32_t value)
611   -{
612   - cpu_abort(env, "mtc0 count\n");
613   -}
614   -
615   -void cpu_mips_store_compare(CPUState *env, uint32_t value)
616   -{
617   - cpu_abort(env, "mtc0 compare\n");
618   -}
619   -
620   -void cpu_mips_start_count(CPUState *env)
621   -{
622   - cpu_abort(env, "start count\n");
623   -}
624   -
625   -void cpu_mips_stop_count(CPUState *env)
626   -{
627   - cpu_abort(env, "stop count\n");
628   -}
629   -
630   -void cpu_mips_update_irq(CPUState *env)
631   -{
632   - cpu_abort(env, "mtc0 status / mtc0 cause\n");
633   -}
634   -
635   -void do_mtc0_status_debug(uint32_t old, uint32_t val)
636   -{
637   - cpu_abort(env, "mtc0 status debug\n");
638   -}
639   -
640   -void do_mtc0_status_irqraise_debug (void)
641   -{
642   - cpu_abort(env, "mtc0 status irqraise debug\n");
643   -}
644   -
645   -void cpu_mips_tlb_flush (CPUState *env, int flush_global)
646   -{
647   - cpu_abort(env, "mips_tlb_flush\n");
648   -}
649   -
650   -#else
651   -
  599 +#ifndef CONFIG_USER_ONLY
652 600 /* CP0 helpers */
653 601 target_ulong do_mfc0_mvpcontrol (void)
654 602 {
... ... @@ -1582,44 +1530,6 @@ target_ulong do_yield(target_ulong t0)
1582 1530 return env->CP0_YQMask;
1583 1531 }
1584 1532  
1585   -/* CP1 functions */
1586   -void fpu_handle_exception(void)
1587   -{
1588   -#ifdef CONFIG_SOFTFLOAT
1589   - int flags = get_float_exception_flags(&env->fpu->fp_status);
1590   - unsigned int cpuflags = 0, enable, cause = 0;
1591   -
1592   - enable = GET_FP_ENABLE(env->fpu->fcr31);
1593   -
1594   - /* determine current flags */
1595   - if (flags & float_flag_invalid) {
1596   - cpuflags |= FP_INVALID;
1597   - cause |= FP_INVALID & enable;
1598   - }
1599   - if (flags & float_flag_divbyzero) {
1600   - cpuflags |= FP_DIV0;
1601   - cause |= FP_DIV0 & enable;
1602   - }
1603   - if (flags & float_flag_overflow) {
1604   - cpuflags |= FP_OVERFLOW;
1605   - cause |= FP_OVERFLOW & enable;
1606   - }
1607   - if (flags & float_flag_underflow) {
1608   - cpuflags |= FP_UNDERFLOW;
1609   - cause |= FP_UNDERFLOW & enable;
1610   - }
1611   - if (flags & float_flag_inexact) {
1612   - cpuflags |= FP_INEXACT;
1613   - cause |= FP_INEXACT & enable;
1614   - }
1615   - SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
1616   - SET_FP_CAUSE(env->fpu->fcr31, cause);
1617   -#else
1618   - SET_FP_FLAGS(env->fpu->fcr31, 0);
1619   - SET_FP_CAUSE(env->fpu->fcr31, 0);
1620   -#endif
1621   -}
1622   -
1623 1533 #ifndef CONFIG_USER_ONLY
1624 1534 /* TLB management */
1625 1535 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
... ... @@ -1743,8 +1653,6 @@ void r4k_do_tlbr (void)
1743 1653 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1744 1654 }
1745 1655  
1746   -#endif /* !CONFIG_USER_ONLY */
1747   -
1748 1656 /* Specials */
1749 1657 target_ulong do_di (void)
1750 1658 {
... ... @@ -1821,6 +1729,7 @@ void do_deret (void)
1821 1729 debug_post_eret();
1822 1730 env->CP0_LLAddr = 1;
1823 1731 }
  1732 +#endif /* !CONFIG_USER_ONLY */
1824 1733  
1825 1734 target_ulong do_rdhwr_cpunum(void)
1826 1735 {
... ...
target-mips/translate.c
  View file @0eaef5a
... ... @@ -2808,8 +2808,8 @@ fail:
2808 2808 tcg_temp_free(t1);
2809 2809 }
2810 2810  
2811   -/* CP0 (MMU and control) */
2812 2811 #ifndef CONFIG_USER_ONLY
  2812 +/* CP0 (MMU and control) */
2813 2813 static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
2814 2814 {
2815 2815 TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
... ... @@ -8052,12 +8052,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
8052 8052 tcg_gen_helper_1_0(do_rdhwr_ccres, t0);
8053 8053 break;
8054 8054 case 29:
8055   -#if defined (CONFIG_USER_ONLY)
8056   - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
8057   - break;
8058   -#else
8059   - /* XXX: Some CPUs implement this in hardware. Not supported yet. */
8060   -#endif
  8055 + if (env->user_mode_only) {
  8056 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
  8057 + break;
  8058 + } else {
  8059 + /* XXX: Some CPUs implement this in hardware.
  8060 + Not supported yet. */
  8061 + }
8061 8062 default: /* Invalid */
8062 8063 MIPS_INVAL("rdhwr");
8063 8064 generate_exception(ctx, EXCP_RI);
... ... @@ -8166,20 +8167,22 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
8166 8167 case OPC_DMTC0:
8167 8168 #endif
8168 8169 #ifndef CONFIG_USER_ONLY
8169   - gen_cp0(env, ctx, op1, rt, rd);
8170   -#endif
  8170 + if (!env->user_mode_only)
  8171 + gen_cp0(env, ctx, op1, rt, rd);
  8172 +#endif /* !CONFIG_USER_ONLY */
8171 8173 break;
8172 8174 case OPC_C0_FIRST ... OPC_C0_LAST:
8173 8175 #ifndef CONFIG_USER_ONLY
8174   - gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
8175   -#endif
  8176 + if (!env->user_mode_only)
  8177 + gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
  8178 +#endif /* !CONFIG_USER_ONLY */
8176 8179 break;
8177 8180 case OPC_MFMC0:
8178 8181 #ifndef CONFIG_USER_ONLY
8179   - op2 = MASK_MFMC0(ctx->opcode);
8180   - {
  8182 + if (!env->user_mode_only) {
8181 8183 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
8182 8184  
  8185 + op2 = MASK_MFMC0(ctx->opcode);
8183 8186 switch (op2) {
8184 8187 case OPC_DMT:
8185 8188 check_insn(env, ctx, ASE_MT);
... ... @@ -8219,7 +8222,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
8219 8222 gen_store_gpr(t0, rt);
8220 8223 tcg_temp_free(t0);
8221 8224 }
8222   -#endif
  8225 +#endif /* !CONFIG_USER_ONLY */
8223 8226 break;
8224 8227 case OPC_RDPGPR:
8225 8228 check_insn(env, ctx, ISA_MIPS32R2);
... ... @@ -8474,11 +8477,10 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
8474 8477 /* Restore delay slot state from the tb context. */
8475 8478 ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
8476 8479 restore_cpu_state(env, &ctx);
8477   -#if defined(CONFIG_USER_ONLY)
8478   - ctx.mem_idx = MIPS_HFLAG_UM;
8479   -#else
8480   - ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
8481   -#endif
  8480 + if (env->user_mode_only)
  8481 + ctx.mem_idx = MIPS_HFLAG_UM;
  8482 + else
  8483 + ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
8482 8484 num_insns = 0;
8483 8485 max_insns = tb->cflags & CF_COUNT_MASK;
8484 8486 if (max_insns == 0)
... ... @@ -8759,42 +8761,42 @@ void cpu_reset (CPUMIPSState *env)
8759 8761 tlb_flush(env, 1);
8760 8762  
8761 8763 /* Minimal init */
8762   -#if !defined(CONFIG_USER_ONLY)
8763   - if (env->hflags & MIPS_HFLAG_BMASK) {
8764   - /* If the exception was raised from a delay slot,
8765   - * come back to the jump. */
8766   - env->CP0_ErrorEPC = env->active_tc.PC - 4;
  8764 +#if defined(CONFIG_USER_ONLY)
  8765 + env->user_mode_only = 1;
  8766 +#endif
  8767 + if (env->user_mode_only) {
  8768 + env->hflags = MIPS_HFLAG_UM;
8767 8769 } else {
8768   - env->CP0_ErrorEPC = env->active_tc.PC;
8769   - }
8770   - env->active_tc.PC = (int32_t)0xBFC00000;
8771   - env->CP0_Wired = 0;
8772   - /* SMP not implemented */
8773   - env->CP0_EBase = 0x80000000;
8774   - env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
8775   - /* vectored interrupts not implemented, timer on int 7,
8776   - no performance counters. */
8777   - env->CP0_IntCtl = 0xe0000000;
8778   - {
8779   - int i;
8780   -
8781   - for (i = 0; i < 7; i++) {
8782   - env->CP0_WatchLo[i] = 0;
8783   - env->CP0_WatchHi[i] = 0x80000000;
  8770 + if (env->hflags & MIPS_HFLAG_BMASK) {
  8771 + /* If the exception was raised from a delay slot,
  8772 + come back to the jump. */
  8773 + env->CP0_ErrorEPC = env->active_tc.PC - 4;
  8774 + } else {
  8775 + env->CP0_ErrorEPC = env->active_tc.PC;
  8776 + }
  8777 + env->active_tc.PC = (int32_t)0xBFC00000;
  8778 + env->CP0_Wired = 0;
  8779 + /* SMP not implemented */
  8780 + env->CP0_EBase = 0x80000000;
  8781 + env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
  8782 + /* vectored interrupts not implemented, timer on int 7,
  8783 + no performance counters. */
  8784 + env->CP0_IntCtl = 0xe0000000;
  8785 + {
  8786 + int i;
  8787 +
  8788 + for (i = 0; i < 7; i++) {
  8789 + env->CP0_WatchLo[i] = 0;
  8790 + env->CP0_WatchHi[i] = 0x80000000;
  8791 + }
  8792 + env->CP0_WatchLo[7] = 0;
  8793 + env->CP0_WatchHi[7] = 0;
8784 8794 }
8785   - env->CP0_WatchLo[7] = 0;
8786   - env->CP0_WatchHi[7] = 0;
  8795 + /* Count register increments in debug mode, EJTAG version 1 */
  8796 + env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
  8797 + env->hflags = MIPS_HFLAG_CP0;
8787 8798 }
8788   - /* Count register increments in debug mode, EJTAG version 1 */
8789   - env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
8790   -#endif
8791 8799 env->exception_index = EXCP_NONE;
8792   -#if defined(CONFIG_USER_ONLY)
8793   - env->hflags = MIPS_HFLAG_UM;
8794   - env->user_mode_only = 1;
8795   -#else
8796   - env->hflags = MIPS_HFLAG_CP0;
8797   -#endif
8798 8800 cpu_mips_register(env, env->cpu_model);
8799 8801 }
8800 8802  
... ...
target-mips/translate_init.c
  View file @0eaef5a
... ... @@ -439,7 +439,6 @@ void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
439 439 }
440 440 }
441 441  
442   -#ifndef CONFIG_USER_ONLY
443 442 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
444 443 {
445 444 env->tlb->nb_tlb = 1;
... ... @@ -485,21 +484,20 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
485 484 env->CP0_Random = env->tlb->nb_tlb - 1;
486 485 env->tlb->tlb_in_use = env->tlb->nb_tlb;
487 486 }
488   -#endif /* CONFIG_USER_ONLY */
489 487  
490 488 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
491 489 {
492 490 env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext));
493 491  
494 492 env->fpu->fcr0 = def->CP1_fcr0;
495   -#ifdef CONFIG_USER_ONLY
496   - if (env->CP0_Config1 & (1 << CP0C1_FP))
497   - env->hflags |= MIPS_HFLAG_FPU;
  493 + if (env->user_mode_only) {
  494 + if (env->CP0_Config1 & (1 << CP0C1_FP))
  495 + env->hflags |= MIPS_HFLAG_FPU;
498 496 #ifdef TARGET_MIPS64
499   - if (env->fpu->fcr0 & (1 << FCR0_F64))
500   - env->hflags |= MIPS_HFLAG_F64;
501   -#endif
  497 + if (env->fpu->fcr0 & (1 << FCR0_F64))
  498 + env->hflags |= MIPS_HFLAG_F64;
502 499 #endif
  500 + }
503 501 }
504 502  
505 503 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
... ... @@ -512,15 +510,15 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
512 510 implemented, 5 TCs implemented. */
513 511 env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
514 512 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
515   -#ifndef CONFIG_USER_ONLY
516   - /* Usermode has no TLB support */
517   - (env->tlb->nb_tlb << CP0MVPC0_PTLBE) |
518   -#endif
519 513 // TODO: actually do 2 VPEs.
520 514 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
521 515 // (0x04 << CP0MVPC0_PTC);
522 516 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
523 517 (0x04 << CP0MVPC0_PTC);
  518 + /* Usermode has no TLB support */
  519 + if (!env->user_mode_only)
  520 + env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
  521 +
524 522 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
525 523 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
526 524 env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
... ... @@ -568,9 +566,8 @@ static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
568 566 env->CP0_SRSConf4 = def->CP0_SRSConf4;
569 567 env->insn_flags = def->insn_flags;
570 568  
571   -#ifndef CONFIG_USER_ONLY
572   - mmu_init(env, def);
573   -#endif
  569 + if (!env->user_mode_only)
  570 + mmu_init(env, def);
574 571 fpu_init(env, def);
575 572 mvp_init(env, def);
576 573 return 0;
... ...