gwj / at91sam9263 · Commits

Commit d26bc2118e99702eb8c1bb240786bcadd7fa21ac

Authored by ths
1 parent 5850586c

Clean out the N32 macros from target-mips, and introduce MIPS ABI specific 

defines for linux-user.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3556 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 13 changed files with 75 additions and 73 deletions
configure
  View file @d26bc21
... ... @@ -1099,16 +1099,18 @@ elif test "$target_cpu" = "mips" -o "$target_cpu" = "mipsel" ; then
1099 1099 echo "TARGET_ARCH=mips" >> $config_mak
1100 1100 echo "#define TARGET_ARCH \"mips\"" >> $config_h
1101 1101 echo "#define TARGET_MIPS 1" >> $config_h
  1102 + echo "#define TARGET_ABI_MIPSO32 1" >> $config_h
1102 1103 elif test "$target_cpu" = "mipsn32" -o "$target_cpu" = "mipsn32el" ; then
1103 1104 echo "TARGET_ARCH=mipsn32" >> $config_mak
1104 1105 echo "#define TARGET_ARCH \"mipsn32\"" >> $config_h
1105 1106 echo "#define TARGET_MIPS 1" >> $config_h
1106   - echo "#define TARGET_MIPSN32 1" >> $config_h
  1107 + echo "#define TARGET_ABI_MIPSN32 1" >> $config_h
1107 1108 elif test "$target_cpu" = "mips64" -o "$target_cpu" = "mips64el" ; then
1108 1109 echo "TARGET_ARCH=mips64" >> $config_mak
1109 1110 echo "#define TARGET_ARCH \"mips64\"" >> $config_h
1110 1111 echo "#define TARGET_MIPS 1" >> $config_h
1111 1112 echo "#define TARGET_MIPS64 1" >> $config_h
  1113 + echo "#define TARGET_ABI_MIPSN64 1" >> $config_h
1112 1114 elif test "$target_cpu" = "cris" ; then
1113 1115 echo "TARGET_ARCH=cris" >> $config_mak
1114 1116 echo "#define TARGET_ARCH \"cris\"" >> $config_h
... ...
linux-user/main.c
  View file @d26bc21
... ... @@ -2225,7 +2225,7 @@ int main(int argc, char **argv)
2225 2225  
2226 2226 /* Choose and initialise CPU */
2227 2227 if (cpu_model == NULL)
2228   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  2228 +#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2229 2229 cpu_model = "20Kc";
2230 2230 #else
2231 2231 cpu_model = "24Kf";
... ...
linux-user/signal.c
  View file @d26bc21
... ... @@ -1939,7 +1939,7 @@ void sparc64_get_context(CPUSPARCState *env)
1939 1939 force_sig(SIGSEGV);
1940 1940 }
1941 1941 #endif
1942   -#elif defined(TARGET_MIPS64)
  1942 +#elif defined(TARGET_ABI_MIPSN64)
1943 1943  
1944 1944 # warning signal handling not implemented
1945 1945  
... ... @@ -1968,7 +1968,7 @@ long do_rt_sigreturn(CPUState *env)
1968 1968 return -ENOSYS;
1969 1969 }
1970 1970  
1971   -#elif defined(TARGET_MIPSN32)
  1971 +#elif defined(TARGET_ABI_MIPSN32)
1972 1972  
1973 1973 # warning signal handling not implemented
1974 1974  
... ... @@ -1997,7 +1997,7 @@ long do_rt_sigreturn(CPUState *env)
1997 1997 return -ENOSYS;
1998 1998 }
1999 1999  
2000   -#elif defined(TARGET_MIPS)
  2000 +#elif defined(TARGET_ABI_MIPSO32)
2001 2001  
2002 2002 struct target_sigcontext {
2003 2003 uint32_t sc_regmask; /* Unused */
... ...
linux-user/syscall_defs.h
  View file @d26bc21
... ... @@ -307,8 +307,8 @@ int do_sigaction(int sig, const struct target_sigaction *act,
307 307 #define TARGET_SA_NODEFER 0x40000000
308 308 #define TARGET_SA_RESTART 0x10000000
309 309 #define TARGET_SA_RESETHAND 0x80000000
310   -#if !defined(TARGET_MIPSN32) && !defined(TARGET_MIPS64)
311   -#define TARGET_SA_RESTORER 0x04000000 /* Only for o32 */
  310 +#if !defined(TARGET_ABI_MIPSN32) && !defined(TARGET_ABI_MIPSN64)
  311 +#define TARGET_SA_RESTORER 0x04000000 /* Only for O32 */
312 312 #endif
313 313 #else
314 314 #define TARGET_SA_NOCLDSTOP 0x00000001
... ... @@ -450,7 +450,7 @@ int do_sigaction(int sig, const struct target_sigaction *act,
450 450  
451 451 struct target_sigaction {
452 452 uint32_t sa_flags;
453   -#if defined(TARGET_MIPSN32)
  453 +#if defined(TARGET_ABI_MIPSN32)
454 454 uint32_t _sa_handler;
455 455 #else
456 456 abi_ulong _sa_handler;
... ... @@ -1194,7 +1194,7 @@ struct target_stat64 {
1194 1194 unsigned long long st_ino;
1195 1195 } __attribute__((packed));
1196 1196  
1197   -#elif defined(TARGET_MIPS64)
  1197 +#elif defined(TARGET_ABI_MIPSN64)
1198 1198  
1199 1199 /* The memory layout is the same as of struct stat64 of the 32-bit kernel. */
1200 1200 struct target_stat {
... ... @@ -1233,7 +1233,7 @@ struct target_stat {
1233 1233 abi_ulong st_blocks;
1234 1234 };
1235 1235  
1236   -#elif defined(TARGET_MIPSN32)
  1236 +#elif defined(TARGET_ABI_MIPSN32)
1237 1237  
1238 1238 struct target_stat {
1239 1239 unsigned st_dev;
... ... @@ -1304,7 +1304,7 @@ struct target_stat64 {
1304 1304 int st_blocks;
1305 1305 };
1306 1306  
1307   -#elif defined(TARGET_MIPS)
  1307 +#elif defined(TARGET_ABI_MIPSO32)
1308 1308  
1309 1309 struct target_stat {
1310 1310 unsigned st_dev;
... ... @@ -1486,7 +1486,7 @@ typedef struct {
1486 1486 } target_fsid_t;
1487 1487  
1488 1488 #ifdef TARGET_MIPS
1489   -#ifdef TARGET_MIPSN32
  1489 +#ifdef TARGET_ABI_MIPSN32
1490 1490 struct target_statfs {
1491 1491 int32_t f_type;
1492 1492 int32_t f_bsize;
... ...
target-mips/exec.h
  View file @d26bc21
... ... @@ -56,7 +56,7 @@ register target_ulong T2 asm(AREG3);
56 56 #include "softmmu_exec.h"
57 57 #endif /* !defined(CONFIG_USER_ONLY) */
58 58  
59   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  59 +#if defined(TARGET_MIPS64)
60 60 #if TARGET_LONG_BITS > HOST_LONG_BITS
61 61 void do_dsll (void);
62 62 void do_dsll32 (void);
... ... @@ -86,7 +86,7 @@ void do_maddu (void);
86 86 void do_msub (void);
87 87 void do_msubu (void);
88 88 #endif
89   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  89 +#if defined(TARGET_MIPS64)
90 90 void do_ddiv (void);
91 91 #if TARGET_LONG_BITS > HOST_LONG_BITS
92 92 void do_ddivu (void);
... ... @@ -236,7 +236,7 @@ static always_inline void compute_hflags(CPUState *env)
236 236 !(env->hflags & MIPS_HFLAG_DM)) {
237 237 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
238 238 }
239   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  239 +#if defined(TARGET_MIPS64)
240 240 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
241 241 (env->CP0_Status & (1 << CP0St_PX)) ||
242 242 (env->CP0_Status & (1 << CP0St_UX)))
... ...
target-mips/helper.c
  View file @d26bc21
... ... @@ -76,7 +76,7 @@ int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
76 76 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
77 77 target_ulong tag = address & ~mask;
78 78 target_ulong VPN = tlb->VPN & ~mask;
79   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  79 +#if defined(TARGET_MIPS64)
80 80 tag &= env->SEGMask;
81 81 #endif
82 82  
... ... @@ -108,7 +108,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
108 108 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
109 109 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
110 110 int kernel_mode = !user_mode && !supervisor_mode;
111   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  111 +#if defined(TARGET_MIPS64)
112 112 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
113 113 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
114 114 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
... ... @@ -130,7 +130,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
130 130 } else {
131 131 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
132 132 }
133   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  133 +#if defined(TARGET_MIPS64)
134 134 } else if (address < 0x4000000000000000ULL) {
135 135 /* xuseg */
136 136 if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
... ... @@ -305,7 +305,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
305 305 ((address >> 9) & 0x007ffff0);
306 306 env->CP0_EntryHi =
307 307 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
308   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  308 +#if defined(TARGET_MIPS64)
309 309 env->CP0_EntryHi &= env->SEGMask;
310 310 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
311 311 ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
... ... @@ -425,7 +425,7 @@ void do_interrupt (CPUState *env)
425 425 case EXCP_TLBL:
426 426 cause = 2;
427 427 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
428   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  428 +#if defined(TARGET_MIPS64)
429 429 int R = env->CP0_BadVAddr >> 62;
430 430 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
431 431 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
... ... @@ -473,7 +473,7 @@ void do_interrupt (CPUState *env)
473 473 case EXCP_TLBS:
474 474 cause = 3;
475 475 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
476   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  476 +#if defined(TARGET_MIPS64)
477 477 int R = env->CP0_BadVAddr >> 62;
478 478 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
479 479 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
... ... @@ -559,7 +559,7 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
559 559 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
560 560 if (tlb->V0) {
561 561 addr = tlb->VPN & ~mask;
562   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  562 +#if defined(TARGET_MIPS64)
563 563 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
564 564 addr |= 0x3FFFFF0000000000ULL;
565 565 }
... ... @@ -572,7 +572,7 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
572 572 }
573 573 if (tlb->V1) {
574 574 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
575   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  575 +#if defined(TARGET_MIPS64)
576 576 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
577 577 addr |= 0x3FFFFF0000000000ULL;
578 578 }
... ...
target-mips/mips-defs.h
  View file @d26bc21
... ... @@ -8,7 +8,7 @@
8 8 #define TARGET_PAGE_BITS 12
9 9 #define MIPS_TLB_MAX 128
10 10  
11   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  11 +#if defined(TARGET_MIPS64)
12 12 #define TARGET_LONG_BITS 64
13 13 #else
14 14 #define TARGET_LONG_BITS 32
... ...
target-mips/op.c
  View file @d26bc21
... ... @@ -301,7 +301,7 @@ void op_addr_add (void)
301 301 /* For compatibility with 32-bit code, data reference in user mode
302 302 with Status_UX = 0 should be casted to 32-bit and sign extended.
303 303 See the MIPS64 PRA manual, section 4.10. */
304   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  304 +#if defined(TARGET_MIPS64)
305 305 if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
306 306 !(env->CP0_Status & (1 << CP0St_UX)))
307 307 T0 = (int64_t)(int32_t)(T0 + T1);
... ... @@ -384,7 +384,7 @@ void op_divu (void)
384 384 RETURN();
385 385 }
386 386  
387   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  387 +#if defined(TARGET_MIPS64)
388 388 /* Arithmetic */
389 389 void op_dadd (void)
390 390 {
... ... @@ -453,7 +453,7 @@ void op_ddivu (void)
453 453 RETURN();
454 454 }
455 455 #endif
456   -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
  456 +#endif /* TARGET_MIPS64 */
457 457  
458 458 /* Logical */
459 459 void op_and (void)
... ... @@ -552,7 +552,7 @@ void op_clz (void)
552 552 RETURN();
553 553 }
554 554  
555   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  555 +#if defined(TARGET_MIPS64)
556 556  
557 557 #if TARGET_LONG_BITS > HOST_LONG_BITS
558 558 /* Those might call libgcc functions. */
... ... @@ -743,7 +743,7 @@ void op_dclz (void)
743 743 RETURN();
744 744 }
745 745 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
746   -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
  746 +#endif /* TARGET_MIPS64 */
747 747  
748 748 /* 64 bits arithmetic */
749 749 #if TARGET_LONG_BITS > HOST_LONG_BITS
... ... @@ -846,7 +846,7 @@ void op_msubu (void)
846 846 }
847 847 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
848 848  
849   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  849 +#if defined(TARGET_MIPS64)
850 850 void op_dmult (void)
851 851 {
852 852 CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
... ... @@ -950,7 +950,7 @@ void op_save_btarget (void)
950 950 RETURN();
951 951 }
952 952  
953   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  953 +#if defined(TARGET_MIPS64)
954 954 void op_save_btarget64 (void)
955 955 {
956 956 env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
... ... @@ -1784,7 +1784,7 @@ void op_mtc0_entryhi (void)
1784 1784  
1785 1785 /* 1k pages not implemented */
1786 1786 val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1787   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  1787 +#if defined(TARGET_MIPS64)
1788 1788 val &= env->SEGMask;
1789 1789 #endif
1790 1790 old = env->CP0_EntryHi;
... ... @@ -2011,7 +2011,7 @@ void op_mtc0_desave (void)
2011 2011 RETURN();
2012 2012 }
2013 2013  
2014   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  2014 +#if defined(TARGET_MIPS64)
2015 2015 void op_dmfc0_yqmask (void)
2016 2016 {
2017 2017 T0 = env->CP0_YQMask;
... ... @@ -2125,7 +2125,7 @@ void op_dmfc0_errorepc (void)
2125 2125 T0 = env->CP0_ErrorEPC;
2126 2126 RETURN();
2127 2127 }
2128   -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
  2128 +#endif /* TARGET_MIPS64 */
2129 2129  
2130 2130 /* MIPS MT functions */
2131 2131 void op_mftgpr(void)
... ... @@ -3039,7 +3039,7 @@ void op_save_pc (void)
3039 3039 RETURN();
3040 3040 }
3041 3041  
3042   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  3042 +#if defined(TARGET_MIPS64)
3043 3043 void op_save_pc64 (void)
3044 3044 {
3045 3045 env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
... ... @@ -3111,7 +3111,7 @@ void op_wsbh(void)
3111 3111 RETURN();
3112 3112 }
3113 3113  
3114   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  3114 +#if defined(TARGET_MIPS64)
3115 3115 void op_dext(void)
3116 3116 {
3117 3117 unsigned int pos = PARAM1;
... ...
target-mips/op_helper.c
  View file @d26bc21
... ... @@ -68,7 +68,7 @@ void do_raise_exception_direct (uint32_t exception)
68 68 do_raise_exception_direct_err (exception, 0);
69 69 }
70 70  
71   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  71 +#if defined(TARGET_MIPS64)
72 72 #if TARGET_LONG_BITS > HOST_LONG_BITS
73 73 /* Those might call libgcc functions. */
74 74 void do_dsll (void)
... ... @@ -159,7 +159,7 @@ void do_dclz (void)
159 159 }
160 160  
161 161 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
162   -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
  162 +#endif /* TARGET_MIPS64 */
163 163  
164 164 /* 64 bits arithmetic for 32 bits hosts */
165 165 #if TARGET_LONG_BITS > HOST_LONG_BITS
... ... @@ -228,7 +228,7 @@ void do_div (void)
228 228 }
229 229 #endif
230 230  
231   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  231 +#if defined(TARGET_MIPS64)
232 232 void do_ddiv (void)
233 233 {
234 234 if (T1 != 0) {
... ... @@ -247,7 +247,7 @@ void do_ddivu (void)
247 247 }
248 248 }
249 249 #endif
250   -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
  250 +#endif /* TARGET_MIPS64 */
251 251  
252 252 #if defined(CONFIG_USER_ONLY)
253 253 void do_mfc0_random (void)
... ... @@ -392,7 +392,7 @@ static void r4k_fill_tlb (int idx)
392 392 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
393 393 tlb = &env->tlb->mmu.r4k.tlb[idx];
394 394 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
395   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  395 +#if defined(TARGET_MIPS64)
396 396 tlb->VPN &= env->SEGMask;
397 397 #endif
398 398 tlb->ASID = env->CP0_EntryHi & 0xFF;
... ...
target-mips/op_mem.c
  View file @d26bc21
... ... @@ -190,7 +190,7 @@ void glue(op_sc, MEMSUFFIX) (void)
190 190 RETURN();
191 191 }
192 192  
193   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  193 +#if defined(TARGET_MIPS64)
194 194 void glue(op_ld, MEMSUFFIX) (void)
195 195 {
196 196 T0 = glue(ldq, MEMSUFFIX)(T0);
... ... @@ -381,7 +381,7 @@ void glue(op_scd, MEMSUFFIX) (void)
381 381 }
382 382 RETURN();
383 383 }
384   -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
  384 +#endif /* TARGET_MIPS64 */
385 385  
386 386 void glue(op_lwc1, MEMSUFFIX) (void)
387 387 {
... ...
target-mips/op_template.c
  View file @d26bc21
... ... @@ -82,7 +82,7 @@ SET_RESET(T2, _T2)
82 82  
83 83 #undef SET_RESET
84 84  
85   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  85 +#if defined(TARGET_MIPS64)
86 86 #define SET64(treg, tregname) \
87 87 void glue(op_set64, tregname)(void) \
88 88 { \
... ...
target-mips/translate.c
  View file @d26bc21
... ... @@ -590,7 +590,7 @@ do { \
590 590 } \
591 591 } while (0)
592 592  
593   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  593 +#if defined(TARGET_MIPS64)
594 594 #define GEN_LOAD_IMM_TN(Tn, Imm) \
595 595 do { \
596 596 if (Imm == 0) { \
... ... @@ -638,7 +638,7 @@ do { \
638 638  
639 639 static always_inline void gen_save_pc(target_ulong pc)
640 640 {
641   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  641 +#if defined(TARGET_MIPS64)
642 642 if (pc == (int32_t)pc) {
643 643 gen_op_save_pc(pc);
644 644 } else {
... ... @@ -651,7 +651,7 @@ static always_inline void gen_save_pc(target_ulong pc)
651 651  
652 652 static always_inline void gen_save_btarget(target_ulong btarget)
653 653 {
654   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  654 +#if defined(TARGET_MIPS64)
655 655 if (btarget == (int32_t)btarget) {
656 656 gen_op_save_btarget(btarget);
657 657 } else {
... ... @@ -802,7 +802,7 @@ static GenOpFunc *gen_op_s##width[] = { \
802 802 }
803 803 #endif
804 804  
805   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  805 +#if defined(TARGET_MIPS64)
806 806 OP_LD_TABLE(d);
807 807 OP_LD_TABLE(dl);
808 808 OP_LD_TABLE(dr);
... ... @@ -852,7 +852,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
852 852 /* Don't do NOP if destination is zero: we must perform the actual
853 853 memory access. */
854 854 switch (opc) {
855   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  855 +#if defined(TARGET_MIPS64)
856 856 case OPC_LWU:
857 857 op_ldst(lwu);
858 858 GEN_STORE_TN_REG(rt, T0);
... ... @@ -1048,7 +1048,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1048 1048 switch (opc) {
1049 1049 case OPC_ADDI:
1050 1050 case OPC_ADDIU:
1051   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  1051 +#if defined(TARGET_MIPS64)
1052 1052 case OPC_DADDI:
1053 1053 case OPC_DADDIU:
1054 1054 #endif
... ... @@ -1068,7 +1068,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1068 1068 case OPC_SLL:
1069 1069 case OPC_SRA:
1070 1070 case OPC_SRL:
1071   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  1071 +#if defined(TARGET_MIPS64)
1072 1072 case OPC_DSLL:
1073 1073 case OPC_DSRA:
1074 1074 case OPC_DSRL:
... ... @@ -1091,7 +1091,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1091 1091 gen_op_add();
1092 1092 opn = "addiu";
1093 1093 break;
1094   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  1094 +#if defined(TARGET_MIPS64)
1095 1095 case OPC_DADDI:
1096 1096 save_cpu_state(ctx, 1);
1097 1097 gen_op_daddo();
... ... @@ -1155,7 +1155,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1155 1155 break;
1156 1156 }
1157 1157 break;
1158   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  1158 +#if defined(TARGET_MIPS64)
1159 1159 case OPC_DSLL:
1160 1160 gen_op_dsll();
1161 1161 opn = "dsll";
... ... @@ -1260,7 +1260,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1260 1260 gen_op_sub();
1261 1261 opn = "subu";
1262 1262 break;
1263   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  1263 +#if defined(TARGET_MIPS64)
1264 1264 case OPC_DADD:
1265 1265 save_cpu_state(ctx, 1);
1266 1266 gen_op_daddo();
... ... @@ -1346,7 +1346,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1346 1346 break;
1347 1347 }
1348 1348 break;
1349   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  1349 +#if defined(TARGET_MIPS64)
1350 1350 case OPC_DSLLV:
1351 1351 gen_op_dsllv();
1352 1352 opn = "dsllv";
... ... @@ -1451,7 +1451,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1451 1451 gen_op_multu();
1452 1452 opn = "multu";
1453 1453 break;
1454   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  1454 +#if defined(TARGET_MIPS64)
1455 1455 case OPC_DDIV:
1456 1456 gen_op_ddiv();
1457 1457 opn = "ddiv";
... ... @@ -1512,7 +1512,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
1512 1512 gen_op_clz();
1513 1513 opn = "clz";
1514 1514 break;
1515   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  1515 +#if defined(TARGET_MIPS64)
1516 1516 case OPC_DCLO:
1517 1517 gen_op_dclo();
1518 1518 opn = "dclo";
... ... @@ -2319,7 +2319,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2319 2319 case 20:
2320 2320 switch (sel) {
2321 2321 case 0:
2322   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  2322 +#if defined(TARGET_MIPS64)
2323 2323 check_insn(env, ctx, ISA_MIPS3);
2324 2324 gen_op_mfc0_xcontext();
2325 2325 rn = "XContext";
... ... @@ -2901,7 +2901,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2901 2901 case 20:
2902 2902 switch (sel) {
2903 2903 case 0:
2904   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  2904 +#if defined(TARGET_MIPS64)
2905 2905 check_insn(env, ctx, ISA_MIPS3);
2906 2906 gen_op_mtc0_xcontext();
2907 2907 rn = "XContext";
... ... @@ -3111,7 +3111,7 @@ die:
3111 3111 generate_exception(ctx, EXCP_RI);
3112 3112 }
3113 3113  
3114   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  3114 +#if defined(TARGET_MIPS64)
3115 3115 static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3116 3116 {
3117 3117 const char *rn = "invalid";
... ... @@ -4254,7 +4254,7 @@ die:
4254 4254 #endif
4255 4255 generate_exception(ctx, EXCP_RI);
4256 4256 }
4257   -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
  4257 +#endif /* TARGET_MIPS64 */
4258 4258  
4259 4259 static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4260 4260 int u, int sel, int h)
... ... @@ -4604,7 +4604,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
4604 4604 gen_mtc0(env, ctx, rd, ctx->opcode & 0x7);
4605 4605 opn = "mtc0";
4606 4606 break;
4607   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  4607 +#if defined(TARGET_MIPS64)
4608 4608 case OPC_DMFC0:
4609 4609 check_insn(env, ctx, ISA_MIPS3);
4610 4610 if (rt == 0) {
... ... @@ -5877,7 +5877,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
5877 5877 /* MIPS16 extension to MIPS32 */
5878 5878 /* SmartMIPS extension to MIPS32 */
5879 5879  
5880   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  5880 +#if defined(TARGET_MIPS64)
5881 5881  
5882 5882 /* MDMX extension to MIPS64 */
5883 5883  
... ... @@ -5987,7 +5987,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
5987 5987 }
5988 5988 break;
5989 5989  
5990   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  5990 +#if defined(TARGET_MIPS64)
5991 5991 /* MIPS64 specific opcodes */
5992 5992 case OPC_DSLL:
5993 5993 case OPC_DSRL ... OPC_DSRA:
... ... @@ -6043,7 +6043,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6043 6043 }
6044 6044 /* Treat as NOP. */
6045 6045 break;
6046   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  6046 +#if defined(TARGET_MIPS64)
6047 6047 case OPC_DCLZ ... OPC_DCLO:
6048 6048 check_insn(env, ctx, ISA_MIPS64);
6049 6049 check_mips_64(ctx);
... ... @@ -6130,7 +6130,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6130 6130 gen_op_yield();
6131 6131 GEN_STORE_TN_REG(rd, T0);
6132 6132 break;
6133   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  6133 +#if defined(TARGET_MIPS64)
6134 6134 case OPC_DEXTM ... OPC_DEXT:
6135 6135 case OPC_DINSM ... OPC_DINS:
6136 6136 check_insn(env, ctx, ISA_MIPS64R2);
... ... @@ -6192,7 +6192,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6192 6192 case OPC_MTC0:
6193 6193 case OPC_MFTR:
6194 6194 case OPC_MTTR:
6195   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  6195 +#if defined(TARGET_MIPS64)
6196 6196 case OPC_DMFC0:
6197 6197 case OPC_DMTC0:
6198 6198 #endif
... ... @@ -6313,7 +6313,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6313 6313 case OPC_CTC1:
6314 6314 gen_cp1(ctx, op1, rt, rd);
6315 6315 break;
6316   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  6316 +#if defined(TARGET_MIPS64)
6317 6317 case OPC_DMFC1:
6318 6318 case OPC_DMTC1:
6319 6319 check_insn(env, ctx, ISA_MIPS3);
... ... @@ -6398,7 +6398,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6398 6398 }
6399 6399 break;
6400 6400  
6401   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  6401 +#if defined(TARGET_MIPS64)
6402 6402 /* MIPS64 opcodes */
6403 6403 case OPC_LWU:
6404 6404 case OPC_LDL ... OPC_LDR:
... ... @@ -6665,7 +6665,7 @@ void dump_fpu (CPUState *env)
6665 6665 }
6666 6666 }
6667 6667  
6668   -#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
  6668 +#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6669 6669 /* Debug help: The architecture requires 32bit code to maintain proper
6670 6670 sign-extened values on 64bit machines. */
6671 6671  
... ... @@ -6720,7 +6720,7 @@ void cpu_dump_state (CPUState *env, FILE *f,
6720 6720 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
6721 6721 if (env->hflags & MIPS_HFLAG_FPU)
6722 6722 fpu_dump_state(env, f, cpu_fprintf, flags);
6723   -#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
  6723 +#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6724 6724 cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
6725 6725 #endif
6726 6726 }
... ...
target-mips/translate_init.c
  View file @d26bc21
... ... @@ -201,7 +201,7 @@ static mips_def_t mips_defs[] =
201 201 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
202 202 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
203 203 },
204   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  204 +#if defined(TARGET_MIPS64)
205 205 {
206 206 .name = "R4000",
207 207 .CP0_PRid = 0x00000400,
... ... @@ -437,7 +437,7 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
437 437 env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
438 438 env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
439 439 env->CP0_SRSCtl = def->CP0_SRSCtl;
440   -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
  440 +#if defined(TARGET_MIPS64)
441 441 if (def->insn_flags & ISA_MIPS3)
442 442 {
443 443 env->hflags |= MIPS_HFLAG_64;
... ...