gwj / at91sam9263 · Commits

Commit 3953d7868768c179440e8302e536b436171205cc

Authored by ths
1 parent 1698b741

Move mips CPU specific initialization to translate_init.c. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2522 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 61 additions and 40 deletions
target-mips/mips-defs.h
  View file @3953d78
... ... @@ -15,43 +15,6 @@
15 15 #define MIPS_USES_R4K_TLB
16 16 #define MIPS_TLB_NB 16
17 17 #define MIPS_TLB_MAX 128
18   -/* Define a implementation number of 1.
19   - * Define a major version 1, minor version 0.
20   - */
21   -#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
22   - /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
23   - uncached coherency */
24   -#define MIPS_CONFIG0_1 \
25   - ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
26   - (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
27   - (0x2 << CP0C0_K0))
28   -#ifdef TARGET_WORDS_BIGENDIAN
29   -#define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
30   -#else
31   -#define MIPS_CONFIG0 MIPS_CONFIG0_1
32   -#endif
33   -/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
34   - 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
35   - no coprocessor2 attached, no MDMX support attached,
36   - no performance counters, watch registers present,
37   - no code compression, EJTAG present, no FPU */
38   -#define MIPS_CONFIG1 \
39   -((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \
40   - (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
41   - (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
42   - (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
43   - (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
44   - (0 << CP0C1_FP))
45   -/* Have config3, no tertiary/secondary caches implemented */
46   -#define MIPS_CONFIG2 \
47   -((1 << CP0C2_M))
48   -/* No config4, no DSP ASE, no large physaddr,
49   - no external interrupt controller, no vectored interupts,
50   - no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
51   -#define MIPS_CONFIG3 \
52   -((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
53   - (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
54   - (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
55 18  
56 19 #ifdef MIPS_HAS_MIPS64
57 20 #define TARGET_LONG_BITS 64
... ...
target-mips/translate.c
  View file @3953d78
... ... @@ -5292,8 +5292,6 @@ void cpu_reset (CPUMIPSState *env)
5292 5292 env->CP0_Wired = 0;
5293 5293 /* SMP not implemented */
5294 5294 env->CP0_EBase = 0x80000000;
5295   - env->CP0_Config2 = MIPS_CONFIG2;
5296   - env->CP0_Config3 = MIPS_CONFIG3;
5297 5295 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
5298 5296 env->CP0_WatchLo = 0;
5299 5297 env->hflags = MIPS_HFLAG_ERL;
... ... @@ -5305,7 +5303,6 @@ void cpu_reset (CPUMIPSState *env)
5305 5303 env->hflags |= MIPS_HFLAG_UM;
5306 5304 env->user_mode_only = 1;
5307 5305 #endif
5308   - env->fcr0 = MIPS_FCR0;
5309 5306 /* XXX some guesswork here, values are CPU specific */
5310 5307 env->SYNCI_Step = 16;
5311 5308 env->CCRes = 2;
... ...
target-mips/translate_init.c
  View file @3953d78
... ... @@ -19,11 +19,53 @@
19 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 20 */
21 21  
  22 +/* CPU / CPU family specific config register values. */
  23 +
  24 +/* Have config1, is MIPS32R1, uses TLB, no virtual icache,
  25 + uncached coherency */
  26 +#define MIPS_CONFIG0 \
  27 + ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
  28 + (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
  29 + (0x2 << CP0C0_K0))
  30 +
  31 +/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
  32 + 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
  33 + no coprocessor2 attached, no MDMX support attached,
  34 + no performance counters, watch registers present,
  35 + no code compression, EJTAG present, no FPU */
  36 +#define MIPS_CONFIG1 \
  37 +((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \
  38 + (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
  39 + (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
  40 + (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
  41 + (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
  42 + (0 << CP0C1_FP))
  43 +
  44 +/* Have config3, no tertiary/secondary caches implemented */
  45 +#define MIPS_CONFIG2 \
  46 +((1 << CP0C2_M))
  47 +
  48 +/* No config4, no DSP ASE, no large physaddr,
  49 + no external interrupt controller, no vectored interupts,
  50 + no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
  51 +#define MIPS_CONFIG3 \
  52 +((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
  53 + (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
  54 + (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
  55 +
  56 +/* Define a implementation number of 1.
  57 + Define a major version 1, minor version 0. */
  58 +#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
  59 +
  60 +
22 61 struct mips_def_t {
23 62 const unsigned char *name;
24 63 int32_t CP0_PRid;
25 64 int32_t CP0_Config0;
26 65 int32_t CP0_Config1;
  66 + int32_t CP0_Config2;
  67 + int32_t CP0_Config3;
  68 + int32_t CP1_fcr0;
27 69 };
28 70  
29 71 /*****************************************************************************/
... ... @@ -36,18 +78,27 @@ static mips_def_t mips_defs[] =
36 78 .CP0_PRid = 0x00018000,
37 79 .CP0_Config0 = MIPS_CONFIG0,
38 80 .CP0_Config1 = MIPS_CONFIG1,
  81 + .CP0_Config2 = MIPS_CONFIG2,
  82 + .CP0_Config3 = MIPS_CONFIG3,
  83 + .CP1_fcr0 = MIPS_FCR0,
39 84 },
40 85 {
41 86 .name = "4KEc",
42 87 .CP0_PRid = 0x00018400,
43 88 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
44 89 .CP0_Config1 = MIPS_CONFIG1,
  90 + .CP0_Config2 = MIPS_CONFIG2,
  91 + .CP0_Config3 = MIPS_CONFIG3,
  92 + .CP1_fcr0 = MIPS_FCR0,
45 93 },
46 94 {
47 95 .name = "24Kf",
48 96 .CP0_PRid = 0x00019300,
49 97 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
50 98 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
  99 + .CP0_Config2 = MIPS_CONFIG2,
  100 + .CP0_Config3 = MIPS_CONFIG3,
  101 + .CP1_fcr0 = MIPS_FCR0,
51 102 },
52 103 #else
53 104 {
... ... @@ -55,6 +106,9 @@ static mips_def_t mips_defs[] =
55 106 .CP0_PRid = 0x00000400,
56 107 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
57 108 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
  109 + .CP0_Config2 = MIPS_CONFIG2,
  110 + .CP0_Config3 = MIPS_CONFIG3,
  111 + .CP1_fcr0 = MIPS_FCR0,
58 112 },
59 113 #endif
60 114 };
... ... @@ -91,7 +145,14 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
91 145 if (!def)
92 146 cpu_abort(env, "Unable to find MIPS CPU definition\n");
93 147 env->CP0_PRid = def->CP0_PRid;
  148 +#ifdef TARGET_WORDS_BIGENDIAN
  149 + env->CP0_Config0 = def->CP0_Config0 | (1 << CP0C0_BE);
  150 +#else
94 151 env->CP0_Config0 = def->CP0_Config0;
  152 +#endif
95 153 env->CP0_Config1 = def->CP0_Config1;
  154 + env->CP0_Config2 = def->CP0_Config2;
  155 + env->CP0_Config3 = def->CP0_Config3;
  156 + env->fcr0 = def->CP1_fcr0;
96 157 return 0;
97 158 }
... ...