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/*
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* QEMU TCX Frame buffer
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*
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* Copyright ( c ) 2003 - 2005 Fabrice Bellard
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*
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* Permission is hereby granted , free of charge , to any person obtaining a copy
* of this software and associated documentation files ( the "Software" ), to deal
* in the Software without restriction , including without limitation the rights
* to use , copy , modify , merge , publish , distribute , sublicense , and / or sell
* copies of the Software , and to permit persons to whom the Software is
* furnished to do so , subject to the following conditions :
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software .
*
* THE SOFTWARE IS PROVIDED "AS IS" , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR
* IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY ,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM , DAMAGES OR OTHER
* LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , ARISING FROM ,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE .
*/
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# include "sun4m.h"
# include "console.h"
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# include "pixel_ops.h"
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# include "sysbus.h"
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# include "qdev-addr.h"
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# define MAXX 1024
# define MAXY 768
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# define TCX_DAC_NREGS 16
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# define TCX_THC_NREGS_8 0x081c
# define TCX_THC_NREGS_24 0x1000
# define TCX_TEC_NREGS 0x1000
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typedef struct TCXState {
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SysBusDevice busdev ;
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target_phys_addr_t addr ;
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DisplayState * ds ;
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uint8_t * vram ;
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uint32_t * vram24 , * cplane ;
ram_addr_t vram_offset , vram24_offset , cplane_offset ;
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uint32_t vram_size ;
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uint16_t width , height , depth ;
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uint8_t r [ 256 ], g [ 256 ], b [ 256 ];
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uint32_t palette [ 256 ];
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uint8_t dac_index , dac_state ;
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} TCXState ;
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static void tcx_screen_dump ( void * opaque , const char * filename );
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static void tcx24_screen_dump ( void * opaque , const char * filename );
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static void tcx_set_dirty ( TCXState * s )
{
unsigned int i ;
for ( i = 0 ; i < MAXX * MAXY ; i += TARGET_PAGE_SIZE ) {
cpu_physical_memory_set_dirty ( s -> vram_offset + i );
}
}
static void tcx24_set_dirty ( TCXState * s )
{
unsigned int i ;
for ( i = 0 ; i < MAXX * MAXY * 4 ; i += TARGET_PAGE_SIZE ) {
cpu_physical_memory_set_dirty ( s -> vram24_offset + i );
cpu_physical_memory_set_dirty ( s -> cplane_offset + i );
}
}
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static void update_palette_entries ( TCXState * s , int start , int end )
{
int i ;
for ( i = start ; i < end ; i ++ ) {
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switch ( ds_get_bits_per_pixel ( s -> ds )) {
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default :
case 8 :
s -> palette [ i ] = rgb_to_pixel8 ( s -> r [ i ], s -> g [ i ], s -> b [ i ]);
break ;
case 15 :
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s -> palette [ i ] = rgb_to_pixel15 ( s -> r [ i ], s -> g [ i ], s -> b [ i ]);
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break ;
case 16 :
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s -> palette [ i ] = rgb_to_pixel16 ( s -> r [ i ], s -> g [ i ], s -> b [ i ]);
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break ;
case 32 :
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if ( is_surface_bgr ( s -> ds -> surface ))
s -> palette [ i ] = rgb_to_pixel32bgr ( s -> r [ i ], s -> g [ i ], s -> b [ i ]);
else
s -> palette [ i ] = rgb_to_pixel32 ( s -> r [ i ], s -> g [ i ], s -> b [ i ]);
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break ;
}
}
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if ( s -> depth == 24 ) {
tcx24_set_dirty ( s );
} else {
tcx_set_dirty ( s );
}
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}
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static void tcx_draw_line32 ( TCXState * s1 , uint8_t * d ,
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const uint8_t * s , int width )
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{
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int x ;
uint8_t val ;
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uint32_t * p = ( uint32_t * ) d ;
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for ( x = 0 ; x < width ; x ++ ) {
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val = * s ++ ;
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* p ++ = s1 -> palette [ val ];
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}
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}
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static void tcx_draw_line16 ( TCXState * s1 , uint8_t * d ,
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const uint8_t * s , int width )
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{
int x ;
uint8_t val ;
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uint16_t * p = ( uint16_t * ) d ;
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for ( x = 0 ; x < width ; x ++ ) {
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val = * s ++ ;
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* p ++ = s1 -> palette [ val ];
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}
}
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static void tcx_draw_line8 ( TCXState * s1 , uint8_t * d ,
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const uint8_t * s , int width )
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{
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int x ;
uint8_t val ;
for ( x = 0 ; x < width ; x ++ ) {
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val = * s ++ ;
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* d ++ = s1 -> palette [ val ];
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}
}
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/*
XXX Could be much more optimal :
* detect if line / page / whole screen is in 24 bit mode
* if destination is also BGR , use memcpy
*/
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static inline void tcx24_draw_line32 ( TCXState * s1 , uint8_t * d ,
const uint8_t * s , int width ,
const uint32_t * cplane ,
const uint32_t * s24 )
{
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int x , bgr , r , g , b ;
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uint8_t val , * p8 ;
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uint32_t * p = ( uint32_t * ) d ;
uint32_t dval ;
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bgr = is_surface_bgr ( s1 -> ds -> surface );
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for ( x = 0 ; x < width ; x ++ , s ++ , s24 ++ ) {
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if (( be32_to_cpu ( * cplane ++ ) & 0xff000000 ) == 0x03000000 ) {
// 24 - bit direct , BGR order
p8 = ( uint8_t * ) s24 ;
p8 ++ ;
b = * p8 ++ ;
g = * p8 ++ ;
r = * p8 ++ ;
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if ( bgr )
dval = rgb_to_pixel32bgr ( r , g , b );
else
dval = rgb_to_pixel32 ( r , g , b );
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} else {
val = * s ;
dval = s1 -> palette [ val ];
}
* p ++ = dval ;
}
}
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static inline int check_dirty ( ram_addr_t page , ram_addr_t page24 ,
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ram_addr_t cpage )
{
int ret ;
unsigned int off ;
ret = cpu_physical_memory_get_dirty ( page , VGA_DIRTY_FLAG );
for ( off = 0 ; off < TARGET_PAGE_SIZE * 4 ; off += TARGET_PAGE_SIZE ) {
ret |= cpu_physical_memory_get_dirty ( page24 + off , VGA_DIRTY_FLAG );
ret |= cpu_physical_memory_get_dirty ( cpage + off , VGA_DIRTY_FLAG );
}
return ret ;
}
static inline void reset_dirty ( TCXState * ts , ram_addr_t page_min ,
ram_addr_t page_max , ram_addr_t page24 ,
ram_addr_t cpage )
{
cpu_physical_memory_reset_dirty ( page_min , page_max + TARGET_PAGE_SIZE ,
VGA_DIRTY_FLAG );
page_min -= ts -> vram_offset ;
page_max -= ts -> vram_offset ;
cpu_physical_memory_reset_dirty ( page24 + page_min * 4 ,
page24 + page_max * 4 + TARGET_PAGE_SIZE ,
VGA_DIRTY_FLAG );
cpu_physical_memory_reset_dirty ( cpage + page_min * 4 ,
cpage + page_max * 4 + TARGET_PAGE_SIZE ,
VGA_DIRTY_FLAG );
}
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/* Fixed line length 1024 allows us to do nice tricks not possible on
VGA ... */
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static void tcx_update_display ( void * opaque )
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{
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TCXState * ts = opaque ;
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ram_addr_t page , page_min , page_max ;
int y , y_start , dd , ds ;
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uint8_t * d , * s ;
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void ( * f )( TCXState * s1 , uint8_t * dst , const uint8_t * src , int width );
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if ( ds_get_bits_per_pixel ( ts -> ds ) == 0 )
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return ;
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page = ts -> vram_offset ;
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y_start = - 1 ;
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page_min = - 1 ;
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page_max = 0 ;
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d = ds_get_data ( ts -> ds );
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s = ts -> vram ;
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dd = ds_get_linesize ( ts -> ds );
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ds = 1024 ;
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switch ( ds_get_bits_per_pixel ( ts -> ds )) {
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case 32 :
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f = tcx_draw_line32 ;
break ;
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case 15 :
case 16 :
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f = tcx_draw_line16 ;
break ;
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default :
case 8 :
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f = tcx_draw_line8 ;
break ;
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case 0 :
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return ;
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}
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for ( y = 0 ; y < ts -> height ; y += 4 , page += TARGET_PAGE_SIZE ) {
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if ( cpu_physical_memory_get_dirty ( page , VGA_DIRTY_FLAG )) {
if ( y_start < 0 )
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y_start = y ;
if ( page < page_min )
page_min = page ;
if ( page > page_max )
page_max = page ;
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f ( ts , d , s , ts -> width );
d += dd ;
s += ds ;
f ( ts , d , s , ts -> width );
d += dd ;
s += ds ;
f ( ts , d , s , ts -> width );
d += dd ;
s += ds ;
f ( ts , d , s , ts -> width );
d += dd ;
s += ds ;
} else {
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if ( y_start >= 0 ) {
/* flush to display */
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dpy_update ( ts -> ds , 0 , y_start ,
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ts -> width , y - y_start );
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y_start = - 1 ;
}
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d += dd * 4 ;
s += ds * 4 ;
}
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}
if ( y_start >= 0 ) {
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/* flush to display */
dpy_update ( ts -> ds , 0 , y_start ,
ts -> width , y - y_start );
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}
/* reset modified pages */
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if ( page_max >= page_min ) {
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cpu_physical_memory_reset_dirty ( page_min , page_max + TARGET_PAGE_SIZE ,
VGA_DIRTY_FLAG );
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}
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}
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static void tcx24_update_display ( void * opaque )
{
TCXState * ts = opaque ;
ram_addr_t page , page_min , page_max , cpage , page24 ;
int y , y_start , dd , ds ;
uint8_t * d , * s ;
uint32_t * cptr , * s24 ;
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if ( ds_get_bits_per_pixel ( ts -> ds ) != 32 )
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return ;
page = ts -> vram_offset ;
page24 = ts -> vram24_offset ;
cpage = ts -> cplane_offset ;
y_start = - 1 ;
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page_min = - 1 ;
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page_max = 0 ;
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d = ds_get_data ( ts -> ds );
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s = ts -> vram ;
s24 = ts -> vram24 ;
cptr = ts -> cplane ;
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dd = ds_get_linesize ( ts -> ds );
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ds = 1024 ;
for ( y = 0 ; y < ts -> height ; y += 4 , page += TARGET_PAGE_SIZE ,
page24 += TARGET_PAGE_SIZE , cpage += TARGET_PAGE_SIZE ) {
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if ( check_dirty ( page , page24 , cpage )) {
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if ( y_start < 0 )
y_start = y ;
if ( page < page_min )
page_min = page ;
if ( page > page_max )
page_max = page ;
tcx24_draw_line32 ( ts , d , s , ts -> width , cptr , s24 );
d += dd ;
s += ds ;
cptr += ds ;
s24 += ds ;
tcx24_draw_line32 ( ts , d , s , ts -> width , cptr , s24 );
d += dd ;
s += ds ;
cptr += ds ;
s24 += ds ;
tcx24_draw_line32 ( ts , d , s , ts -> width , cptr , s24 );
d += dd ;
s += ds ;
cptr += ds ;
s24 += ds ;
tcx24_draw_line32 ( ts , d , s , ts -> width , cptr , s24 );
d += dd ;
s += ds ;
cptr += ds ;
s24 += ds ;
} else {
if ( y_start >= 0 ) {
/* flush to display */
dpy_update ( ts -> ds , 0 , y_start ,
ts -> width , y - y_start );
y_start = - 1 ;
}
d += dd * 4 ;
s += ds * 4 ;
cptr += ds * 4 ;
s24 += ds * 4 ;
}
}
if ( y_start >= 0 ) {
/* flush to display */
dpy_update ( ts -> ds , 0 , y_start ,
ts -> width , y - y_start );
}
/* reset modified pages */
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if ( page_max >= page_min ) {
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reset_dirty ( ts , page_min , page_max , page24 , cpage );
}
}
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static void tcx_invalidate_display ( void * opaque )
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{
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TCXState * s = opaque ;
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tcx_set_dirty ( s );
qemu_console_resize ( s -> ds , s -> width , s -> height );
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}
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static void tcx24_invalidate_display ( void * opaque )
{
TCXState * s = opaque ;
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tcx_set_dirty ( s );
tcx24_set_dirty ( s );
qemu_console_resize ( s -> ds , s -> width , s -> height );
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}
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static void tcx_save ( QEMUFile * f , void * opaque )
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{
TCXState * s = opaque ;
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qemu_put_be16s ( f , & s -> height );
qemu_put_be16s ( f , & s -> width );
qemu_put_be16s ( f , & s -> depth );
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qemu_put_buffer ( f , s -> r , 256 );
qemu_put_buffer ( f , s -> g , 256 );
qemu_put_buffer ( f , s -> b , 256 );
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qemu_put_8s ( f , & s -> dac_index );
qemu_put_8s ( f , & s -> dac_state );
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}
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static int tcx_load ( QEMUFile * f , void * opaque , int version_id )
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{
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TCXState * s = opaque ;
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uint32_t dummy ;
if ( version_id != 3 && version_id != 4 )
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return - EINVAL ;
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if ( version_id == 3 ) {
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qemu_get_be32s ( f , & dummy );
qemu_get_be32s ( f , & dummy );
qemu_get_be32s ( f , & dummy );
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}
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qemu_get_be16s ( f , & s -> height );
qemu_get_be16s ( f , & s -> width );
qemu_get_be16s ( f , & s -> depth );
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qemu_get_buffer ( f , s -> r , 256 );
qemu_get_buffer ( f , s -> g , 256 );
qemu_get_buffer ( f , s -> b , 256 );
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qemu_get_8s ( f , & s -> dac_index );
qemu_get_8s ( f , & s -> dac_state );
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update_palette_entries ( s , 0 , 256 );
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if ( s -> depth == 24 ) {
tcx24_set_dirty ( s );
} else {
tcx_set_dirty ( s );
}
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return 0 ;
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}
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static void tcx_reset ( void * opaque )
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{
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TCXState * s = opaque ;
/* Initialize palette */
memset ( s -> r , 0 , 256 );
memset ( s -> g , 0 , 256 );
memset ( s -> b , 0 , 256 );
s -> r [ 255 ] = s -> g [ 255 ] = s -> b [ 255 ] = 255 ;
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update_palette_entries ( s , 0 , 256 );
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memset ( s -> vram , 0 , MAXX * MAXY );
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cpu_physical_memory_reset_dirty ( s -> vram_offset , s -> vram_offset +
MAXX * MAXY * ( 1 + 4 + 4 ), VGA_DIRTY_FLAG );
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s -> dac_index = 0 ;
s -> dac_state = 0 ;
}
static uint32_t tcx_dac_readl ( void * opaque , target_phys_addr_t addr )
{
return 0 ;
}
static void tcx_dac_writel ( void * opaque , target_phys_addr_t addr , uint32_t val )
{
TCXState * s = opaque ;
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switch ( addr ) {
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case 0 :
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s -> dac_index = val >> 24 ;
s -> dac_state = 0 ;
break ;
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case 4 :
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switch ( s -> dac_state ) {
case 0 :
s -> r [ s -> dac_index ] = val >> 24 ;
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update_palette_entries ( s , s -> dac_index , s -> dac_index + 1 );
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s -> dac_state ++ ;
break ;
case 1 :
s -> g [ s -> dac_index ] = val >> 24 ;
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update_palette_entries ( s , s -> dac_index , s -> dac_index + 1 );
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s -> dac_state ++ ;
break ;
case 2 :
s -> b [ s -> dac_index ] = val >> 24 ;
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update_palette_entries ( s , s -> dac_index , s -> dac_index + 1 );
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s -> dac_index = ( s -> dac_index + 1 ) & 255 ; // Index autoincrement
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default :
s -> dac_state = 0 ;
break ;
}
break ;
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default :
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break ;
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}
return ;
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}
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static CPUReadMemoryFunc * tcx_dac_read [ 3 ] = {
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NULL ,
NULL ,
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tcx_dac_readl ,
};
static CPUWriteMemoryFunc * tcx_dac_write [ 3 ] = {
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NULL ,
NULL ,
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tcx_dac_writel ,
};
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static uint32_t tcx_dummy_readl ( void * opaque , target_phys_addr_t addr )
{
return 0 ;
}
static void tcx_dummy_writel ( void * opaque , target_phys_addr_t addr ,
uint32_t val )
{
}
static CPUReadMemoryFunc * tcx_dummy_read [ 3 ] = {
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NULL ,
NULL ,
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tcx_dummy_readl ,
};
static CPUWriteMemoryFunc * tcx_dummy_write [ 3 ] = {
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NULL ,
NULL ,
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tcx_dummy_writel ,
};
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void tcx_init ( target_phys_addr_t addr , int vram_size , int width , int height ,
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int depth )
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{
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DeviceState * dev ;
SysBusDevice * s ;
dev = qdev_create ( NULL , "SUNW,tcx" );
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qdev_prop_set_taddr ( dev , "addr" , addr );
qdev_prop_set_uint32 ( dev , "vram_size" , vram_size );
qdev_prop_set_uint16 ( dev , "width" , width );
qdev_prop_set_uint16 ( dev , "height" , height );
qdev_prop_set_uint16 ( dev , "depth" , depth );
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qdev_init ( dev );
s = sysbus_from_qdev ( dev );
/* 8-bit plane */
sysbus_mmio_map ( s , 0 , addr + 0x00800000ULL );
/* DAC */
sysbus_mmio_map ( s , 1 , addr + 0x00200000ULL );
/* TEC (dummy) */
sysbus_mmio_map ( s , 2 , addr + 0x00700000ULL );
/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
sysbus_mmio_map ( s , 3 , addr + 0x00301000ULL );
if ( depth == 24 ) {
/* 24-bit plane */
sysbus_mmio_map ( s , 4 , addr + 0x02000000ULL );
/* Control plane */
sysbus_mmio_map ( s , 5 , addr + 0x0a000000ULL );
} else {
/* THC 8 bit (dummy) */
sysbus_mmio_map ( s , 4 , addr + 0x00300000ULL );
}
}
static void tcx_init1 ( SysBusDevice * dev )
{
TCXState * s = FROM_SYSBUS ( TCXState , dev );
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int io_memory , dummy_memory ;
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ram_addr_t vram_offset ;
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int size ;
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uint8_t * vram_base ;
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vram_offset = qemu_ram_alloc ( s -> vram_size * ( 1 + 4 + 4 ));
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vram_base = qemu_get_ram_ptr ( vram_offset );
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s -> vram_offset = vram_offset ;
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/* 8-bit plane */
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s -> vram = vram_base ;
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size = s -> vram_size ;
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sysbus_init_mmio ( dev , size , s -> vram_offset );
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vram_offset += size ;
vram_base += size ;
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/* DAC */
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io_memory = cpu_register_io_memory ( tcx_dac_read , tcx_dac_write , s );
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sysbus_init_mmio ( dev , TCX_DAC_NREGS , io_memory );
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/* TEC (dummy) */
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dummy_memory = cpu_register_io_memory ( tcx_dummy_read , tcx_dummy_write ,
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s );
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sysbus_init_mmio ( dev , TCX_TEC_NREGS , dummy_memory );
/* THC: NetBSD writes here even with 8-bit display: dummy */
sysbus_init_mmio ( dev , TCX_THC_NREGS_24 , dummy_memory );
if ( s -> depth == 24 ) {
/* 24-bit plane */
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size = s -> vram_size * 4 ;
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s -> vram24 = ( uint32_t * ) vram_base ;
s -> vram24_offset = vram_offset ;
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sysbus_init_mmio ( dev , size , vram_offset );
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vram_offset += size ;
vram_base += size ;
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/* Control plane */
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size = s -> vram_size * 4 ;
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s -> cplane = ( uint32_t * ) vram_base ;
s -> cplane_offset = vram_offset ;
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sysbus_init_mmio ( dev , size , vram_offset );
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s -> ds = graphic_console_init ( tcx24_update_display ,
tcx24_invalidate_display ,
tcx24_screen_dump , NULL , s );
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} else {
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/* THC 8 bit (dummy) */
sysbus_init_mmio ( dev , TCX_THC_NREGS_8 , dummy_memory );
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s -> ds = graphic_console_init ( tcx_update_display ,
tcx_invalidate_display ,
tcx_screen_dump , NULL , s );
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}
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register_savevm ( "tcx" , - 1 , 4 , tcx_save , tcx_load , s );
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qemu_register_reset ( tcx_reset , s );
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tcx_reset ( s );
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qemu_console_resize ( s -> ds , s -> width , s -> height );
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}
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static void tcx_screen_dump ( void * opaque , const char * filename )
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{
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TCXState * s = opaque ;
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FILE * f ;
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uint8_t * d , * d1 , v ;
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int y , x ;
f = fopen ( filename , "wb" );
if ( ! f )
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return ;
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fprintf ( f , "P6 \n %d %d \n %d \n " , s -> width , s -> height , 255 );
d1 = s -> vram ;
for ( y = 0 ; y < s -> height ; y ++ ) {
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d = d1 ;
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for ( x = 0 ; x < s -> width ; x ++ ) {
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v = * d ;
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fputc ( s -> r [ v ], f );
fputc ( s -> g [ v ], f );
fputc ( s -> b [ v ], f );
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d ++ ;
}
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d1 += MAXX ;
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}
fclose ( f );
return ;
}
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static void tcx24_screen_dump ( void * opaque , const char * filename )
{
TCXState * s = opaque ;
FILE * f ;
uint8_t * d , * d1 , v ;
uint32_t * s24 , * cptr , dval ;
int y , x ;
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f = fopen ( filename , "wb" );
if ( ! f )
return ;
fprintf ( f , "P6 \n %d %d \n %d \n " , s -> width , s -> height , 255 );
d1 = s -> vram ;
s24 = s -> vram24 ;
cptr = s -> cplane ;
for ( y = 0 ; y < s -> height ; y ++ ) {
d = d1 ;
for ( x = 0 ; x < s -> width ; x ++ , d ++ , s24 ++ ) {
if (( * cptr ++ & 0xff000000 ) == 0x03000000 ) { // 24 - bit direct
dval = * s24 & 0x00ffffff ;
fputc (( dval >> 16 ) & 0xff , f );
fputc (( dval >> 8 ) & 0xff , f );
fputc ( dval & 0xff , f );
} else {
v = * d ;
fputc ( s -> r [ v ], f );
fputc ( s -> g [ v ], f );
fputc ( s -> b [ v ], f );
}
}
d1 += MAXX ;
}
fclose ( f );
return ;
}
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static SysBusDeviceInfo tcx_info = {
. init = tcx_init1 ,
. qdev . name = "SUNW,tcx" ,
. qdev . size = sizeof ( TCXState ),
. qdev . props = ( Property []) {
{
. name = "addr" ,
. info = & qdev_prop_taddr ,
. offset = offsetof ( TCXState , addr ),
. defval = ( target_phys_addr_t []) { - 1 },
},{
. name = "vram_size" ,
. info = & qdev_prop_hex32 ,
. offset = offsetof ( TCXState , vram_size ),
. defval = ( uint32_t []) { - 1 },
},{
. name = "width" ,
. info = & qdev_prop_uint16 ,
. offset = offsetof ( TCXState , width ),
. defval = ( uint16_t []) { - 1 },
},{
. name = "height" ,
. info = & qdev_prop_uint16 ,
. offset = offsetof ( TCXState , height ),
. defval = ( uint16_t []) { - 1 },
},{
. name = "depth" ,
. info = & qdev_prop_uint16 ,
. offset = offsetof ( TCXState , depth ),
. defval = ( uint16_t []) { - 1 },
},
{ /* end of list */ }
}
};
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static void tcx_register_devices ( void )
{
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sysbus_register_withprop ( & tcx_info );
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}
device_init ( tcx_register_devices )