gwj / at91sam9263 · Commits

Commit e64d7d595f9454d29de7110e3ec6591105c8e467

Authored by blueswir1
1 parent 0e8f0967

Remove address masking 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5853 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 11 changed files with 45 additions and 43 deletions
hw/cs4231.c
  View file @e64d7d5
... ... @@ -30,8 +30,7 @@
30 30 /*
31 31 * In addition to Crystal CS4231 there is a DMA controller on Sparc.
32 32 */
33   -#define CS_MAXADDR 0x3f
34   -#define CS_SIZE (CS_MAXADDR + 1)
  33 +#define CS_SIZE 0x40
35 34 #define CS_REGS 16
36 35 #define CS_DREGS 32
37 36 #define CS_MAXDREG (CS_DREGS - 1)
... ... @@ -68,7 +67,7 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
68 67 CSState *s = opaque;
69 68 uint32_t saddr, ret;
70 69  
71   - saddr = (addr & CS_MAXADDR) >> 2;
  70 + saddr = addr >> 2;
72 71 switch (saddr) {
73 72 case 1:
74 73 switch (CS_RAP(s)) {
... ... @@ -94,7 +93,7 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
94 93 CSState *s = opaque;
95 94 uint32_t saddr;
96 95  
97   - saddr = (addr & CS_MAXADDR) >> 2;
  96 + saddr = addr >> 2;
98 97 DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
99 98 switch (saddr) {
100 99 case 1:
... ...
hw/eccmemctl.c
  View file @e64d7d5
... ... @@ -114,7 +114,6 @@
114 114  
115 115 #define ECC_NREGS 9
116 116 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
117   -#define ECC_ADDR_MASK 0x1f
118 117  
119 118 #define ECC_DIAG_SIZE 4
120 119 #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
... ... @@ -129,7 +128,7 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
129 128 {
130 129 ECCState *s = opaque;
131 130  
132   - switch ((addr & ECC_ADDR_MASK) >> 2) {
  131 + switch (addr >> 2) {
133 132 case ECC_MER:
134 133 s->regs[ECC_MER] = (s->regs[ECC_MER] & (ECC_MER_VER | ECC_MER_IMPL)) |
135 134 (val & ~(ECC_MER_VER | ECC_MER_IMPL));
... ... @@ -167,7 +166,7 @@ static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
167 166 ECCState *s = opaque;
168 167 uint32_t ret = 0;
169 168  
170   - switch ((addr & ECC_ADDR_MASK) >> 2) {
  169 + switch (addr >> 2) {
171 170 case ECC_MER:
172 171 ret = s->regs[ECC_MER];
173 172 DPRINTF("Read memory enable %08x\n", ret);
... ... @@ -225,15 +224,16 @@ static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
225 224 {
226 225 ECCState *s = opaque;
227 226  
228   - DPRINTF("Write diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), val);
  227 + DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
229 228 s->diag[addr & ECC_DIAG_MASK] = val;
230 229 }
231 230  
232 231 static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
233 232 {
234 233 ECCState *s = opaque;
235   - uint32_t ret = s->diag[addr & ECC_DIAG_MASK];
236   - DPRINTF("Read diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), ret);
  234 + uint32_t ret = s->diag[(int)addr];
  235 +
  236 + DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
237 237 return ret;
238 238 }
239 239  
... ...
hw/esp.c
  View file @e64d7d5
... ... @@ -425,7 +425,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
425 425 ESPState *s = opaque;
426 426 uint32_t saddr;
427 427  
428   - saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
  428 + saddr = addr >> s->it_shift;
429 429 DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
430 430 switch (saddr) {
431 431 case ESP_FIFO:
... ... @@ -461,7 +461,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
461 461 ESPState *s = opaque;
462 462 uint32_t saddr;
463 463  
464   - saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
  464 + saddr = addr >> s->it_shift;
465 465 DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
466 466 val);
467 467 switch (saddr) {
... ...
hw/fdc.c
  View file @e64d7d5
... ... @@ -513,7 +513,7 @@ static uint32_t fdctrl_read (void *opaque, uint32_t reg)
513 513 fdctrl_t *fdctrl = opaque;
514 514 uint32_t retval;
515 515  
516   - switch (reg & 0x07) {
  516 + switch (reg) {
517 517 case FD_REG_SRA:
518 518 retval = fdctrl_read_statusA(fdctrl);
519 519 break;
... ... @@ -550,7 +550,7 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
550 550  
551 551 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
552 552  
553   - switch (reg & 0x07) {
  553 + switch (reg) {
554 554 case FD_REG_DOR:
555 555 fdctrl_write_dor(fdctrl, value);
556 556 break;
... ... @@ -568,6 +568,16 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
568 568 }
569 569 }
570 570  
  571 +static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
  572 +{
  573 + return fdctrl_read(opaque, reg & 7);
  574 +}
  575 +
  576 +static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
  577 +{
  578 + fdctrl_write(opaque, reg & 7, value);
  579 +}
  580 +
571 581 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
572 582 {
573 583 return fdctrl_read(opaque, (uint32_t)reg);
... ... @@ -1896,14 +1906,14 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1896 1906 fdctrl);
1897 1907 cpu_register_physical_memory(io_base, 0x08, io_mem);
1898 1908 } else {
1899   - register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
1900   - fdctrl);
1901   - register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
1902   - fdctrl);
1903   - register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
1904   - fdctrl);
1905   - register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
1906   - fdctrl);
  1909 + register_ioport_read((uint32_t)io_base + 0x01, 5, 1,
  1910 + &fdctrl_read_port, fdctrl);
  1911 + register_ioport_read((uint32_t)io_base + 0x07, 1, 1,
  1912 + &fdctrl_read_port, fdctrl);
  1913 + register_ioport_write((uint32_t)io_base + 0x01, 5, 1,
  1914 + &fdctrl_write_port, fdctrl);
  1915 + register_ioport_write((uint32_t)io_base + 0x07, 1, 1,
  1916 + &fdctrl_write_port, fdctrl);
1907 1917 }
1908 1918  
1909 1919 return fdctrl;
... ...
hw/pcnet.c
  View file @e64d7d5
... ... @@ -2060,14 +2060,14 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
2060 2060 printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr,
2061 2061 val & 0xffff);
2062 2062 #endif
2063   - pcnet_ioport_writew(opaque, addr & 7, val & 0xffff);
  2063 + pcnet_ioport_writew(opaque, addr, val & 0xffff);
2064 2064 }
2065 2065  
2066 2066 static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
2067 2067 {
2068 2068 uint32_t val;
2069 2069  
2070   - val = pcnet_ioport_readw(opaque, addr & 7);
  2070 + val = pcnet_ioport_readw(opaque, addr);
2071 2071 #ifdef PCNET_DEBUG_IO
2072 2072 printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
2073 2073 val & 0xffff);
... ...
hw/sbi.c
  View file @e64d7d5
... ... @@ -46,7 +46,6 @@ typedef struct SBIState {
46 46 } SBIState;
47 47  
48 48 #define SBI_SIZE (SBI_NREGS * 4)
49   -#define SBI_MASK (SBI_SIZE - 1)
50 49  
51 50 static void sbi_check_interrupts(void *opaque)
52 51 {
... ... @@ -65,7 +64,7 @@ static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
65 64 SBIState *s = opaque;
66 65 uint32_t saddr, ret;
67 66  
68   - saddr = (addr & SBI_MASK) >> 2;
  67 + saddr = addr >> 2;
69 68 switch (saddr) {
70 69 default:
71 70 ret = s->regs[saddr];
... ... @@ -81,7 +80,7 @@ static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
81 80 SBIState *s = opaque;
82 81 uint32_t saddr;
83 82  
84   - saddr = (addr & SBI_MASK) >> 2;
  83 + saddr = addr >> 2;
85 84 DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
86 85 switch (saddr) {
87 86 default:
... ...
hw/slavio_serial.c
  View file @e64d7d5
... ... @@ -108,8 +108,7 @@ struct SerialState {
108 108 struct ChannelState chn[2];
109 109 };
110 110  
111   -#define SERIAL_MAXADDR 7
112   -#define SERIAL_SIZE (SERIAL_MAXADDR + 1)
  111 +#define SERIAL_SIZE 8
113 112 #define SERIAL_CTRL 0
114 113 #define SERIAL_DATA 1
115 114  
... ... @@ -477,7 +476,7 @@ static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr,
477 476  
478 477 val &= 0xff;
479 478 saddr = (addr & 3) >> 1;
480   - channel = (addr & SERIAL_MAXADDR) >> 2;
  479 + channel = addr >> 2;
481 480 s = &serial->chn[channel];
482 481 switch (saddr) {
483 482 case SERIAL_CTRL:
... ... @@ -574,7 +573,7 @@ static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)
574 573 int channel;
575 574  
576 575 saddr = (addr & 3) >> 1;
577   - channel = (addr & SERIAL_MAXADDR) >> 2;
  576 + channel = addr >> 2;
578 577 s = &serial->chn[channel];
579 578 switch (saddr) {
580 579 case SERIAL_CTRL:
... ...
hw/slavio_timer.c
  View file @e64d7d5
... ... @@ -66,7 +66,6 @@ typedef struct SLAVIO_TIMERState {
66 66 uint32_t slave_mode;
67 67 } SLAVIO_TIMERState;
68 68  
69   -#define TIMER_MAXADDR 0x1f
70 69 #define SYS_TIMER_SIZE 0x14
71 70 #define CPU_TIMER_SIZE 0x10
72 71  
... ... @@ -132,7 +131,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
132 131 SLAVIO_TIMERState *s = opaque;
133 132 uint32_t saddr, ret;
134 133  
135   - saddr = (addr & TIMER_MAXADDR) >> 2;
  134 + saddr = addr >> 2;
136 135 switch (saddr) {
137 136 case TIMER_LIMIT:
138 137 // read limit (system counter mode) or read most signifying
... ... @@ -185,7 +184,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
185 184 uint32_t saddr;
186 185  
187 186 DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
188   - saddr = (addr & TIMER_MAXADDR) >> 2;
  187 + saddr = addr >> 2;
189 188 switch (saddr) {
190 189 case TIMER_LIMIT:
191 190 if (slavio_timer_is_user(s)) {
... ...
hw/sparc32_dma.c
  View file @e64d7d5
... ... @@ -45,7 +45,6 @@ do { printf("DMA: " fmt , ##args); } while (0)
45 45  
46 46 #define DMA_REGS 4
47 47 #define DMA_SIZE (4 * sizeof(uint32_t))
48   -#define DMA_MAXADDR (DMA_SIZE - 1)
49 48  
50 49 #define DMA_VER 0xa0000000
51 50 #define DMA_INTR 1
... ... @@ -157,7 +156,7 @@ static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
157 156 DMAState *s = opaque;
158 157 uint32_t saddr;
159 158  
160   - saddr = (addr & DMA_MAXADDR) >> 2;
  159 + saddr = addr >> 2;
161 160 DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
162 161 s->dmaregs[saddr]);
163 162  
... ... @@ -169,7 +168,7 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
169 168 DMAState *s = opaque;
170 169 uint32_t saddr;
171 170  
172   - saddr = (addr & DMA_MAXADDR) >> 2;
  171 + saddr = addr >> 2;
173 172 DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
174 173 s->dmaregs[saddr], val);
175 174 switch (saddr) {
... ...
hw/sun4c_intctl.c
  View file @e64d7d5
... ... @@ -52,8 +52,7 @@ typedef struct Sun4c_INTCTLState {
52 52 uint8_t pending;
53 53 } Sun4c_INTCTLState;
54 54  
55   -#define INTCTL_MAXADDR 0
56   -#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  55 +#define INTCTL_SIZE 1
57 56  
58 57 static void sun4c_check_interrupts(void *opaque);
59 58  
... ...
hw/tcx.c
  View file @e64d7d5
... ... @@ -437,15 +437,13 @@ static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
437 437 static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
438 438 {
439 439 TCXState *s = opaque;
440   - uint32_t saddr;
441 440  
442   - saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
443   - switch (saddr) {
  441 + switch (addr) {
444 442 case 0:
445 443 s->dac_index = val >> 24;
446 444 s->dac_state = 0;
447 445 break;
448   - case 1:
  446 + case 4:
449 447 switch (s->dac_state) {
450 448 case 0:
451 449 s->r[s->dac_index] = val >> 24;
... ...