gwj / at91sam9263 · Commits

Commit a08d43677f87a19daa653774d3c6f71855e23178

Authored by Jan Kiszka
Committed by Anthony Liguori
1 parent a62acdc0

Revert "Introduce reset notifier order" 

This reverts commit 8217606e (and
updates later added users of qemu_register_reset), we solved the
problem it originally addressed less invasively.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Inline Side-by-side
Showing 83 changed files with 117 additions and 120 deletions
hw/ac97.c
  View file @a08d436
... ... @@ -1369,7 +1369,7 @@ int ac97_init (PCIBus *bus)
1369 1369 pci_register_bar (&d->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
1370 1370 pci_register_bar (&d->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
1371 1371 register_savevm ("ac97", 0, 2, ac97_save, ac97_load, s);
1372   - qemu_register_reset (ac97_on_reset, 0, s);
  1372 + qemu_register_reset (ac97_on_reset, s);
1373 1373 AUD_register_card ("ac97", &s->card);
1374 1374 ac97_on_reset (s);
1375 1375 return 0;
... ...
hw/acpi.c
  View file @a08d436
... ... @@ -550,7 +550,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
550 550  
551 551 s->smbus = i2c_init_bus(NULL, "i2c");
552 552 s->irq = sci_irq;
553   - qemu_register_reset(piix4_reset, 0, s);
  553 + qemu_register_reset(piix4_reset, s);
554 554  
555 555 return s->smbus;
556 556 }
... ...
hw/adb.c
  View file @a08d436
... ... @@ -122,7 +122,7 @@ ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
122 122 d->devreq = devreq;
123 123 d->devreset = devreset;
124 124 d->opaque = opaque;
125   - qemu_register_reset((QEMUResetHandler *)devreset, 0, d);
  125 + qemu_register_reset((QEMUResetHandler *)devreset, d);
126 126 d->devreset(d);
127 127 return d;
128 128 }
... ...
hw/apic.c
  View file @a08d436
... ... @@ -998,7 +998,7 @@ int apic_init(CPUState *env)
998 998 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
999 999  
1000 1000 register_savevm("apic", s->idx, 2, apic_save, apic_load, s);
1001   - qemu_register_reset(apic_reset, 0, s);
  1001 + qemu_register_reset(apic_reset, s);
1002 1002  
1003 1003 local_apics[s->idx] = s;
1004 1004 return 0;
... ...
hw/arm_boot.c
  View file @a08d436
... ... @@ -203,7 +203,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
203 203 if (info->nb_cpus == 0)
204 204 info->nb_cpus = 1;
205 205 env->boot_info = info;
206   - qemu_register_reset(main_cpu_reset, 0, env);
  206 + qemu_register_reset(main_cpu_reset, env);
207 207 }
208 208  
209 209 /* Assume that raw images are linux kernels, and ELF images are not. */
... ...
hw/axis_dev88.c
  View file @a08d436
... ... @@ -271,7 +271,7 @@ void axisdev88_init (ram_addr_t ram_size,
271 271 cpu_model = "crisv32";
272 272 }
273 273 env = cpu_init(cpu_model);
274   - qemu_register_reset(main_cpu_reset, 0, env);
  274 + qemu_register_reset(main_cpu_reset, env);
275 275  
276 276 /* allocate RAM */
277 277 phys_ram = qemu_ram_alloc(ram_size);
... ...
hw/cirrus_vga.c
  View file @a08d436
... ... @@ -3228,7 +3228,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3228 3228 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3229 3229 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
3230 3230  
3231   - qemu_register_reset(cirrus_reset, 0, s);
  3231 + qemu_register_reset(cirrus_reset, s);
3232 3232 cirrus_reset(s);
3233 3233 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3234 3234 }
... ...
hw/cs4231.c
  View file @a08d436
... ... @@ -175,6 +175,6 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl)
175 175 cs_io_memory = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);
176 176 cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
177 177 register_savevm("cs4231", base, 1, cs_save, cs_load, s);
178   - qemu_register_reset(cs_reset, 0, s);
  178 + qemu_register_reset(cs_reset, s);
179 179 cs_reset(s);
180 180 }
... ...
hw/cs4231a.c
  View file @a08d436
... ... @@ -656,7 +656,7 @@ int cs4231a_init (qemu_irq *pic)
656 656 DMA_register_channel (s->dma, cs_dma_read, s);
657 657  
658 658 register_savevm ("cs4231a", 0, 1, cs_save, cs_load, s);
659   - qemu_register_reset (cs_reset, 0, s);
  659 + qemu_register_reset (cs_reset, s);
660 660 cs_reset (s);
661 661  
662 662 AUD_register_card ("cs4231a", &s->card);
... ...
hw/cuda.c
  View file @a08d436
... ... @@ -762,6 +762,6 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
762 762 s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
763 763 *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);
764 764 register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);
765   - qemu_register_reset(cuda_reset, 0, s);
  765 + qemu_register_reset(cuda_reset, s);
766 766 cuda_reset(s);
767 767 }
... ...
hw/dma.c
  View file @a08d436
... ... @@ -493,7 +493,7 @@ static void dma_init2(struct dma_cont *d, int base, int dshift,
493 493 register_ioport_read (base + ((i + 8) << dshift), 1, 1,
494 494 read_cont, d);
495 495 }
496   - qemu_register_reset(dma_reset, 0, d);
  496 + qemu_register_reset(dma_reset, d);
497 497 dma_reset(d);
498 498 for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
499 499 d->regs[i].transfer_handler = dma_phony_handler;
... ...
hw/dp8393x.c
  View file @a08d436
... ... @@ -894,7 +894,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
894 894 nic_receive, NULL, nic_cleanup, s);
895 895  
896 896 qemu_format_nic_info_str(s->vc, nd->macaddr);
897   - qemu_register_reset(nic_reset, 0, s);
  897 + qemu_register_reset(nic_reset, s);
898 898 nic_reset(s);
899 899  
900 900 s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);
... ...
hw/e1000.c
  View file @a08d436
... ... @@ -1121,7 +1121,7 @@ static void pci_e1000_init(PCIDevice *pci_dev)
1121 1121  
1122 1122 register_savevm(info_str, -1, 2, nic_save, nic_load, d);
1123 1123 d->dev.unregister = pci_e1000_uninit;
1124   - qemu_register_reset(e1000_reset, 0, d);
  1124 + qemu_register_reset(e1000_reset, d);
1125 1125 e1000_reset(d);
1126 1126 }
1127 1127  
... ...
hw/eccmemctl.c
  View file @a08d436
... ... @@ -334,7 +334,7 @@ void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
334 334 ecc_io_memory);
335 335 }
336 336 register_savevm("ECC", base, 3, ecc_save, ecc_load, s);
337   - qemu_register_reset(ecc_reset, 0, s);
  337 + qemu_register_reset(ecc_reset, s);
338 338 ecc_reset(s);
339 339 return s;
340 340 }
... ...
hw/eepro100.c
  View file @a08d436
... ... @@ -1772,7 +1772,7 @@ static void nic_init(PCIDevice *pci_dev, uint32_t device)
1772 1772  
1773 1773 qemu_format_nic_info_str(s->vc, s->macaddr);
1774 1774  
1775   - qemu_register_reset(nic_reset, 0, s);
  1775 + qemu_register_reset(nic_reset, s);
1776 1776  
1777 1777 register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s);
1778 1778 }
... ...
hw/es1370.c
  View file @a08d436
... ... @@ -1055,7 +1055,7 @@ int es1370_init (PCIBus *bus)
1055 1055  
1056 1056 pci_register_bar (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
1057 1057 register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s);
1058   - qemu_register_reset (es1370_on_reset, 0, s);
  1058 + qemu_register_reset (es1370_on_reset, s);
1059 1059  
1060 1060 AUD_register_card ("es1370", &s->card);
1061 1061 es1370_reset (s);
... ...
hw/escc.c
  View file @a08d436
... ... @@ -758,7 +758,7 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
758 758 register_savevm("escc", base, 2, escc_save, escc_load, s);
759 759 else
760 760 register_savevm("escc", -1, 2, escc_save, escc_load, s);
761   - qemu_register_reset(escc_reset, 0, s);
  761 + qemu_register_reset(escc_reset, s);
762 762 escc_reset(s);
763 763 return escc_io_memory;
764 764 }
... ... @@ -932,6 +932,6 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
932 932 "QEMU Sun Mouse");
933 933 qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
934 934 register_savevm("slavio_serial_mouse", base, 2, escc_save, escc_load, s);
935   - qemu_register_reset(escc_reset, 0, s);
  935 + qemu_register_reset(escc_reset, s);
936 936 escc_reset(s);
937 937 }
... ...
hw/esp.c
  View file @a08d436
... ... @@ -680,7 +680,7 @@ static void esp_init1(SysBusDevice *dev)
680 680 esp_reset(s);
681 681  
682 682 register_savevm("esp", -1, 3, esp_save, esp_load, s);
683   - qemu_register_reset(esp_reset, 0, s);
  683 + qemu_register_reset(esp_reset, s);
684 684  
685 685 qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
686 686  
... ...
hw/etraxfs.c
  View file @a08d436
... ... @@ -65,7 +65,7 @@ void bareetraxfs_init (ram_addr_t ram_size,
65 65 cpu_model = "crisv32";
66 66 }
67 67 env = cpu_init(cpu_model);
68   - qemu_register_reset(main_cpu_reset, 0, env);
  68 + qemu_register_reset(main_cpu_reset, env);
69 69  
70 70 /* allocate RAM */
71 71 phys_ram = qemu_ram_alloc(ram_size);
... ...
hw/etraxfs_timer.c
  View file @a08d436
... ... @@ -326,7 +326,7 @@ static void etraxfs_timer_init(SysBusDevice *dev)
326 326 timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
327 327 sysbus_init_mmio(dev, 0x5c, timer_regs);
328 328  
329   - qemu_register_reset(etraxfs_timer_reset, 0, t);
  329 + qemu_register_reset(etraxfs_timer_reset, t);
330 330 }
331 331  
332 332 static void etraxfs_timer_register(void)
... ...
hw/fdc.c
  View file @a08d436
... ... @@ -1883,7 +1883,7 @@ static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
1883 1883 }
1884 1884 fdctrl_external_reset(fdctrl);
1885 1885 register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
1886   - qemu_register_reset(fdctrl_external_reset, 0, fdctrl);
  1886 + qemu_register_reset(fdctrl_external_reset, fdctrl);
1887 1887 for (i = 0; i < MAX_FD; i++) {
1888 1888 fd_revalidate(&fdctrl->drives[i]);
1889 1889 }
... ...
hw/fw_cfg.c
  View file @a08d436
... ... @@ -281,7 +281,7 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
281 281 fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
282 282  
283 283 register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s);
284   - qemu_register_reset(fw_cfg_reset, 0, s);
  284 + qemu_register_reset(fw_cfg_reset, s);
285 285 fw_cfg_reset(s);
286 286  
287 287 return s;
... ...
hw/g364fb.c
  View file @a08d436
... ... @@ -598,7 +598,7 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
598 598 s->vram = qemu_get_ram_ptr(s->vram_offset);
599 599 s->irq = irq;
600 600  
601   - qemu_register_reset(g364fb_reset, 0, s);
  601 + qemu_register_reset(g364fb_reset, s);
602 602 register_savevm("g364fb", 0, 1, g364fb_save, g364fb_load, s);
603 603 g364fb_reset(s);
604 604  
... ...
hw/grackle_pci.c
  View file @a08d436
... ... @@ -177,7 +177,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
177 177 d->config[0x27] = 0x85;
178 178 #endif
179 179 register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);
180   - qemu_register_reset(pci_grackle_reset, 0, d);
  180 + qemu_register_reset(pci_grackle_reset, d);
181 181 pci_grackle_reset(d);
182 182  
183 183 return s->bus;
... ...
hw/heathrow_pic.c
  View file @a08d436
... ... @@ -230,7 +230,7 @@ qemu_irq *heathrow_pic_init(int *pmem_index,
230 230  
231 231 register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,
232 232 heathrow_pic_load, s);
233   - qemu_register_reset(heathrow_pic_reset, 0, s);
  233 + qemu_register_reset(heathrow_pic_reset, s);
234 234 heathrow_pic_reset(s);
235 235 return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
236 236 }
... ...
hw/hpet.c
  View file @a08d436
... ... @@ -580,7 +580,7 @@ void hpet_init(qemu_irq *irq) {
580 580 }
581 581 hpet_reset(s);
582 582 register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);
583   - qemu_register_reset(hpet_reset, 0, s);
  583 + qemu_register_reset(hpet_reset, s);
584 584 /* HPET Area */
585 585 iomemtype = cpu_register_io_memory(hpet_ram_read,
586 586 hpet_ram_write, s);
... ...
... ... @@ -259,7 +259,7 @@ void unregister_savevm(const char *idstr, void *opaque);
259 259  
260 260 typedef void QEMUResetHandler(void *opaque);
261 261  
262   -void qemu_register_reset(QEMUResetHandler *func, int order, void *opaque);
  262 +void qemu_register_reset(QEMUResetHandler *func, void *opaque);
263 263  
264 264 /* handler to set the boot_device for a specific type of QEMUMachine */
265 265 /* return 0 if success */
... ...
hw/i8254.c
  View file @a08d436
... ... @@ -497,7 +497,7 @@ PITState *pit_init(int base, qemu_irq irq)
497 497  
498 498 register_savevm("i8254", base, 1, pit_save, pit_load, pit);
499 499  
500   - qemu_register_reset(pit_reset, 0, pit);
  500 + qemu_register_reset(pit_reset, pit);
501 501 register_ioport_write(base, 4, 1, pit_ioport_write, pit);
502 502 register_ioport_read(base, 3, 1, pit_ioport_read, pit);
503 503  
... ...
hw/i8259.c
  View file @a08d436
... ... @@ -508,7 +508,7 @@ static void pic_init1(int io_addr, int elcr_addr, PicState *s)
508 508 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
509 509 }
510 510 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
511   - qemu_register_reset(pic_reset, 0, s);
  511 + qemu_register_reset(pic_reset, s);
512 512 }
513 513  
514 514 void pic_info(Monitor *mon)
... ...
hw/ide.c
  View file @a08d436
... ... @@ -3340,7 +3340,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
3340 3340 ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
3341 3341  
3342 3342 register_savevm("ide", 0, 2, pci_ide_save, pci_ide_load, d);
3343   - qemu_register_reset(cmd646_reset, 0, d);
  3343 + qemu_register_reset(cmd646_reset, d);
3344 3344 cmd646_reset(d);
3345 3345 }
3346 3346  
... ... @@ -3383,7 +3383,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
3383 3383 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
3384 3384 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
3385 3385  
3386   - qemu_register_reset(piix3_reset, 0, d);
  3386 + qemu_register_reset(piix3_reset, d);
3387 3387 piix3_reset(d);
3388 3388  
3389 3389 pci_register_bar((PCIDevice *)d, 4, 0x10,
... ... @@ -3423,7 +3423,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
3423 3423 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
3424 3424 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
3425 3425  
3426   - qemu_register_reset(piix3_reset, 0, d);
  3426 + qemu_register_reset(piix3_reset, d);
3427 3427 piix3_reset(d);
3428 3428  
3429 3429 pci_register_bar((PCIDevice *)d, 4, 0x10,
... ... @@ -3764,7 +3764,7 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
3764 3764 pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
3765 3765 pmac_ide_write, d);
3766 3766 register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d);
3767   - qemu_register_reset(pmac_ide_reset, 0, d);
  3767 + qemu_register_reset(pmac_ide_reset, d);
3768 3768 pmac_ide_reset(d);
3769 3769  
3770 3770 return pmac_ide_memory;
... ...
hw/ioapic.c
  View file @a08d436
... ... @@ -255,7 +255,7 @@ IOAPICState *ioapic_init(void)
255 255 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
256 256  
257 257 register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
258   - qemu_register_reset(ioapic_reset, 0, s);
  258 + qemu_register_reset(ioapic_reset, s);
259 259  
260 260 return s;
261 261 }
... ...
hw/iommu.c
  View file @a08d436
... ... @@ -379,7 +379,7 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
379 379 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
380 380  
381 381 register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
382   - qemu_register_reset(iommu_reset, 0, s);
  382 + qemu_register_reset(iommu_reset, s);
383 383 iommu_reset(s);
384 384 return s;
385 385 }
... ...
hw/lm832x.c
  View file @a08d436
... ... @@ -501,7 +501,7 @@ static void lm8323_init(i2c_slave *i2c)
501 501  
502 502 lm_kbd_reset(s);
503 503  
504   - qemu_register_reset((void *) lm_kbd_reset, 0, s);
  504 + qemu_register_reset((void *) lm_kbd_reset, s);
505 505 register_savevm("LM8323", -1, 0, lm_kbd_save, lm_kbd_load, s);
506 506 }
507 507  
... ...
hw/m48t59.c
  View file @a08d436
... ... @@ -641,7 +641,7 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
641 641 }
642 642 qemu_get_timedate(&s->alarm, 0);
643 643  
644   - qemu_register_reset(m48t59_reset, 0, s);
  644 + qemu_register_reset(m48t59_reset, s);
645 645 save_base = mem_base ? mem_base : io_base;
646 646 register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);
647 647  
... ...
hw/mac_dbdma.c
  View file @a08d436
... ... @@ -839,7 +839,7 @@ void* DBDMA_init (int *dbdma_mem_index)
839 839  
840 840 *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);
841 841 register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
842   - qemu_register_reset(dbdma_reset, 0, s);
  842 + qemu_register_reset(dbdma_reset, s);
843 843 dbdma_reset(s);
844 844  
845 845 dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
... ...
hw/mac_nvram.c
  View file @a08d436
... ... @@ -142,7 +142,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
142 142 *mem_index = s->mem_index;
143 143 register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,
144 144 s);
145   - qemu_register_reset(macio_nvram_reset, 0, s);
  145 + qemu_register_reset(macio_nvram_reset, s);
146 146 macio_nvram_reset(s);
147 147  
148 148 return s;
... ...
hw/mc146818rtc.c
  View file @a08d436
... ... @@ -626,7 +626,7 @@ RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year)
626 626 if (rtc_td_hack)
627 627 register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
628 628 #endif
629   - qemu_register_reset(rtc_reset, 0, s);
  629 + qemu_register_reset(rtc_reset, s);
630 630  
631 631 return s;
632 632 }
... ... @@ -743,6 +743,6 @@ RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
743 743 if (rtc_td_hack)
744 744 register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
745 745 #endif
746   - qemu_register_reset(rtc_reset, 0, s);
  746 + qemu_register_reset(rtc_reset, s);
747 747 return s;
748 748 }
... ...
hw/mips_jazz.c
  View file @a08d436
... ... @@ -146,7 +146,7 @@ void mips_jazz_init (ram_addr_t ram_size,
146 146 fprintf(stderr, "Unable to find CPU definition\n");
147 147 exit(1);
148 148 }
149   - qemu_register_reset(main_cpu_reset, 0, env);
  149 + qemu_register_reset(main_cpu_reset, env);
150 150  
151 151 /* allocate RAM */
152 152 ram_offset = qemu_ram_alloc(ram_size);
... ...
hw/mips_malta.c
  View file @a08d436
... ... @@ -447,7 +447,7 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir
447 447 s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1);
448 448  
449 449 malta_fpga_reset(s);
450   - qemu_register_reset(malta_fpga_reset, 0, s);
  450 + qemu_register_reset(malta_fpga_reset, s);
451 451  
452 452 return s;
453 453 }
... ... @@ -792,7 +792,7 @@ void mips_malta_init (ram_addr_t ram_size,
792 792 fprintf(stderr, "Unable to find CPU definition\n");
793 793 exit(1);
794 794 }
795   - qemu_register_reset(main_cpu_reset, 0, env);
  795 + qemu_register_reset(main_cpu_reset, env);
796 796  
797 797 /* allocate RAM */
798 798 if (ram_size > (256 << 20)) {
... ...
hw/mips_mipssim.c
  View file @a08d436
... ... @@ -126,7 +126,7 @@ mips_mipssim_init (ram_addr_t ram_size,
126 126 fprintf(stderr, "Unable to find CPU definition\n");
127 127 exit(1);
128 128 }
129   - qemu_register_reset(main_cpu_reset, 0, env);
  129 + qemu_register_reset(main_cpu_reset, env);
130 130  
131 131 /* Allocate RAM. */
132 132 ram_offset = qemu_ram_alloc(ram_size);
... ...
hw/mips_r4k.c
  View file @a08d436
... ... @@ -171,7 +171,7 @@ void mips_r4k_init (ram_addr_t ram_size,
171 171 fprintf(stderr, "Unable to find CPU definition\n");
172 172 exit(1);
173 173 }
174   - qemu_register_reset(main_cpu_reset, 0, env);
  174 + qemu_register_reset(main_cpu_reset, env);
175 175  
176 176 /* allocate RAM */
177 177 if (ram_size > (256 << 20)) {
... ...
hw/musicpal.c
  View file @a08d436
... ... @@ -441,7 +441,7 @@ static i2c_interface *musicpal_audio_init(qemu_irq irq)
441 441 musicpal_audio_writefn, s);
442 442 cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
443 443  
444   - qemu_register_reset(musicpal_audio_reset, 0, s);
  444 + qemu_register_reset(musicpal_audio_reset, s);
445 445  
446 446 return i2c;
447 447 }
... ... @@ -1047,7 +1047,7 @@ static void mv88w8618_pic_init(SysBusDevice *dev)
1047 1047 mv88w8618_pic_writefn, s);
1048 1048 sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
1049 1049  
1050   - qemu_register_reset(mv88w8618_pic_reset, 0, s);
  1050 + qemu_register_reset(mv88w8618_pic_reset, s);
1051 1051 }
1052 1052  
1053 1053 /* PIT register offsets */
... ...
hw/nseries.c
  View file @a08d436
... ... @@ -1329,7 +1329,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
1329 1329 binfo->initrd_filename = initrd_filename;
1330 1330 arm_load_kernel(s->cpu->env, binfo);
1331 1331  
1332   - qemu_register_reset(n8x0_boot_init, 0, s);
  1332 + qemu_register_reset(n8x0_boot_init, s);
1333 1333 n8x0_boot_init(s);
1334 1334 }
1335 1335  
... ...
hw/omap1.c
  View file @a08d436
... ... @@ -4797,7 +4797,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
4797 4797 omap_setup_dsp_mapping(omap15xx_dsp_mm);
4798 4798 omap_setup_mpui_io(s);
4799 4799  
4800   - qemu_register_reset(omap1_mpu_reset, 0, s);
  4800 + qemu_register_reset(omap1_mpu_reset, s);
4801 4801  
4802 4802 return s;
4803 4803 }
... ...
hw/omap2.c
  View file @a08d436
... ... @@ -4868,7 +4868,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
4868 4868 * GPMC registers 6800a000 6800afff
4869 4869 */
4870 4870  
4871   - qemu_register_reset(omap2_mpu_reset, 0, s);
  4871 + qemu_register_reset(omap2_mpu_reset, s);
4872 4872  
4873 4873 return s;
4874 4874 }
... ...
hw/openpic.c
  View file @a08d436
... ... @@ -1249,7 +1249,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
1249 1249 opp->need_swap = 1;
1250 1250  
1251 1251 register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp);
1252   - qemu_register_reset(openpic_reset, 0, opp);
  1252 + qemu_register_reset(openpic_reset, opp);
1253 1253  
1254 1254 opp->irq_raise = openpic_irq_raise;
1255 1255 opp->reset = openpic_reset;
... ... @@ -1709,7 +1709,7 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
1709 1709 mpp->reset = mpic_reset;
1710 1710  
1711 1711 register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);
1712   - qemu_register_reset(mpic_reset, 0, mpp);
  1712 + qemu_register_reset(mpic_reset, mpp);
1713 1713 mpp->reset(mpp);
1714 1714  
1715 1715 return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
... ...
hw/parallel.c
  View file @a08d436
... ... @@ -448,7 +448,7 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
448 448 s->irq = irq;
449 449 s->chr = chr;
450 450 parallel_reset(s);
451   - qemu_register_reset(parallel_reset, 0, s);
  451 + qemu_register_reset(parallel_reset, s);
452 452  
453 453 if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
454 454 s->hw_driver = 1;
... ... @@ -541,7 +541,7 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
541 541 s->chr = chr;
542 542 s->it_shift = it_shift;
543 543 parallel_reset(s);
544   - qemu_register_reset(parallel_reset, 0, s);
  544 + qemu_register_reset(parallel_reset, s);
545 545  
546 546 io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
547 547 cpu_register_physical_memory(base, 8 << it_shift, io_sw);
... ...
... ... @@ -84,7 +84,7 @@ static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
84 84 cpu_physical_memory_read(addr, rrd->data, size);
85 85 rrd->addr = addr;
86 86 rrd->size = size;
87   - qemu_register_reset(option_rom_reset, 0, rrd);
  87 + qemu_register_reset(option_rom_reset, rrd);
88 88 }
89 89  
90 90 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
... ... @@ -1115,7 +1115,7 @@ static void pc_init1(ram_addr_t ram_size,
1115 1115 /* APIC reset callback resets cpu */
1116 1116 apic_init(env);
1117 1117 } else {
1118   - qemu_register_reset((QEMUResetHandler*)cpu_reset, 0, env);
  1118 + qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
1119 1119 }
1120 1120 }
1121 1121  
... ...
hw/pci.c
  View file @a08d436
... ... @@ -120,7 +120,7 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
120 120 bus->next = first_bus;
121 121 first_bus = bus;
122 122 register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
123   - qemu_register_reset(pci_bus_reset, 0, bus);
  123 + qemu_register_reset(pci_bus_reset, bus);
124 124 return bus;
125 125 }
126 126  
... ...
hw/pckbd.c
  View file @a08d436
... ... @@ -381,7 +381,7 @@ void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base)
381 381 #ifdef TARGET_I386
382 382 vmmouse_init(s->mouse);
383 383 #endif
384   - qemu_register_reset(kbd_reset, 0, s);
  384 + qemu_register_reset(kbd_reset, s);
385 385 }
386 386  
387 387 /* Memory mapped interface */
... ... @@ -438,5 +438,5 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
438 438 #ifdef TARGET_I386
439 439 vmmouse_init(s->mouse);
440 440 #endif
441   - qemu_register_reset(kbd_reset, 0, s);
  441 + qemu_register_reset(kbd_reset, s);
442 442 }
... ...
hw/petalogix_s3adsp1800_mmu.c
  View file @a08d436
... ... @@ -120,7 +120,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
120 120 env = cpu_init(cpu_model);
121 121  
122 122 env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
123   - qemu_register_reset(main_cpu_reset, 0, env);
  123 + qemu_register_reset(main_cpu_reset, env);
124 124  
125 125 /* Attach emulated BRAM through the LMB. */
126 126 phys_lmb_bram = qemu_ram_alloc(LMB_BRAM_SIZE);
... ...
hw/piix_pci.c
  View file @a08d436
... ... @@ -345,7 +345,7 @@ int piix3_init(PCIBus *bus, int devfn)
345 345 PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
346 346  
347 347 piix3_reset(d);
348   - qemu_register_reset(piix3_reset, 0, d);
  348 + qemu_register_reset(piix3_reset, d);
349 349 return d->devfn;
350 350 }
351 351  
... ... @@ -369,6 +369,6 @@ int piix4_init(PCIBus *bus, int devfn)
369 369  
370 370  
371 371 piix4_reset(d);
372   - qemu_register_reset(piix4_reset, 0, d);
  372 + qemu_register_reset(piix4_reset, d);
373 373 return d->devfn;
374 374 }
... ...
hw/pl181.c
  View file @a08d436
... ... @@ -458,7 +458,7 @@ static void pl181_init(SysBusDevice *dev)
458 458 sysbus_init_irq(dev, &s->irq[1]);
459 459 bd = qdev_init_bdrv(&dev->qdev, IF_SD);
460 460 s->card = sd_init(bd, 0);
461   - qemu_register_reset(pl181_reset, 0, s);
  461 + qemu_register_reset(pl181_reset, s);
462 462 pl181_reset(s);
463 463 /* ??? Save/restore. */
464 464 }
... ...
hw/ppc405_boards.c
  View file @a08d436
... ... @@ -165,7 +165,7 @@ static void ref405ep_fpga_init (uint32_t base)
165 165 ref405ep_fpga_write, fpga);
166 166 cpu_register_physical_memory(base, 0x00000100, fpga_memory);
167 167 ref405ep_fpga_reset(fpga);
168   - qemu_register_reset(&ref405ep_fpga_reset, 0, fpga);
  168 + qemu_register_reset(&ref405ep_fpga_reset, fpga);
169 169 }
170 170  
171 171 static void ref405ep_init (ram_addr_t ram_size,
... ... @@ -489,7 +489,7 @@ static void taihu_cpld_init (uint32_t base)
489 489 taihu_cpld_write, cpld);
490 490 cpu_register_physical_memory(base, 0x00000100, cpld_memory);
491 491 taihu_cpld_reset(cpld);
492   - qemu_register_reset(&taihu_cpld_reset, 0, cpld);
  492 + qemu_register_reset(&taihu_cpld_reset, cpld);
493 493 }
494 494  
495 495 static void taihu_405ep_init(ram_addr_t ram_size,
... ...
hw/ppc405_uc.c
  View file @a08d436
... ... @@ -173,7 +173,7 @@ void ppc4xx_plb_init (CPUState *env)
173 173 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
174 174 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
175 175 ppc4xx_plb_reset(plb);
176   - qemu_register_reset(ppc4xx_plb_reset, 0, plb);
  176 + qemu_register_reset(ppc4xx_plb_reset, plb);
177 177 }
178 178  
179 179 /*****************************************************************************/
... ... @@ -249,7 +249,7 @@ void ppc4xx_pob_init (CPUState *env)
249 249 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
250 250 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
251 251 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
252   - qemu_register_reset(ppc4xx_pob_reset, 0, pob);
  252 + qemu_register_reset(ppc4xx_pob_reset, pob);
253 253 ppc4xx_pob_reset(env);
254 254 }
255 255  
... ... @@ -386,7 +386,7 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
386 386 #endif
387 387 ppc4xx_mmio_register(env, mmio, offset, 0x002,
388 388 opba_read, opba_write, opba);
389   - qemu_register_reset(ppc4xx_opba_reset, 0, opba);
  389 + qemu_register_reset(ppc4xx_opba_reset, opba);
390 390 ppc4xx_opba_reset(opba);
391 391 }
392 392  
... ... @@ -580,7 +580,7 @@ void ppc405_ebc_init (CPUState *env)
580 580  
581 581 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
582 582 ebc_reset(ebc);
583   - qemu_register_reset(&ebc_reset, 0, ebc);
  583 + qemu_register_reset(&ebc_reset, ebc);
584 584 ppc_dcr_register(env, EBC0_CFGADDR,
585 585 ebc, &dcr_read_ebc, &dcr_write_ebc);
586 586 ppc_dcr_register(env, EBC0_CFGDATA,
... ... @@ -672,7 +672,7 @@ void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
672 672 dma = qemu_mallocz(sizeof(ppc405_dma_t));
673 673 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
674 674 ppc405_dma_reset(dma);
675   - qemu_register_reset(&ppc405_dma_reset, 0, dma);
  675 + qemu_register_reset(&ppc405_dma_reset, dma);
676 676 ppc_dcr_register(env, DMA0_CR0,
677 677 dma, &dcr_read_dma, &dcr_write_dma);
678 678 ppc_dcr_register(env, DMA0_CT0,
... ... @@ -837,7 +837,7 @@ void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
837 837 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
838 838 gpio->base = offset;
839 839 ppc405_gpio_reset(gpio);
840   - qemu_register_reset(&ppc405_gpio_reset, 0, gpio);
  840 + qemu_register_reset(&ppc405_gpio_reset, gpio);
841 841 #ifdef DEBUG_GPIO
842 842 printf("%s: offset " PADDRX "\n", __func__, offset);
843 843 #endif
... ... @@ -1028,7 +1028,7 @@ void ppc405_ocm_init (CPUState *env)
1028 1028 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
1029 1029 ocm->offset = qemu_ram_alloc(4096);
1030 1030 ocm_reset(ocm);
1031   - qemu_register_reset(&ocm_reset, 0, ocm);
  1031 + qemu_register_reset(&ocm_reset, ocm);
1032 1032 ppc_dcr_register(env, OCM0_ISARC,
1033 1033 ocm, &dcr_read_ocm, &dcr_write_ocm);
1034 1034 ppc_dcr_register(env, OCM0_ISACNTL,
... ... @@ -1280,7 +1280,7 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
1280 1280 #endif
1281 1281 ppc4xx_mmio_register(env, mmio, offset, 0x011,
1282 1282 i2c_read, i2c_write, i2c);
1283   - qemu_register_reset(ppc4xx_i2c_reset, 0, i2c);
  1283 + qemu_register_reset(ppc4xx_i2c_reset, i2c);
1284 1284 }
1285 1285  
1286 1286 /*****************************************************************************/
... ... @@ -1562,7 +1562,7 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
1562 1562 #endif
1563 1563 ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
1564 1564 gpt_read, gpt_write, gpt);
1565   - qemu_register_reset(ppc4xx_gpt_reset, 0, gpt);
  1565 + qemu_register_reset(ppc4xx_gpt_reset, gpt);
1566 1566 }
1567 1567  
1568 1568 /*****************************************************************************/
... ... @@ -1787,7 +1787,7 @@ void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
1787 1787 for (i = 0; i < 4; i++)
1788 1788 mal->irqs[i] = irqs[i];
1789 1789 ppc40x_mal_reset(mal);
1790   - qemu_register_reset(&ppc40x_mal_reset, 0, mal);
  1790 + qemu_register_reset(&ppc40x_mal_reset, mal);
1791 1791 ppc_dcr_register(env, MAL0_CFG,
1792 1792 mal, &dcr_read_mal, &dcr_write_mal);
1793 1793 ppc_dcr_register(env, MAL0_ESR,
... ... @@ -2171,7 +2171,7 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2171 2171 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2172 2172 &dcr_read_crcpc, &dcr_write_crcpc);
2173 2173 ppc405cr_clk_init(cpc);
2174   - qemu_register_reset(ppc405cr_cpc_reset, 0, cpc);
  2174 + qemu_register_reset(ppc405cr_cpc_reset, cpc);
2175 2175 ppc405cr_cpc_reset(cpc);
2176 2176 }
2177 2177  
... ... @@ -2493,7 +2493,7 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2493 2493 cpc->jtagid = 0x20267049;
2494 2494 cpc->sysclk = sysclk;
2495 2495 ppc405ep_cpc_reset(cpc);
2496   - qemu_register_reset(&ppc405ep_cpc_reset, 0, cpc);
  2496 + qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2497 2497 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2498 2498 &dcr_read_epcpc, &dcr_write_epcpc);
2499 2499 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
... ...
hw/ppc4xx_devs.c
  View file @a08d436
... ... @@ -60,7 +60,7 @@ CPUState *ppc4xx_init (const char *cpu_model,
60 60 tb_clk->opaque = env;
61 61 ppc_dcr_init(env, NULL, NULL);
62 62 /* Register qemu callbacks */
63   - qemu_register_reset(&cpu_ppc_reset, 0, env);
  63 + qemu_register_reset(&cpu_ppc_reset, env);
64 64  
65 65 return env;
66 66 }
... ... @@ -498,7 +498,7 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
498 498 ppc_dcr_register(env, dcr_base + i, uic,
499 499 &dcr_read_uic, &dcr_write_uic);
500 500 }
501   - qemu_register_reset(ppcuic_reset, 0, uic);
  501 + qemu_register_reset(ppcuic_reset, uic);
502 502 ppcuic_reset(uic);
503 503  
504 504 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
... ... @@ -834,7 +834,7 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
834 834 memcpy(sdram->ram_sizes, ram_sizes,
835 835 nbanks * sizeof(target_phys_addr_t));
836 836 sdram_reset(sdram);
837   - qemu_register_reset(&sdram_reset, 0, sdram);
  837 + qemu_register_reset(&sdram_reset, sdram);
838 838 ppc_dcr_register(env, SDRAM0_CFGADDR,
839 839 sdram, &dcr_read_sdram, &dcr_write_sdram);
840 840 ppc_dcr_register(env, SDRAM0_CFGDATA,
... ...
hw/ppc4xx_pci.c
  View file @a08d436
... ... @@ -404,7 +404,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
404 404 goto free;
405 405 cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
406 406  
407   - qemu_register_reset(ppc4xx_pci_reset, 0, controller);
  407 + qemu_register_reset(ppc4xx_pci_reset, controller);
408 408  
409 409 /* XXX load/save code not tested. */
410 410 register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,
... ...
hw/ppc_newworld.c
  View file @a08d436
... ... @@ -128,7 +128,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
128 128 #if 0
129 129 env->osi_call = vga_osi_call;
130 130 #endif
131   - qemu_register_reset(&cpu_ppc_reset, 0, env);
  131 + qemu_register_reset(&cpu_ppc_reset, env);
132 132 envs[i] = env;
133 133 }
134 134  
... ...
hw/ppc_oldworld.c
  View file @a08d436
... ... @@ -154,7 +154,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
154 154 /* Set time-base frequency to 16.6 Mhz */
155 155 cpu_ppc_tb_init(env, 16600000UL);
156 156 env->osi_call = vga_osi_call;
157   - qemu_register_reset(&cpu_ppc_reset, 0, env);
  157 + qemu_register_reset(&cpu_ppc_reset, env);
158 158 envs[i] = env;
159 159 }
160 160  
... ...
hw/ppc_prep.c
  View file @a08d436
... ... @@ -573,7 +573,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
573 573 /* Set time-base frequency to 100 Mhz */
574 574 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
575 575 }
576   - qemu_register_reset(&cpu_ppc_reset, 0, env);
  576 + qemu_register_reset(&cpu_ppc_reset, env);
577 577 envs[i] = env;
578 578 }
579 579  
... ...
hw/ps2.c
  View file @a08d436
... ... @@ -593,7 +593,7 @@ void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg)
593 593 ps2_reset(&s->common);
594 594 register_savevm("ps2kbd", 0, 3, ps2_kbd_save, ps2_kbd_load, s);
595 595 qemu_add_kbd_event_handler(ps2_put_keycode, s);
596   - qemu_register_reset(ps2_reset, 0, &s->common);
  596 + qemu_register_reset(ps2_reset, &s->common);
597 597 return s;
598 598 }
599 599  
... ... @@ -606,6 +606,6 @@ void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg)
606 606 ps2_reset(&s->common);
607 607 register_savevm("ps2mouse", 0, 2, ps2_mouse_save, ps2_mouse_load, s);
608 608 qemu_add_mouse_event_handler(ps2_mouse_event, s, 0, "QEMU PS/2 Mouse");
609   - qemu_register_reset(ps2_reset, 0, &s->common);
  609 + qemu_register_reset(ps2_reset, &s->common);
610 610 return s;
611 611 }
... ...
hw/rc4030.c
  View file @a08d436
... ... @@ -810,7 +810,7 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
810 810 s->timer_irq = timer;
811 811 s->jazz_bus_irq = jazz_bus;
812 812  
813   - qemu_register_reset(rc4030_reset, 0, s);
  813 + qemu_register_reset(rc4030_reset, s);
814 814 register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);
815 815 rc4030_reset(s);
816 816  
... ...
hw/rtl8139.c
  View file @a08d436
... ... @@ -3477,7 +3477,7 @@ static void pci_rtl8139_init(PCIDevice *dev)
3477 3477  
3478 3478 s->pci_dev = (PCIDevice *)d;
3479 3479 qdev_get_macaddr(&dev->qdev, s->macaddr);
3480   - qemu_register_reset(rtl8139_reset, 0, s);
  3480 + qemu_register_reset(rtl8139_reset, s);
3481 3481 rtl8139_reset(s);
3482 3482 s->vc = qdev_get_vlan_client(&dev->qdev,
3483 3483 rtl8139_can_receive, rtl8139_receive, NULL,
... ...
hw/sbi.c
  View file @a08d436
... ... @@ -149,7 +149,7 @@ void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
149 149 cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
150 150  
151 151 register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
152   - qemu_register_reset(sbi_reset, 0, s);
  152 + qemu_register_reset(sbi_reset, s);
153 153 *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
154 154 *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
155 155 sbi_reset(s);
... ...
hw/serial.c
  View file @a08d436
... ... @@ -720,7 +720,7 @@ static void serial_init_core(SerialState *s, qemu_irq irq, int baudbase,
720 720 s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
721 721 s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
722 722  
723   - qemu_register_reset(serial_reset, 0, s);
  723 + qemu_register_reset(serial_reset, s);
724 724 serial_reset(s);
725 725  
726 726 qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
... ...
hw/slavio_intctl.c
  View file @a08d436
... ... @@ -409,7 +409,7 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
409 409  
410 410 register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
411 411 slavio_intctl_load, s);
412   - qemu_register_reset(slavio_intctl_reset, 0, s);
  412 + qemu_register_reset(slavio_intctl_reset, s);
413 413 *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
414 414  
415 415 *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
... ...
hw/slavio_misc.c
  View file @a08d436
... ... @@ -501,7 +501,7 @@ void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
501 501  
502 502 register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
503 503 s);
504   - qemu_register_reset(slavio_misc_reset, 0, s);
  504 + qemu_register_reset(slavio_misc_reset, s);
505 505 slavio_misc_reset(s);
506 506  
507 507 return s;
... ...
hw/slavio_timer.c
  View file @a08d436
... ... @@ -390,7 +390,7 @@ static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
390 390 slavio_timer_io_memory);
391 391 register_savevm("slavio_timer", addr, 3, slavio_timer_save,
392 392 slavio_timer_load, s);
393   - qemu_register_reset(slavio_timer_reset, 0, s);
  393 + qemu_register_reset(slavio_timer_reset, s);
394 394 slavio_timer_reset(s);
395 395  
396 396 return s;
... ...
hw/sparc32_dma.c
  View file @a08d436
... ... @@ -256,7 +256,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
256 256 cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
257 257  
258 258 register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
259   - qemu_register_reset(dma_reset, 0, s);
  259 + qemu_register_reset(dma_reset, s);
260 260 *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
261 261  
262 262 *reset = &s->dev_reset;
... ...
hw/sun4c_intctl.c
  View file @a08d436
... ... @@ -211,7 +211,7 @@ void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
211 211 register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,
212 212 sun4c_intctl_load, s);
213 213  
214   - qemu_register_reset(sun4c_intctl_reset, 0, s);
  214 + qemu_register_reset(sun4c_intctl_reset, s);
215 215 *irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);
216 216  
217 217 sun4c_intctl_reset(s);
... ...
hw/sun4m.c
  View file @a08d436
... ... @@ -418,9 +418,9 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
418 418 cpu_sparc_set_id(env, i);
419 419 envs[i] = env;
420 420 if (i == 0) {
421   - qemu_register_reset(main_cpu_reset, 0, env);
  421 + qemu_register_reset(main_cpu_reset, env);
422 422 } else {
423   - qemu_register_reset(secondary_cpu_reset, 0, env);
  423 + qemu_register_reset(secondary_cpu_reset, env);
424 424 env->halted = 1;
425 425 }
426 426 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
... ... @@ -1208,9 +1208,9 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1208 1208 cpu_sparc_set_id(env, i);
1209 1209 envs[i] = env;
1210 1210 if (i == 0) {
1211   - qemu_register_reset(main_cpu_reset, 0, env);
  1211 + qemu_register_reset(main_cpu_reset, env);
1212 1212 } else {
1213   - qemu_register_reset(secondary_cpu_reset, 0, env);
  1213 + qemu_register_reset(secondary_cpu_reset, env);
1214 1214 env->halted = 1;
1215 1215 }
1216 1216 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
... ... @@ -1430,7 +1430,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1430 1430  
1431 1431 cpu_sparc_set_id(env, 0);
1432 1432  
1433   - qemu_register_reset(main_cpu_reset, 0, env);
  1433 + qemu_register_reset(main_cpu_reset, env);
1434 1434 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1435 1435 env->prom_addr = hwdef->slavio_base;
1436 1436  
... ...
hw/sun4u.c
  View file @a08d436
... ... @@ -374,7 +374,7 @@ static void sun4uv_init(ram_addr_t RAM_size,
374 374 reset_info = qemu_mallocz(sizeof(ResetData));
375 375 reset_info->env = env;
376 376 reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
377   - qemu_register_reset(main_cpu_reset, 0, reset_info);
  377 + qemu_register_reset(main_cpu_reset, reset_info);
378 378 main_cpu_reset(reset_info);
379 379 // Override warm reset address with cold start address
380 380 env->pc = hwdef->prom_addr + 0x20ULL;
... ...
hw/syborg_virtio.c
  View file @a08d436
... ... @@ -260,7 +260,7 @@ static void syborg_virtio_init(SyborgVirtIOProxy *proxy, VirtIODevice *vdev)
260 260  
261 261 proxy->id = ((uint32_t)0x1af4 << 16) | vdev->device_id;
262 262  
263   - qemu_register_reset(virtio_reset, 0, vdev);
  263 + qemu_register_reset(virtio_reset, vdev);
264 264  
265 265 virtio_bind_device(vdev, &syborg_virtio_bindings, proxy);
266 266 }
... ...
hw/tcx.c
  View file @a08d436
... ... @@ -560,7 +560,7 @@ void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height,
560 560 dummy_memory);
561 561  
562 562 register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
563   - qemu_register_reset(tcx_reset, 0, s);
  563 + qemu_register_reset(tcx_reset, s);
564 564 tcx_reset(s);
565 565 qemu_console_resize(s->ds, width, height);
566 566 }
... ...
hw/tsc2005.c
  View file @a08d436
... ... @@ -548,7 +548,7 @@ void *tsc2005_init(qemu_irq pintdav)
548 548 qemu_add_mouse_event_handler(tsc2005_touchscreen_event, s, 1,
549 549 "QEMU TSC2005-driven Touchscreen");
550 550  
551   - qemu_register_reset((void *) tsc2005_reset, 0, s);
  551 + qemu_register_reset((void *) tsc2005_reset, s);
552 552 register_savevm("tsc2005", -1, 0, tsc2005_save, tsc2005_load, s);
553 553  
554 554 return s;
... ...
hw/tsc210x.c
  View file @a08d436
... ... @@ -1143,7 +1143,7 @@ uWireSlave *tsc2102_init(qemu_irq pint)
1143 1143  
1144 1144 AUD_register_card(s->name, &s->card);
1145 1145  
1146   - qemu_register_reset((void *) tsc210x_reset, 0, s);
  1146 + qemu_register_reset((void *) tsc210x_reset, s);
1147 1147 register_savevm(s->name, -1, 0,
1148 1148 tsc210x_save, tsc210x_load, s);
1149 1149  
... ... @@ -1194,7 +1194,7 @@ uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav)
1194 1194  
1195 1195 AUD_register_card(s->name, &s->card);
1196 1196  
1197   - qemu_register_reset((void *) tsc210x_reset, 0, s);
  1197 + qemu_register_reset((void *) tsc210x_reset, s);
1198 1198 register_savevm(s->name, -1, 0, tsc210x_save, tsc210x_load, s);
1199 1199  
1200 1200 return &s->chip;
... ...
hw/unin_pci.c
  View file @a08d436
... ... @@ -266,7 +266,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
266 266 d->config[0x34] = 0x00; // capabilities_pointer
267 267 #endif
268 268 register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
269   - qemu_register_reset(pci_unin_reset, 0, d);
  269 + qemu_register_reset(pci_unin_reset, d);
270 270 pci_unin_reset(d);
271 271  
272 272 return s->bus;
... ...
hw/usb-ohci.c
  View file @a08d436
... ... @@ -1695,7 +1695,7 @@ static void usb_ohci_init(OHCIState *ohci, int num_ports, int devfn,
1695 1695 }
1696 1696  
1697 1697 ohci->async_td = 0;
1698   - qemu_register_reset(ohci_reset, 0, ohci);
  1698 + qemu_register_reset(ohci_reset, ohci);
1699 1699 ohci_reset(ohci);
1700 1700 }
1701 1701  
... ...
hw/usb-uhci.c
  View file @a08d436
... ... @@ -1094,7 +1094,7 @@ void usb_uhci_piix3_init(PCIBus *bus, int devfn)
1094 1094 }
1095 1095 s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s);
1096 1096  
1097   - qemu_register_reset(uhci_reset, 0, s);
  1097 + qemu_register_reset(uhci_reset, s);
1098 1098 uhci_reset(s);
1099 1099  
1100 1100 /* Use region 4 for consistency with real hardware. BSD guests seem
... ... @@ -1129,7 +1129,7 @@ void usb_uhci_piix4_init(PCIBus *bus, int devfn)
1129 1129 }
1130 1130 s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s);
1131 1131  
1132   - qemu_register_reset(uhci_reset, 0, s);
  1132 + qemu_register_reset(uhci_reset, s);
1133 1133 uhci_reset(s);
1134 1134  
1135 1135 /* Use region 4 for consistency with real hardware. BSD guests seem
... ...
hw/vga.c
  View file @a08d436
... ... @@ -2306,7 +2306,7 @@ void vga_init(VGAState *s)
2306 2306 {
2307 2307 int vga_io_memory;
2308 2308  
2309   - qemu_register_reset(vga_reset, 0, s);
  2309 + qemu_register_reset(vga_reset, s);
2310 2310 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2311 2311  
2312 2312 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
... ...
hw/virtio-pci.c
  View file @a08d436
... ... @@ -409,7 +409,7 @@ static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev,
409 409 pci_register_bar(&proxy->pci_dev, 0, size, PCI_ADDRESS_SPACE_IO,
410 410 virtio_map);
411 411  
412   - qemu_register_reset(virtio_pci_reset, 0, proxy);
  412 + qemu_register_reset(virtio_pci_reset, proxy);
413 413  
414 414 virtio_bind_device(vdev, &virtio_pci_bindings, proxy);
415 415 }
... ...
kvm-all.c
  View file @a08d436
... ... @@ -186,7 +186,7 @@ int kvm_init_vcpu(CPUState *env)
186 186  
187 187 ret = kvm_arch_init_vcpu(env);
188 188 if (ret == 0) {
189   - qemu_register_reset(kvm_reset_vcpu, 0, env);
  189 + qemu_register_reset(kvm_reset_vcpu, env);
190 190 ret = kvm_arch_put_registers(env);
191 191 }
192 192 err:
... ...
... ... @@ -3610,7 +3610,6 @@ void vm_start(void)
3610 3610 typedef struct QEMUResetEntry {
3611 3611 QEMUResetHandler *func;
3612 3612 void *opaque;
3613   - int order;
3614 3613 struct QEMUResetEntry *next;
3615 3614 } QEMUResetEntry;
3616 3615  
... ... @@ -3666,18 +3665,16 @@ static void do_vm_stop(int reason)
3666 3665 }
3667 3666 }
3668 3667  
3669   -void qemu_register_reset(QEMUResetHandler *func, int order, void *opaque)
  3668 +void qemu_register_reset(QEMUResetHandler *func, void *opaque)
3670 3669 {
3671 3670 QEMUResetEntry **pre, *re;
3672 3671  
3673 3672 pre = &first_reset_entry;
3674   - while (*pre != NULL && (*pre)->order >= order) {
  3673 + while (*pre != NULL)
3675 3674 pre = &(*pre)->next;
3676   - }
3677 3675 re = qemu_mallocz(sizeof(QEMUResetEntry));
3678 3676 re->func = func;
3679 3677 re->opaque = opaque;
3680   - re->order = order;
3681 3678 re->next = NULL;
3682 3679 *pre = re;
3683 3680 }
... ...