Commit ee6847d19be16c789b8bd4e553b7cd6701ba1245
Committed by
Anthony Liguori
1 parent
f114784f
qdev: rework device properties.
This patch is a major overhaul of the device properties. The properties are saved directly in the device state struct now, the linked list of property values is gone. Advantages: * We don't have to maintain the list with the property values. * The value in the property list and the value actually used by the device can't go out of sync any more (used to happen for the pci.devfn == -1 case) because there is only one place where the value is stored. * A record describing the property is required now, you can't set random properties any more. There are bus-specific and device-specific properties. The former should be used for properties common to all bus drivers. Typical use case is bus addressing, i.e. pci.devfn and i2c.address. Properties have a PropertyInfo struct attached with name, size and function pointers to parse and print properties. A few common property types have PropertyInfos defined in qdev-properties.c. Drivers are free to implement their own very special property parsers if needed. Properties can have default values. If unset they are zero-filled. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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47 changed files
with
922 additions
and
392 deletions
Makefile
... | ... | @@ -108,7 +108,7 @@ obj-y += bt-hci-csr.o |
108 | 108 | obj-y += buffered_file.o migration.o migration-tcp.o net.o qemu-sockets.o |
109 | 109 | obj-y += qemu-char.o aio.o net-checksum.o savevm.o cache-utils.o |
110 | 110 | obj-y += msmouse.o ps2.o |
111 | -obj-y += qdev.o ssi.o | |
111 | +obj-y += qdev.o qdev-properties.o ssi.o | |
112 | 112 | |
113 | 113 | obj-$(CONFIG_BRLAPI) += baum.o |
114 | 114 | ... | ... |
Makefile.hw
hw/arm_sysctl.c
... | ... | @@ -194,7 +194,6 @@ static void arm_sysctl_init1(SysBusDevice *dev) |
194 | 194 | arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); |
195 | 195 | int iomemtype; |
196 | 196 | |
197 | - s->sys_id = qdev_get_prop_int(&dev->qdev, "sys_id", 0); | |
198 | 197 | /* The MPcore bootloader uses these flags to start secondary CPUs. |
199 | 198 | We don't use a bootloader, so do this here. */ |
200 | 199 | s->flags = 3; |
... | ... | @@ -210,15 +209,28 @@ void arm_sysctl_init(uint32_t base, uint32_t sys_id) |
210 | 209 | DeviceState *dev; |
211 | 210 | |
212 | 211 | dev = qdev_create(NULL, "realview_sysctl"); |
213 | - qdev_set_prop_int(dev, "sys_id", sys_id); | |
212 | + qdev_prop_set_uint32(dev, "sys_id", sys_id); | |
214 | 213 | qdev_init(dev); |
215 | 214 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); |
216 | 215 | } |
217 | 216 | |
217 | +static SysBusDeviceInfo arm_sysctl_info = { | |
218 | + .init = arm_sysctl_init1, | |
219 | + .qdev.name = "realview_sysctl", | |
220 | + .qdev.size = sizeof(arm_sysctl_state), | |
221 | + .qdev.props = (Property[]) { | |
222 | + { | |
223 | + .name = "sys_id", | |
224 | + .info = &qdev_prop_uint32, | |
225 | + .offset = offsetof(arm_sysctl_state, sys_id), | |
226 | + }, | |
227 | + {/* end of list */} | |
228 | + } | |
229 | +}; | |
230 | + | |
218 | 231 | static void arm_sysctl_register_devices(void) |
219 | 232 | { |
220 | - sysbus_register_dev("realview_sysctl", sizeof(arm_sysctl_state), | |
221 | - arm_sysctl_init1); | |
233 | + sysbus_register_withprop(&arm_sysctl_info); | |
222 | 234 | } |
223 | 235 | |
224 | 236 | device_init(arm_sysctl_register_devices) | ... | ... |
hw/armv7m.c
... | ... | @@ -127,7 +127,6 @@ static void bitband_init(SysBusDevice *dev) |
127 | 127 | BitBandState *s = FROM_SYSBUS(BitBandState, dev); |
128 | 128 | int iomemtype; |
129 | 129 | |
130 | - s->base = qdev_get_prop_int(&dev->qdev, "base", 0); | |
131 | 130 | iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn, |
132 | 131 | &s->base); |
133 | 132 | sysbus_init_mmio(dev, 0x02000000, iomemtype); |
... | ... | @@ -138,12 +137,12 @@ static void armv7m_bitband_init(void) |
138 | 137 | DeviceState *dev; |
139 | 138 | |
140 | 139 | dev = qdev_create(NULL, "ARM,bitband-memory"); |
141 | - qdev_set_prop_int(dev, "base", 0x20000000); | |
140 | + qdev_prop_set_uint32(dev, "base", 0x20000000); | |
142 | 141 | qdev_init(dev); |
143 | 142 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x22000000); |
144 | 143 | |
145 | 144 | dev = qdev_create(NULL, "ARM,bitband-memory"); |
146 | - qdev_set_prop_int(dev, "base", 0x40000000); | |
145 | + qdev_prop_set_uint32(dev, "base", 0x40000000); | |
147 | 146 | qdev_init(dev); |
148 | 147 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x42000000); |
149 | 148 | } |
... | ... | @@ -238,10 +237,23 @@ qemu_irq *armv7m_init(int flash_size, int sram_size, |
238 | 237 | return pic; |
239 | 238 | } |
240 | 239 | |
240 | +static SysBusDeviceInfo bitband_info = { | |
241 | + .init = bitband_init, | |
242 | + .qdev.name = "ARM,bitband-memory", | |
243 | + .qdev.size = sizeof(BitBandState), | |
244 | + .qdev.props = (Property[]) { | |
245 | + { | |
246 | + .name = "base", | |
247 | + .info = &qdev_prop_hex32, | |
248 | + .offset = offsetof(BitBandState, base), | |
249 | + }, | |
250 | + {/* end of list */} | |
251 | + } | |
252 | +}; | |
253 | + | |
241 | 254 | static void armv7m_register_devices(void) |
242 | 255 | { |
243 | - sysbus_register_dev("ARM,bitband-memory", sizeof(BitBandState), | |
244 | - bitband_init); | |
256 | + sysbus_register_withprop(&bitband_info); | |
245 | 257 | } |
246 | 258 | |
247 | 259 | device_init(armv7m_register_devices) | ... | ... |
hw/axis_dev88.c
... | ... | @@ -297,7 +297,7 @@ void axisdev88_init (ram_addr_t ram_size, |
297 | 297 | cpu_irq = cris_pic_init_cpu(env); |
298 | 298 | dev = qdev_create(NULL, "etraxfs,pic"); |
299 | 299 | /* FIXME: Is there a proper way to signal vectors to the CPU core? */ |
300 | - qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector); | |
300 | + qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector); | |
301 | 301 | qdev_init(dev); |
302 | 302 | s = sysbus_from_qdev(dev); |
303 | 303 | sysbus_mmio_map(s, 0, 0x3001c000); | ... | ... |
hw/cs4231.c
hw/eccmemctl.c
... | ... | @@ -321,7 +321,6 @@ static void ecc_init1(SysBusDevice *dev) |
321 | 321 | ECCState *s = FROM_SYSBUS(ECCState, dev); |
322 | 322 | |
323 | 323 | sysbus_init_irq(dev, &s->irq); |
324 | - s->version = qdev_get_prop_int(&dev->qdev, "version", -1); | |
325 | 324 | s->regs[0] = s->version; |
326 | 325 | ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s); |
327 | 326 | sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory); |
... | ... | @@ -342,7 +341,7 @@ void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
342 | 341 | SysBusDevice *s; |
343 | 342 | |
344 | 343 | dev = qdev_create(NULL, "eccmemctl"); |
345 | - qdev_set_prop_int(dev, "version", version); | |
344 | + qdev_prop_set_uint32(dev, "version", version); | |
346 | 345 | qdev_init(dev); |
347 | 346 | s = sysbus_from_qdev(dev); |
348 | 347 | sysbus_connect_irq(s, 0, irq); |
... | ... | @@ -352,9 +351,25 @@ void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
352 | 351 | } |
353 | 352 | } |
354 | 353 | |
354 | +static SysBusDeviceInfo ecc_info = { | |
355 | + .init = ecc_init1, | |
356 | + .qdev.name = "eccmemctl", | |
357 | + .qdev.size = sizeof(ECCState), | |
358 | + .qdev.props = (Property[]) { | |
359 | + { | |
360 | + .name = "version", | |
361 | + .info = &qdev_prop_uint32, | |
362 | + .offset = offsetof(ECCState, version), | |
363 | + .defval = (uint32_t[]) { -1 }, | |
364 | + }, | |
365 | + {/* end of list */} | |
366 | + } | |
367 | +}; | |
368 | + | |
369 | + | |
355 | 370 | static void ecc_register_devices(void) |
356 | 371 | { |
357 | - sysbus_register_dev("eccmemctl", sizeof(ECCState), ecc_init1); | |
372 | + sysbus_register_withprop(&ecc_info); | |
358 | 373 | } |
359 | 374 | |
360 | 375 | device_init(ecc_register_devices) | ... | ... |
hw/escc.c
... | ... | @@ -120,6 +120,8 @@ struct SerialState { |
120 | 120 | struct ChannelState chn[2]; |
121 | 121 | int it_shift; |
122 | 122 | int mmio_index; |
123 | + uint32_t disabled; | |
124 | + uint32_t frequency; | |
123 | 125 | }; |
124 | 126 | |
125 | 127 | #define SERIAL_CTRL 0 |
... | ... | @@ -732,13 +734,13 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB, |
732 | 734 | SerialState *d; |
733 | 735 | |
734 | 736 | dev = qdev_create(NULL, "escc"); |
735 | - qdev_set_prop_int(dev, "disabled", 0); | |
736 | - qdev_set_prop_int(dev, "frequency", clock); | |
737 | - qdev_set_prop_int(dev, "it_shift", it_shift); | |
738 | - qdev_set_prop_ptr(dev, "chrB", chrB); | |
739 | - qdev_set_prop_ptr(dev, "chrA", chrA); | |
740 | - qdev_set_prop_int(dev, "chnBtype", ser); | |
741 | - qdev_set_prop_int(dev, "chnAtype", ser); | |
737 | + qdev_prop_set_uint32(dev, "disabled", 0); | |
738 | + qdev_prop_set_uint32(dev, "frequency", clock); | |
739 | + qdev_prop_set_uint32(dev, "it_shift", it_shift); | |
740 | + qdev_prop_set_ptr(dev, "chrB", chrB); | |
741 | + qdev_prop_set_ptr(dev, "chrA", chrA); | |
742 | + qdev_prop_set_uint32(dev, "chnBtype", ser); | |
743 | + qdev_prop_set_uint32(dev, "chnAtype", ser); | |
742 | 744 | qdev_init(dev); |
743 | 745 | s = sysbus_from_qdev(dev); |
744 | 746 | sysbus_connect_irq(s, 0, irqA); |
... | ... | @@ -895,13 +897,13 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq, |
895 | 897 | SysBusDevice *s; |
896 | 898 | |
897 | 899 | dev = qdev_create(NULL, "escc"); |
898 | - qdev_set_prop_int(dev, "disabled", disabled); | |
899 | - qdev_set_prop_int(dev, "frequency", clock); | |
900 | - qdev_set_prop_int(dev, "it_shift", it_shift); | |
901 | - qdev_set_prop_ptr(dev, "chrB", NULL); | |
902 | - qdev_set_prop_ptr(dev, "chrA", NULL); | |
903 | - qdev_set_prop_int(dev, "chnBtype", mouse); | |
904 | - qdev_set_prop_int(dev, "chnAtype", kbd); | |
900 | + qdev_prop_set_uint32(dev, "disabled", disabled); | |
901 | + qdev_prop_set_uint32(dev, "frequency", clock); | |
902 | + qdev_prop_set_uint32(dev, "it_shift", it_shift); | |
903 | + qdev_prop_set_ptr(dev, "chrB", NULL); | |
904 | + qdev_prop_set_ptr(dev, "chrA", NULL); | |
905 | + qdev_prop_set_uint32(dev, "chnBtype", mouse); | |
906 | + qdev_prop_set_uint32(dev, "chnAtype", kbd); | |
905 | 907 | qdev_init(dev); |
906 | 908 | s = sysbus_from_qdev(dev); |
907 | 909 | sysbus_connect_irq(s, 0, irq); |
... | ... | @@ -914,19 +916,13 @@ static void escc_init1(SysBusDevice *dev) |
914 | 916 | SerialState *s = FROM_SYSBUS(SerialState, dev); |
915 | 917 | int io; |
916 | 918 | unsigned int i; |
917 | - uint32_t clock, disabled; | |
918 | - | |
919 | - s->it_shift = qdev_get_prop_int(&dev->qdev, "it_shift", 0); | |
920 | - clock = qdev_get_prop_int(&dev->qdev, "frequency", 0); | |
921 | - s->chn[0].chr = qdev_get_prop_ptr(&dev->qdev, "chrB"); | |
922 | - s->chn[1].chr = qdev_get_prop_ptr(&dev->qdev, "chrA"); | |
923 | - disabled = qdev_get_prop_int(&dev->qdev, "disabled", 0); | |
924 | - s->chn[0].disabled = disabled; | |
925 | - s->chn[1].disabled = disabled; | |
919 | + | |
920 | + s->chn[0].disabled = s->disabled; | |
921 | + s->chn[1].disabled = s->disabled; | |
926 | 922 | for (i = 0; i < 2; i++) { |
927 | 923 | sysbus_init_irq(dev, &s->chn[i].irq); |
928 | 924 | s->chn[i].chn = 1 - i; |
929 | - s->chn[i].clock = clock / 2; | |
925 | + s->chn[i].clock = s->frequency / 2; | |
930 | 926 | if (s->chn[i].chr) { |
931 | 927 | qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, |
932 | 928 | serial_receive1, serial_event, &s->chn[i]); |
... | ... | @@ -934,8 +930,6 @@ static void escc_init1(SysBusDevice *dev) |
934 | 930 | } |
935 | 931 | s->chn[0].otherchn = &s->chn[1]; |
936 | 932 | s->chn[1].otherchn = &s->chn[0]; |
937 | - s->chn[0].type = qdev_get_prop_int(&dev->qdev, "chnBtype", 0); | |
938 | - s->chn[1].type = qdev_get_prop_int(&dev->qdev, "chnAtype", 0); | |
939 | 933 | |
940 | 934 | io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s); |
941 | 935 | sysbus_init_mmio(dev, ESCC_SIZE << s->it_shift, io); |
... | ... | @@ -957,15 +951,43 @@ static SysBusDeviceInfo escc_info = { |
957 | 951 | .init = escc_init1, |
958 | 952 | .qdev.name = "escc", |
959 | 953 | .qdev.size = sizeof(SerialState), |
960 | - .qdev.props = (DevicePropList[]) { | |
961 | - {.name = "frequency", .type = PROP_TYPE_INT}, | |
962 | - {.name = "it_shift", .type = PROP_TYPE_INT}, | |
963 | - {.name = "disabled", .type = PROP_TYPE_INT}, | |
964 | - {.name = "chrB", .type = PROP_TYPE_PTR}, | |
965 | - {.name = "chrA", .type = PROP_TYPE_PTR}, | |
966 | - {.name = "chnBtype", .type = PROP_TYPE_INT}, | |
967 | - {.name = "chnAtype", .type = PROP_TYPE_INT}, | |
968 | - {.name = NULL} | |
954 | + .qdev.props = (Property[]) { | |
955 | + { | |
956 | + .name = "frequency", | |
957 | + .info = &qdev_prop_uint32, | |
958 | + .offset = offsetof(SerialState, frequency), | |
959 | + }, | |
960 | + { | |
961 | + .name = "it_shift", | |
962 | + .info = &qdev_prop_uint32, | |
963 | + .offset = offsetof(SerialState, it_shift), | |
964 | + }, | |
965 | + { | |
966 | + .name = "disabled", | |
967 | + .info = &qdev_prop_uint32, | |
968 | + .offset = offsetof(SerialState, disabled), | |
969 | + }, | |
970 | + { | |
971 | + .name = "chrB", | |
972 | + .info = &qdev_prop_ptr, | |
973 | + .offset = offsetof(SerialState, chn[1].chr), | |
974 | + }, | |
975 | + { | |
976 | + .name = "chrA", | |
977 | + .info = &qdev_prop_ptr, | |
978 | + .offset = offsetof(SerialState, chn[0].chr), | |
979 | + }, | |
980 | + { | |
981 | + .name = "chnBtype", | |
982 | + .info = &qdev_prop_uint32, | |
983 | + .offset = offsetof(SerialState, chn[1].type), | |
984 | + }, | |
985 | + { | |
986 | + .name = "chnAtype", | |
987 | + .info = &qdev_prop_uint32, | |
988 | + .offset = offsetof(SerialState, chn[0].type), | |
989 | + }, | |
990 | + {/* end of list */} | |
969 | 991 | } |
970 | 992 | }; |
971 | 993 | ... | ... |
hw/esp.c
... | ... | @@ -650,12 +650,14 @@ void esp_init(target_phys_addr_t espaddr, int it_shift, |
650 | 650 | { |
651 | 651 | DeviceState *dev; |
652 | 652 | SysBusDevice *s; |
653 | + ESPState *esp; | |
653 | 654 | |
654 | 655 | dev = qdev_create(NULL, "esp"); |
655 | - qdev_set_prop_ptr(dev, "dma_memory_read", dma_memory_read); | |
656 | - qdev_set_prop_ptr(dev, "dma_memory_write", dma_memory_write); | |
657 | - qdev_set_prop_ptr(dev, "dma_opaque", dma_opaque); | |
658 | - qdev_set_prop_int(dev, "it_shift", it_shift); | |
656 | + esp = DO_UPCAST(ESPState, busdev.qdev, dev); | |
657 | + esp->dma_memory_read = dma_memory_read; | |
658 | + esp->dma_memory_write = dma_memory_write; | |
659 | + esp->dma_opaque = dma_opaque; | |
660 | + esp->it_shift = it_shift; | |
659 | 661 | qdev_init(dev); |
660 | 662 | s = sysbus_from_qdev(dev); |
661 | 663 | sysbus_connect_irq(s, 0, irq); |
... | ... | @@ -668,11 +670,7 @@ static void esp_init1(SysBusDevice *dev) |
668 | 670 | int esp_io_memory; |
669 | 671 | |
670 | 672 | sysbus_init_irq(dev, &s->irq); |
671 | - s->it_shift = qdev_get_prop_int(&dev->qdev, "it_shift", -1); | |
672 | 673 | assert(s->it_shift != -1); |
673 | - s->dma_memory_read = qdev_get_prop_ptr(&dev->qdev, "dma_memory_read"); | |
674 | - s->dma_memory_write = qdev_get_prop_ptr(&dev->qdev, "dma_memory_write"); | |
675 | - s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma_opaque"); | |
676 | 674 | |
677 | 675 | esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s); |
678 | 676 | sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); | ... | ... |
hw/etraxfs.c
... | ... | @@ -88,7 +88,7 @@ void bareetraxfs_init (ram_addr_t ram_size, |
88 | 88 | cpu_irq = cris_pic_init_cpu(env); |
89 | 89 | dev = qdev_create(NULL, "etraxfs,pic"); |
90 | 90 | /* FIXME: Is there a proper way to signal vectors to the CPU core? */ |
91 | - qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector); | |
91 | + qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector); | |
92 | 92 | qdev_init(dev); |
93 | 93 | s = sysbus_from_qdev(dev); |
94 | 94 | sysbus_mmio_map(s, 0, 0x3001c000); | ... | ... |
hw/etraxfs_pic.c
... | ... | @@ -140,7 +140,6 @@ static void etraxfs_pic_init(SysBusDevice *dev) |
140 | 140 | struct etrax_pic *s = FROM_SYSBUS(typeof (*s), dev); |
141 | 141 | int intr_vect_regs; |
142 | 142 | |
143 | - s->interrupt_vector = qdev_get_prop_ptr(&dev->qdev, "interrupt_vector"); | |
144 | 143 | qdev_init_gpio_in(&dev->qdev, irq_handler, 32); |
145 | 144 | sysbus_init_irq(dev, &s->parent_irq); |
146 | 145 | sysbus_init_irq(dev, &s->parent_nmi); |
... | ... | @@ -149,10 +148,23 @@ static void etraxfs_pic_init(SysBusDevice *dev) |
149 | 148 | sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs); |
150 | 149 | } |
151 | 150 | |
151 | +static SysBusDeviceInfo etraxfs_pic_info = { | |
152 | + .init = etraxfs_pic_init, | |
153 | + .qdev.name = "etraxfs,pic", | |
154 | + .qdev.size = sizeof(struct etrax_pic), | |
155 | + .qdev.props = (Property[]) { | |
156 | + { | |
157 | + .name = "interrupt_vector", | |
158 | + .info = &qdev_prop_ptr, | |
159 | + .offset = offsetof(struct etrax_pic, interrupt_vector), | |
160 | + }, | |
161 | + {/* end of list */} | |
162 | + } | |
163 | +}; | |
164 | + | |
152 | 165 | static void etraxfs_pic_register(void) |
153 | 166 | { |
154 | - sysbus_register_dev("etraxfs,pic", sizeof (struct etrax_pic), | |
155 | - etraxfs_pic_init); | |
167 | + sysbus_register_withprop(&etraxfs_pic_info); | |
156 | 168 | } |
157 | 169 | |
158 | 170 | device_init(etraxfs_pic_register) | ... | ... |
hw/fdc.c
... | ... | @@ -511,6 +511,8 @@ struct fdctrl_t { |
511 | 511 | /* Floppy drives */ |
512 | 512 | fdrive_t drives[MAX_FD]; |
513 | 513 | int reset_sensei; |
514 | + uint32_t strict_io; | |
515 | + uint32_t mem_mapped; | |
514 | 516 | }; |
515 | 517 | |
516 | 518 | static uint32_t fdctrl_read (void *opaque, uint32_t reg) |
... | ... | @@ -1898,9 +1900,9 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, |
1898 | 1900 | fdctrl_t *fdctrl; |
1899 | 1901 | |
1900 | 1902 | dev = qdev_create(NULL, "fdc"); |
1901 | - qdev_set_prop_int(dev, "strict_io", 0); | |
1902 | - qdev_set_prop_int(dev, "mem_mapped", mem_mapped); | |
1903 | - qdev_set_prop_int(dev, "sun4m", 0); | |
1903 | + qdev_prop_set_uint32(dev, "strict_io", 0); | |
1904 | + qdev_prop_set_uint32(dev, "mem_mapped", mem_mapped); | |
1905 | + qdev_prop_set_uint32(dev, "sun4m", 0); | |
1904 | 1906 | qdev_init(dev); |
1905 | 1907 | s = sysbus_from_qdev(dev); |
1906 | 1908 | sysbus_connect_irq(s, 0, irq); |
... | ... | @@ -1931,9 +1933,9 @@ fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base, |
1931 | 1933 | fdctrl_t *fdctrl; |
1932 | 1934 | |
1933 | 1935 | dev = qdev_create(NULL, "fdc"); |
1934 | - qdev_set_prop_int(dev, "strict_io", 1); | |
1935 | - qdev_set_prop_int(dev, "mem_mapped", 1); | |
1936 | - qdev_set_prop_int(dev, "sun4m", 1); | |
1936 | + qdev_prop_set_uint32(dev, "strict_io", 1); | |
1937 | + qdev_prop_set_uint32(dev, "mem_mapped", 1); | |
1938 | + qdev_prop_set_uint32(dev, "sun4m", 1); | |
1937 | 1939 | qdev_init(dev); |
1938 | 1940 | s = sysbus_from_qdev(dev); |
1939 | 1941 | sysbus_connect_irq(s, 0, irq); |
... | ... | @@ -1953,7 +1955,7 @@ static void fdc_init1(SysBusDevice *dev) |
1953 | 1955 | |
1954 | 1956 | sysbus_init_irq(dev, &s->irq); |
1955 | 1957 | qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); |
1956 | - if (qdev_get_prop_int(&dev->qdev, "strict_io", 0)) { | |
1958 | + if (s->strict_io) { | |
1957 | 1959 | io = cpu_register_io_memory(fdctrl_mem_read_strict, |
1958 | 1960 | fdctrl_mem_write_strict, s); |
1959 | 1961 | } else { |
... | ... | @@ -1967,12 +1969,28 @@ static SysBusDeviceInfo fdc_info = { |
1967 | 1969 | .init = fdc_init1, |
1968 | 1970 | .qdev.name = "fdc", |
1969 | 1971 | .qdev.size = sizeof(fdctrl_t), |
1970 | - .qdev.props = (DevicePropList[]) { | |
1971 | - {.name = "io_base", .type = PROP_TYPE_INT}, | |
1972 | - {.name = "strict_io", .type = PROP_TYPE_INT}, | |
1973 | - {.name = "mem_mapped", .type = PROP_TYPE_INT}, | |
1974 | - {.name = "sun4m", .type = PROP_TYPE_INT}, | |
1975 | - {.name = NULL} | |
1972 | + .qdev.props = (Property[]) { | |
1973 | + { | |
1974 | + .name = "io_base", | |
1975 | + .info = &qdev_prop_uint32, | |
1976 | + .offset = offsetof(fdctrl_t, io_base), | |
1977 | + }, | |
1978 | + { | |
1979 | + .name = "strict_io", | |
1980 | + .info = &qdev_prop_uint32, | |
1981 | + .offset = offsetof(fdctrl_t, strict_io), | |
1982 | + }, | |
1983 | + { | |
1984 | + .name = "mem_mapped", | |
1985 | + .info = &qdev_prop_uint32, | |
1986 | + .offset = offsetof(fdctrl_t, mem_mapped), | |
1987 | + }, | |
1988 | + { | |
1989 | + .name = "sun4m", | |
1990 | + .info = &qdev_prop_uint32, | |
1991 | + .offset = offsetof(fdctrl_t, sun4m), | |
1992 | + }, | |
1993 | + {/* end of properties */} | |
1976 | 1994 | } |
1977 | 1995 | }; |
1978 | 1996 | ... | ... |
hw/i2c.c
... | ... | @@ -20,6 +20,14 @@ struct i2c_bus |
20 | 20 | static struct BusInfo i2c_bus_info = { |
21 | 21 | .name = "I2C", |
22 | 22 | .size = sizeof(i2c_bus), |
23 | + .props = (Property[]) { | |
24 | + { | |
25 | + .name = "address", | |
26 | + .info = &qdev_prop_uint32, | |
27 | + .offset = offsetof(struct i2c_slave, address), | |
28 | + }, | |
29 | + {/* end of list */} | |
30 | + } | |
23 | 31 | }; |
24 | 32 | |
25 | 33 | static void i2c_bus_save(QEMUFile *f, void *opaque) |
... | ... | @@ -151,7 +159,6 @@ static void i2c_slave_qdev_init(DeviceState *dev, DeviceInfo *base) |
151 | 159 | i2c_slave *s = I2C_SLAVE_FROM_QDEV(dev); |
152 | 160 | |
153 | 161 | s->info = info; |
154 | - s->address = qdev_get_prop_int(dev, "address", 0); | |
155 | 162 | |
156 | 163 | info->init(s); |
157 | 164 | } |
... | ... | @@ -169,7 +176,7 @@ DeviceState *i2c_create_slave(i2c_bus *bus, const char *name, int addr) |
169 | 176 | DeviceState *dev; |
170 | 177 | |
171 | 178 | dev = qdev_create(&bus->qbus, name); |
172 | - qdev_set_prop_int(dev, "address", addr); | |
179 | + qdev_prop_set_uint32(dev, "address", addr); | |
173 | 180 | qdev_init(dev); |
174 | 181 | return dev; |
175 | 182 | } | ... | ... |
hw/i2c.h
hw/integratorcp.c
... | ... | @@ -17,6 +17,7 @@ |
17 | 17 | |
18 | 18 | typedef struct { |
19 | 19 | SysBusDevice busdev; |
20 | + uint32_t memsz; | |
20 | 21 | uint32_t flash_offset; |
21 | 22 | uint32_t cm_osc; |
22 | 23 | uint32_t cm_ctrl; |
... | ... | @@ -230,23 +231,21 @@ static void integratorcm_init(SysBusDevice *dev) |
230 | 231 | { |
231 | 232 | int iomemtype; |
232 | 233 | integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev); |
233 | - int memsz; | |
234 | 234 | |
235 | - memsz = qdev_get_prop_int(&dev->qdev, "memsz", 0); | |
236 | 235 | s->cm_osc = 0x01000048; |
237 | 236 | /* ??? What should the high bits of this value be? */ |
238 | 237 | s->cm_auxosc = 0x0007feff; |
239 | 238 | s->cm_sdram = 0x00011122; |
240 | - if (memsz >= 256) { | |
239 | + if (s->memsz >= 256) { | |
241 | 240 | integrator_spd[31] = 64; |
242 | 241 | s->cm_sdram |= 0x10; |
243 | - } else if (memsz >= 128) { | |
242 | + } else if (s->memsz >= 128) { | |
244 | 243 | integrator_spd[31] = 32; |
245 | 244 | s->cm_sdram |= 0x0c; |
246 | - } else if (memsz >= 64) { | |
245 | + } else if (s->memsz >= 64) { | |
247 | 246 | integrator_spd[31] = 16; |
248 | 247 | s->cm_sdram |= 0x08; |
249 | - } else if (memsz >= 32) { | |
248 | + } else if (s->memsz >= 32) { | |
250 | 249 | integrator_spd[31] = 4; |
251 | 250 | s->cm_sdram |= 0x04; |
252 | 251 | } else { |
... | ... | @@ -475,7 +474,7 @@ static void integratorcp_init(ram_addr_t ram_size, |
475 | 474 | cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM); |
476 | 475 | |
477 | 476 | dev = qdev_create(NULL, "integrator_core"); |
478 | - qdev_set_prop_int(dev, "memsz", ram_size >> 20); | |
477 | + qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); | |
479 | 478 | qdev_init(dev); |
480 | 479 | sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); |
481 | 480 | |
... | ... | @@ -522,11 +521,24 @@ static void integratorcp_machine_init(void) |
522 | 521 | |
523 | 522 | machine_init(integratorcp_machine_init); |
524 | 523 | |
524 | +static SysBusDeviceInfo core_info = { | |
525 | + .init = integratorcm_init, | |
526 | + .qdev.name = "integrator_core", | |
527 | + .qdev.size = sizeof(integratorcm_state), | |
528 | + .qdev.props = (Property[]) { | |
529 | + { | |
530 | + .name = "memsz", | |
531 | + .info = &qdev_prop_uint32, | |
532 | + .offset = offsetof(integratorcm_state, memsz), | |
533 | + }, | |
534 | + {/* end of list */} | |
535 | + } | |
536 | +}; | |
537 | + | |
525 | 538 | static void integratorcp_register_devices(void) |
526 | 539 | { |
527 | 540 | sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init); |
528 | - sysbus_register_dev("integrator_core", sizeof(integratorcm_state), | |
529 | - integratorcm_init); | |
541 | + sysbus_register_withprop(&core_info); | |
530 | 542 | } |
531 | 543 | |
532 | 544 | device_init(integratorcp_register_devices) | ... | ... |
hw/iommu.c
... | ... | @@ -373,7 +373,7 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
373 | 373 | IOMMUState *d; |
374 | 374 | |
375 | 375 | dev = qdev_create(NULL, "iommu"); |
376 | - qdev_set_prop_int(dev, "version", version); | |
376 | + qdev_prop_set_uint32(dev, "version", version); | |
377 | 377 | qdev_init(dev); |
378 | 378 | s = sysbus_from_qdev(dev); |
379 | 379 | sysbus_connect_irq(s, 0, irq); |
... | ... | @@ -391,8 +391,6 @@ static void iommu_init1(SysBusDevice *dev) |
391 | 391 | |
392 | 392 | sysbus_init_irq(dev, &s->irq); |
393 | 393 | |
394 | - s->version = qdev_get_prop_int(&dev->qdev, "version", 0); | |
395 | - | |
396 | 394 | io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s); |
397 | 395 | sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io); |
398 | 396 | |
... | ... | @@ -405,9 +403,13 @@ static SysBusDeviceInfo iommu_info = { |
405 | 403 | .init = iommu_init1, |
406 | 404 | .qdev.name = "iommu", |
407 | 405 | .qdev.size = sizeof(IOMMUState), |
408 | - .qdev.props = (DevicePropList[]) { | |
409 | - {.name = "version", .type = PROP_TYPE_INT}, | |
410 | - {.name = NULL} | |
406 | + .qdev.props = (Property[]) { | |
407 | + { | |
408 | + .name = "version", | |
409 | + .info = &qdev_prop_uint32, | |
410 | + .offset = offsetof(IOMMUState, version), | |
411 | + }, | |
412 | + {/* end of property list */} | |
411 | 413 | } |
412 | 414 | }; |
413 | 415 | ... | ... |
hw/m48t59.c
... | ... | @@ -43,11 +43,11 @@ |
43 | 43 | struct m48t59_t { |
44 | 44 | SysBusDevice busdev; |
45 | 45 | /* Model parameters */ |
46 | - int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 | |
46 | + uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 | |
47 | 47 | /* Hardware parameters */ |
48 | 48 | qemu_irq IRQ; |
49 | 49 | uint32_t io_base; |
50 | - uint16_t size; | |
50 | + uint32_t size; | |
51 | 51 | /* RTC management */ |
52 | 52 | time_t time_offset; |
53 | 53 | time_t stop_time; |
... | ... | @@ -623,9 +623,9 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, |
623 | 623 | m48t59_t *d; |
624 | 624 | |
625 | 625 | dev = qdev_create(NULL, "m48t59"); |
626 | - qdev_set_prop_int(dev, "type", type); | |
627 | - qdev_set_prop_int(dev, "size", size); | |
628 | - qdev_set_prop_int(dev, "io_base", io_base); | |
626 | + qdev_prop_set_uint32(dev, "type", type); | |
627 | + qdev_prop_set_uint32(dev, "size", size); | |
628 | + qdev_prop_set_uint32(dev, "io_base", io_base); | |
629 | 629 | qdev_init(dev); |
630 | 630 | s = sysbus_from_qdev(dev); |
631 | 631 | sysbus_connect_irq(s, 0, IRQ); |
... | ... | @@ -647,11 +647,8 @@ static void m48t59_init1(SysBusDevice *dev) |
647 | 647 | m48t59_t *s = FROM_SYSBUS(m48t59_t, dev); |
648 | 648 | int mem_index; |
649 | 649 | |
650 | - s->size = qdev_get_prop_int(&dev->qdev, "size", -1); | |
651 | 650 | s->buffer = qemu_mallocz(s->size); |
652 | 651 | sysbus_init_irq(dev, &s->IRQ); |
653 | - s->io_base = qdev_get_prop_int(&dev->qdev, "io_base", 0); | |
654 | - s->type = qdev_get_prop_int(&dev->qdev, "type", -1); | |
655 | 652 | |
656 | 653 | mem_index = cpu_register_io_memory(nvram_read, nvram_write, s); |
657 | 654 | sysbus_init_mmio(dev, s->size, mem_index); |
... | ... | @@ -666,9 +663,33 @@ static void m48t59_init1(SysBusDevice *dev) |
666 | 663 | register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s); |
667 | 664 | } |
668 | 665 | |
666 | +static SysBusDeviceInfo m48t59_info = { | |
667 | + .init = m48t59_init1, | |
668 | + .qdev.name = "m48t59", | |
669 | + .qdev.size = sizeof(m48t59_t), | |
670 | + .qdev.props = (Property[]) { | |
671 | + { | |
672 | + .name = "size", | |
673 | + .info = &qdev_prop_uint32, | |
674 | + .offset = offsetof(m48t59_t, size), | |
675 | + .defval = (uint32_t[]) { -1 }, | |
676 | + },{ | |
677 | + .name = "type", | |
678 | + .info = &qdev_prop_uint32, | |
679 | + .offset = offsetof(m48t59_t, type), | |
680 | + .defval = (uint32_t[]) { -1 }, | |
681 | + },{ | |
682 | + .name = "io_base", | |
683 | + .info = &qdev_prop_hex32, | |
684 | + .offset = offsetof(m48t59_t, io_base), | |
685 | + }, | |
686 | + {/* end of list */} | |
687 | + } | |
688 | +}; | |
689 | + | |
669 | 690 | static void m48t59_register_devices(void) |
670 | 691 | { |
671 | - sysbus_register_dev("m48t59", sizeof(m48t59_t), m48t59_init1); | |
692 | + sysbus_register_withprop(&m48t59_info); | |
672 | 693 | } |
673 | 694 | |
674 | 695 | device_init(m48t59_register_devices) | ... | ... |
hw/mips_malta.c
... | ... | @@ -914,8 +914,8 @@ void mips_malta_init (ram_addr_t ram_size, |
914 | 914 | /* TODO: Populate SPD eeprom data. */ |
915 | 915 | DeviceState *eeprom; |
916 | 916 | eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); |
917 | - qdev_set_prop_int(eeprom, "address", 0x50 + i); | |
918 | - qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256)); | |
917 | + qdev_prop_set_uint32(eeprom, "address", 0x50 + i); | |
918 | + qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); | |
919 | 919 | qdev_init(eeprom); |
920 | 920 | } |
921 | 921 | pit = pit_init(0x40, i8259[0]); | ... | ... |
hw/musicpal.c
... | ... | @@ -1578,7 +1578,7 @@ static void musicpal_init(ram_addr_t ram_size, |
1578 | 1578 | |
1579 | 1579 | qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
1580 | 1580 | dev = qdev_create(NULL, "mv88w8618_eth"); |
1581 | - qdev_set_netdev(dev, &nd_table[0]); | |
1581 | + dev->nd = &nd_table[0]; | |
1582 | 1582 | qdev_init(dev); |
1583 | 1583 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE); |
1584 | 1584 | sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]); | ... | ... |
hw/pc.c
... | ... | @@ -1402,8 +1402,8 @@ static void pc_init1(ram_addr_t ram_size, |
1402 | 1402 | for (i = 0; i < 8; i++) { |
1403 | 1403 | DeviceState *eeprom; |
1404 | 1404 | eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); |
1405 | - qdev_set_prop_int(eeprom, "address", 0x50 + i); | |
1406 | - qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256)); | |
1405 | + qdev_prop_set_uint32(eeprom, "address", 0x50 + i); | |
1406 | + qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); | |
1407 | 1407 | qdev_init(eeprom); |
1408 | 1408 | } |
1409 | 1409 | } | ... | ... |
hw/pci.c
... | ... | @@ -59,6 +59,15 @@ static struct BusInfo pci_bus_info = { |
59 | 59 | .name = "PCI", |
60 | 60 | .size = sizeof(PCIBus), |
61 | 61 | .print_dev = pcibus_dev_print, |
62 | + .props = (Property[]) { | |
63 | + { | |
64 | + .name = "devfn", | |
65 | + .info = &qdev_prop_uint32, | |
66 | + .offset = offsetof(PCIDevice, devfn), | |
67 | + .defval = (uint32_t[]) { -1 }, | |
68 | + }, | |
69 | + {/* end of list */} | |
70 | + } | |
62 | 71 | }; |
63 | 72 | |
64 | 73 | static void pci_update_mappings(PCIDevice *d); |
... | ... | @@ -770,7 +779,7 @@ PCIDevice *pci_create(const char *name, const char *devaddr) |
770 | 779 | } |
771 | 780 | |
772 | 781 | dev = qdev_create(&bus->qbus, name); |
773 | - qdev_set_prop_int(dev, "devfn", devfn); | |
782 | + qdev_prop_set_uint32(dev, "devfn", devfn); | |
774 | 783 | return (PCIDevice *)dev; |
775 | 784 | } |
776 | 785 | |
... | ... | @@ -813,7 +822,7 @@ PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
813 | 822 | if (strcmp(nd->model, pci_nic_models[i]) == 0) { |
814 | 823 | pci_dev = pci_create(pci_nic_names[i], devaddr); |
815 | 824 | dev = &pci_dev->qdev; |
816 | - qdev_set_netdev(dev, nd); | |
825 | + dev->nd = nd; | |
817 | 826 | qdev_init(dev); |
818 | 827 | nd->private = dev; |
819 | 828 | return pci_dev; |
... | ... | @@ -891,7 +900,7 @@ static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
891 | 900 | int devfn; |
892 | 901 | |
893 | 902 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
894 | - devfn = qdev_get_prop_int(qdev, "devfn", -1); | |
903 | + devfn = pci_dev->devfn; | |
895 | 904 | pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
896 | 905 | info->config_read, info->config_write); |
897 | 906 | assert(pci_dev); |
... | ... | @@ -918,7 +927,7 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
918 | 927 | DeviceState *dev; |
919 | 928 | |
920 | 929 | dev = qdev_create(&bus->qbus, name); |
921 | - qdev_set_prop_int(dev, "devfn", devfn); | |
930 | + qdev_prop_set_uint32(dev, "devfn", devfn); | |
922 | 931 | qdev_init(dev); |
923 | 932 | |
924 | 933 | return (PCIDevice *)dev; | ... | ... |
hw/pcnet.c
... | ... | @@ -2128,8 +2128,6 @@ static void lance_init(SysBusDevice *dev) |
2128 | 2128 | s->mmio_index = |
2129 | 2129 | cpu_register_io_memory(lance_mem_read, lance_mem_write, d); |
2130 | 2130 | |
2131 | - s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma"); | |
2132 | - | |
2133 | 2131 | qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1); |
2134 | 2132 | |
2135 | 2133 | sysbus_init_mmio(dev, 4, s->mmio_index); |
... | ... | @@ -2141,6 +2139,21 @@ static void lance_init(SysBusDevice *dev) |
2141 | 2139 | |
2142 | 2140 | pcnet_common_init(&dev->qdev, s, lance_cleanup); |
2143 | 2141 | } |
2142 | + | |
2143 | +static SysBusDeviceInfo lance_info = { | |
2144 | + .init = lance_init, | |
2145 | + .qdev.name = "lance", | |
2146 | + .qdev.size = sizeof(SysBusPCNetState), | |
2147 | + .qdev.props = (Property[]) { | |
2148 | + { | |
2149 | + .name = "dma", | |
2150 | + .info = &qdev_prop_ptr, | |
2151 | + .offset = offsetof(SysBusPCNetState, state.dma_opaque), | |
2152 | + }, | |
2153 | + {/* end of list */} | |
2154 | + } | |
2155 | +}; | |
2156 | + | |
2144 | 2157 | #endif /* TARGET_SPARC */ |
2145 | 2158 | |
2146 | 2159 | static PCIDeviceInfo pcnet_info = { |
... | ... | @@ -2153,7 +2166,7 @@ static void pcnet_register_devices(void) |
2153 | 2166 | { |
2154 | 2167 | pci_qdev_register(&pcnet_info); |
2155 | 2168 | #if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) |
2156 | - sysbus_register_dev("lance", sizeof(SysBusPCNetState), lance_init); | |
2169 | + sysbus_register_withprop(&lance_info); | |
2157 | 2170 | #endif |
2158 | 2171 | } |
2159 | 2172 | ... | ... |
hw/qdev-addr.c
0 โ 100644
1 | +#include "qdev.h" | |
2 | +#include "qdev-addr.h" | |
3 | +#include "targphys.h" | |
4 | + | |
5 | +/* --- target physical address --- */ | |
6 | + | |
7 | +static int parse_taddr(DeviceState *dev, Property *prop, const char *str) | |
8 | +{ | |
9 | + target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop); | |
10 | + | |
11 | + *ptr = strtoull(str, NULL, 16); | |
12 | + return 0; | |
13 | +} | |
14 | + | |
15 | +static int print_taddr(DeviceState *dev, Property *prop, char *dest, size_t len) | |
16 | +{ | |
17 | + target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop); | |
18 | + return snprintf(dest, len, "0x" TARGET_FMT_plx, *ptr); | |
19 | +} | |
20 | + | |
21 | +PropertyInfo qdev_prop_taddr = { | |
22 | + .name = "taddr", | |
23 | + .type = PROP_TYPE_TADDR, | |
24 | + .size = sizeof(target_phys_addr_t), | |
25 | + .parse = parse_taddr, | |
26 | + .print = print_taddr, | |
27 | +}; | |
28 | + | |
29 | +void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value) | |
30 | +{ | |
31 | + qdev_prop_set(dev, name, &value, PROP_TYPE_TADDR); | |
32 | +} | ... | ... |
hw/qdev-addr.h
0 โ 100644
hw/qdev-properties.c
0 โ 100644
1 | +#include "qdev.h" | |
2 | + | |
3 | +void *qdev_get_prop_ptr(DeviceState *dev, Property *prop) | |
4 | +{ | |
5 | + void *ptr = dev; | |
6 | + ptr += prop->offset; | |
7 | + return ptr; | |
8 | +} | |
9 | + | |
10 | +/* --- 16bit integer --- */ | |
11 | + | |
12 | +static int parse_uint16(DeviceState *dev, Property *prop, const char *str) | |
13 | +{ | |
14 | + uint16_t *ptr = qdev_get_prop_ptr(dev, prop); | |
15 | + const char *fmt; | |
16 | + | |
17 | + /* accept both hex and decimal */ | |
18 | + fmt = strncasecmp(str, "0x",2) == 0 ? "%" PRIx16 : "%" PRIu16; | |
19 | + if (sscanf(str, fmt, ptr) != 1) | |
20 | + return -1; | |
21 | + return 0; | |
22 | +} | |
23 | + | |
24 | +static int print_uint16(DeviceState *dev, Property *prop, char *dest, size_t len) | |
25 | +{ | |
26 | + uint16_t *ptr = qdev_get_prop_ptr(dev, prop); | |
27 | + return snprintf(dest, len, "%" PRIu16, *ptr); | |
28 | +} | |
29 | + | |
30 | +PropertyInfo qdev_prop_uint16 = { | |
31 | + .name = "uint16", | |
32 | + .type = PROP_TYPE_UINT16, | |
33 | + .size = sizeof(uint16_t), | |
34 | + .parse = parse_uint16, | |
35 | + .print = print_uint16, | |
36 | +}; | |
37 | + | |
38 | +/* --- 32bit integer --- */ | |
39 | + | |
40 | +static int parse_uint32(DeviceState *dev, Property *prop, const char *str) | |
41 | +{ | |
42 | + uint32_t *ptr = qdev_get_prop_ptr(dev, prop); | |
43 | + const char *fmt; | |
44 | + | |
45 | + /* accept both hex and decimal */ | |
46 | + fmt = strncasecmp(str, "0x",2) == 0 ? "%" PRIx32 : "%" PRIu32; | |
47 | + if (sscanf(str, fmt, ptr) != 1) | |
48 | + return -1; | |
49 | + return 0; | |
50 | +} | |
51 | + | |
52 | +static int print_uint32(DeviceState *dev, Property *prop, char *dest, size_t len) | |
53 | +{ | |
54 | + uint32_t *ptr = qdev_get_prop_ptr(dev, prop); | |
55 | + return snprintf(dest, len, "%" PRIu32, *ptr); | |
56 | +} | |
57 | + | |
58 | +PropertyInfo qdev_prop_uint32 = { | |
59 | + .name = "uint32", | |
60 | + .type = PROP_TYPE_UINT32, | |
61 | + .size = sizeof(uint32_t), | |
62 | + .parse = parse_uint32, | |
63 | + .print = print_uint32, | |
64 | +}; | |
65 | + | |
66 | +/* --- 32bit hex value --- */ | |
67 | + | |
68 | +static int parse_hex32(DeviceState *dev, Property *prop, const char *str) | |
69 | +{ | |
70 | + uint32_t *ptr = qdev_get_prop_ptr(dev, prop); | |
71 | + | |
72 | + if (sscanf(str, "%" PRIx32, ptr) != 1) | |
73 | + return -1; | |
74 | + return 0; | |
75 | +} | |
76 | + | |
77 | +static int print_hex32(DeviceState *dev, Property *prop, char *dest, size_t len) | |
78 | +{ | |
79 | + uint32_t *ptr = qdev_get_prop_ptr(dev, prop); | |
80 | + return snprintf(dest, len, "0x%" PRIx32, *ptr); | |
81 | +} | |
82 | + | |
83 | +PropertyInfo qdev_prop_hex32 = { | |
84 | + .name = "hex32", | |
85 | + .type = PROP_TYPE_UINT32, | |
86 | + .size = sizeof(uint32_t), | |
87 | + .parse = parse_hex32, | |
88 | + .print = print_hex32, | |
89 | +}; | |
90 | + | |
91 | +/* --- pointer --- */ | |
92 | + | |
93 | +static int print_ptr(DeviceState *dev, Property *prop, char *dest, size_t len) | |
94 | +{ | |
95 | + void **ptr = qdev_get_prop_ptr(dev, prop); | |
96 | + return snprintf(dest, len, "<%p>", *ptr); | |
97 | +} | |
98 | + | |
99 | +PropertyInfo qdev_prop_ptr = { | |
100 | + .name = "ptr", | |
101 | + .type = PROP_TYPE_PTR, | |
102 | + .size = sizeof(void*), | |
103 | + .print = print_ptr, | |
104 | +}; | |
105 | + | |
106 | +/* --- mac address --- */ | |
107 | + | |
108 | +/* | |
109 | + * accepted syntax versions: | |
110 | + * 01:02:03:04:05:06 | |
111 | + * 01-02-03-04-05-06 | |
112 | + */ | |
113 | +static int parse_mac(DeviceState *dev, Property *prop, const char *str) | |
114 | +{ | |
115 | + uint8_t *mac = qdev_get_prop_ptr(dev, prop); | |
116 | + int i, pos; | |
117 | + char *p; | |
118 | + | |
119 | + for (i = 0, pos = 0; i < 6; i++, pos += 3) { | |
120 | + if (!isxdigit(str[pos])) | |
121 | + return -1; | |
122 | + if (!isxdigit(str[pos+1])) | |
123 | + return -1; | |
124 | + if (i == 5 && str[pos+2] != '\0') | |
125 | + return -1; | |
126 | + if (str[pos+2] != ':' && str[pos+2] != '-') | |
127 | + return -1; | |
128 | + mac[i] = strtol(str+pos, &p, 16); | |
129 | + } | |
130 | + return 0; | |
131 | +} | |
132 | + | |
133 | +static int print_mac(DeviceState *dev, Property *prop, char *dest, size_t len) | |
134 | +{ | |
135 | + uint8_t *mac = qdev_get_prop_ptr(dev, prop); | |
136 | + return snprintf(dest, len, "%02x:%02x:%02x:%02x:%02x:%02x", | |
137 | + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); | |
138 | +} | |
139 | + | |
140 | +PropertyInfo qdev_prop_macaddr = { | |
141 | + .name = "mac-addr", | |
142 | + .type = PROP_TYPE_MACADDR, | |
143 | + .size = 6, | |
144 | + .parse = parse_mac, | |
145 | + .print = print_mac, | |
146 | +}; | |
147 | + | |
148 | +/* --- public helpers --- */ | |
149 | + | |
150 | +static Property *qdev_prop_walk(Property *props, const char *name) | |
151 | +{ | |
152 | + if (!props) | |
153 | + return NULL; | |
154 | + while (props->name) { | |
155 | + if (strcmp(props->name, name) == 0) | |
156 | + return props; | |
157 | + props++; | |
158 | + } | |
159 | + return NULL; | |
160 | +} | |
161 | + | |
162 | +static Property *qdev_prop_find(DeviceState *dev, const char *name) | |
163 | +{ | |
164 | + Property *prop; | |
165 | + | |
166 | + /* device properties */ | |
167 | + prop = qdev_prop_walk(dev->info->props, name); | |
168 | + if (prop) | |
169 | + return prop; | |
170 | + | |
171 | + /* bus properties */ | |
172 | + prop = qdev_prop_walk(dev->parent_bus->info->props, name); | |
173 | + if (prop) | |
174 | + return prop; | |
175 | + | |
176 | + return NULL; | |
177 | +} | |
178 | + | |
179 | +int qdev_prop_parse(DeviceState *dev, const char *name, const char *value) | |
180 | +{ | |
181 | + Property *prop; | |
182 | + | |
183 | + prop = qdev_prop_find(dev, name); | |
184 | + if (!prop) { | |
185 | + fprintf(stderr, "property \"%s.%s\" not found\n", | |
186 | + dev->info->name, name); | |
187 | + return -1; | |
188 | + } | |
189 | + if (!prop->info->parse) { | |
190 | + fprintf(stderr, "property \"%s.%s\" has no parser\n", | |
191 | + dev->info->name, name); | |
192 | + return -1; | |
193 | + } | |
194 | + return prop->info->parse(dev, prop, value); | |
195 | +} | |
196 | + | |
197 | +void qdev_prop_set(DeviceState *dev, const char *name, void *src, enum PropertyType type) | |
198 | +{ | |
199 | + Property *prop; | |
200 | + void *dst; | |
201 | + | |
202 | + prop = qdev_prop_find(dev, name); | |
203 | + if (!prop) { | |
204 | + fprintf(stderr, "%s: property \"%s.%s\" not found\n", | |
205 | + __FUNCTION__, dev->info->name, name); | |
206 | + abort(); | |
207 | + } | |
208 | + if (prop->info->type != type) { | |
209 | + fprintf(stderr, "%s: property \"%s.%s\" type mismatch\n", | |
210 | + __FUNCTION__, dev->info->name, name); | |
211 | + abort(); | |
212 | + } | |
213 | + dst = qdev_get_prop_ptr(dev, prop); | |
214 | + memcpy(dst, src, prop->info->size); | |
215 | +} | |
216 | + | |
217 | +void qdev_prop_set_uint16(DeviceState *dev, const char *name, uint16_t value) | |
218 | +{ | |
219 | + qdev_prop_set(dev, name, &value, PROP_TYPE_UINT16); | |
220 | +} | |
221 | + | |
222 | +void qdev_prop_set_uint32(DeviceState *dev, const char *name, uint32_t value) | |
223 | +{ | |
224 | + qdev_prop_set(dev, name, &value, PROP_TYPE_UINT32); | |
225 | +} | |
226 | + | |
227 | +void qdev_prop_set_ptr(DeviceState *dev, const char *name, void *value) | |
228 | +{ | |
229 | + qdev_prop_set(dev, name, &value, PROP_TYPE_PTR); | |
230 | +} | |
231 | + | |
232 | +void qdev_prop_set_defaults(DeviceState *dev, Property *props) | |
233 | +{ | |
234 | + char *dst; | |
235 | + | |
236 | + if (!props) | |
237 | + return; | |
238 | + while (props->name) { | |
239 | + if (props->defval) { | |
240 | + dst = qdev_get_prop_ptr(dev, props); | |
241 | + memcpy(dst, props->defval, props->info->size); | |
242 | + } | |
243 | + props++; | |
244 | + } | |
245 | +} | |
246 | + | ... | ... |
hw/qdev.c
... | ... | @@ -30,16 +30,6 @@ |
30 | 30 | #include "sysemu.h" |
31 | 31 | #include "monitor.h" |
32 | 32 | |
33 | -struct DeviceProperty { | |
34 | - const char *name; | |
35 | - DevicePropType type; | |
36 | - union { | |
37 | - uint64_t i; | |
38 | - void *ptr; | |
39 | - } value; | |
40 | - DeviceProperty *next; | |
41 | -}; | |
42 | - | |
43 | 33 | /* This is a nasty hack to allow passing a NULL bus to qdev_create. */ |
44 | 34 | static BusState *main_system_bus; |
45 | 35 | extern struct BusInfo system_bus_info; |
... | ... | @@ -85,6 +75,8 @@ DeviceState *qdev_create(BusState *bus, const char *name) |
85 | 75 | dev = qemu_mallocz(info->size); |
86 | 76 | dev->info = info; |
87 | 77 | dev->parent_bus = bus; |
78 | + qdev_prop_set_defaults(dev, dev->info->props); | |
79 | + qdev_prop_set_defaults(dev, dev->parent_bus->info->props); | |
88 | 80 | LIST_INSERT_HEAD(&bus->children, dev, sibling); |
89 | 81 | return dev; |
90 | 82 | } |
... | ... | @@ -104,52 +96,6 @@ void qdev_free(DeviceState *dev) |
104 | 96 | free(dev); |
105 | 97 | } |
106 | 98 | |
107 | -static DeviceProperty *create_prop(DeviceState *dev, const char *name, | |
108 | - DevicePropType type) | |
109 | -{ | |
110 | - DeviceProperty *prop; | |
111 | - | |
112 | - /* TODO: Check for duplicate properties. */ | |
113 | - prop = qemu_mallocz(sizeof(*prop)); | |
114 | - prop->name = qemu_strdup(name); | |
115 | - prop->type = type; | |
116 | - prop->next = dev->props; | |
117 | - dev->props = prop; | |
118 | - | |
119 | - return prop; | |
120 | -} | |
121 | - | |
122 | -void qdev_set_prop_int(DeviceState *dev, const char *name, uint64_t value) | |
123 | -{ | |
124 | - DeviceProperty *prop; | |
125 | - | |
126 | - prop = create_prop(dev, name, PROP_TYPE_INT); | |
127 | - prop->value.i = value; | |
128 | -} | |
129 | - | |
130 | -void qdev_set_prop_dev(DeviceState *dev, const char *name, DeviceState *value) | |
131 | -{ | |
132 | - DeviceProperty *prop; | |
133 | - | |
134 | - prop = create_prop(dev, name, PROP_TYPE_DEV); | |
135 | - prop->value.ptr = value; | |
136 | -} | |
137 | - | |
138 | -void qdev_set_prop_ptr(DeviceState *dev, const char *name, void *value) | |
139 | -{ | |
140 | - DeviceProperty *prop; | |
141 | - | |
142 | - prop = create_prop(dev, name, PROP_TYPE_PTR); | |
143 | - prop->value.ptr = value; | |
144 | -} | |
145 | - | |
146 | -void qdev_set_netdev(DeviceState *dev, NICInfo *nd) | |
147 | -{ | |
148 | - assert(!dev->nd); | |
149 | - dev->nd = nd; | |
150 | -} | |
151 | - | |
152 | - | |
153 | 99 | /* Get a character (serial) device interface. */ |
154 | 100 | CharDriverState *qdev_init_chardev(DeviceState *dev) |
155 | 101 | { |
... | ... | @@ -168,52 +114,6 @@ BusState *qdev_get_parent_bus(DeviceState *dev) |
168 | 114 | return dev->parent_bus; |
169 | 115 | } |
170 | 116 | |
171 | -static DeviceProperty *find_prop(DeviceState *dev, const char *name, | |
172 | - DevicePropType type) | |
173 | -{ | |
174 | - DeviceProperty *prop; | |
175 | - | |
176 | - for (prop = dev->props; prop; prop = prop->next) { | |
177 | - if (strcmp(prop->name, name) == 0) { | |
178 | - assert (prop->type == type); | |
179 | - return prop; | |
180 | - } | |
181 | - } | |
182 | - return NULL; | |
183 | -} | |
184 | - | |
185 | -uint64_t qdev_get_prop_int(DeviceState *dev, const char *name, uint64_t def) | |
186 | -{ | |
187 | - DeviceProperty *prop; | |
188 | - | |
189 | - prop = find_prop(dev, name, PROP_TYPE_INT); | |
190 | - if (!prop) { | |
191 | - return def; | |
192 | - } | |
193 | - | |
194 | - return prop->value.i; | |
195 | -} | |
196 | - | |
197 | -void *qdev_get_prop_ptr(DeviceState *dev, const char *name) | |
198 | -{ | |
199 | - DeviceProperty *prop; | |
200 | - | |
201 | - prop = find_prop(dev, name, PROP_TYPE_PTR); | |
202 | - assert(prop); | |
203 | - return prop->value.ptr; | |
204 | -} | |
205 | - | |
206 | -DeviceState *qdev_get_prop_dev(DeviceState *dev, const char *name) | |
207 | -{ | |
208 | - DeviceProperty *prop; | |
209 | - | |
210 | - prop = find_prop(dev, name, PROP_TYPE_DEV); | |
211 | - if (!prop) { | |
212 | - return NULL; | |
213 | - } | |
214 | - return prop->value.ptr; | |
215 | -} | |
216 | - | |
217 | 117 | void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n) |
218 | 118 | { |
219 | 119 | assert(dev->num_gpio_in == 0); |
... | ... | @@ -326,9 +226,24 @@ BusState *qbus_create(BusInfo *info, DeviceState *parent, const char *name) |
326 | 226 | #define qdev_printf(fmt, ...) monitor_printf(mon, "%*s" fmt, indent, "", ## __VA_ARGS__) |
327 | 227 | static void qbus_print(Monitor *mon, BusState *bus, int indent); |
328 | 228 | |
229 | +static void qdev_print_props(Monitor *mon, DeviceState *dev, Property *props, | |
230 | + const char *prefix, int indent) | |
231 | +{ | |
232 | + char buf[64]; | |
233 | + | |
234 | + if (!props) | |
235 | + return; | |
236 | + while (props->name) { | |
237 | + if (props->info->print) { | |
238 | + props->info->print(dev, props, buf, sizeof(buf)); | |
239 | + qdev_printf("%s-prop: %s = %s\n", prefix, props->name, buf); | |
240 | + } | |
241 | + props++; | |
242 | + } | |
243 | +} | |
244 | + | |
329 | 245 | static void qdev_print(Monitor *mon, DeviceState *dev, int indent) |
330 | 246 | { |
331 | - DeviceProperty *prop; | |
332 | 247 | BusState *child; |
333 | 248 | qdev_printf("dev: %s\n", dev->info->name); |
334 | 249 | indent += 2; |
... | ... | @@ -338,24 +253,8 @@ static void qdev_print(Monitor *mon, DeviceState *dev, int indent) |
338 | 253 | if (dev->num_gpio_out) { |
339 | 254 | qdev_printf("gpio-out %d\n", dev->num_gpio_out); |
340 | 255 | } |
341 | - for (prop = dev->props; prop; prop = prop->next) { | |
342 | - switch (prop->type) { | |
343 | - case PROP_TYPE_INT: | |
344 | - qdev_printf("prop-int %s 0x%" PRIx64 "\n", prop->name, | |
345 | - prop->value.i); | |
346 | - break; | |
347 | - case PROP_TYPE_PTR: | |
348 | - qdev_printf("prop-ptr %s\n", prop->name); | |
349 | - break; | |
350 | - case PROP_TYPE_DEV: | |
351 | - qdev_printf("prop-dev %s %s\n", prop->name, | |
352 | - ((DeviceState *)prop->value.ptr)->info->name); | |
353 | - break; | |
354 | - default: | |
355 | - qdev_printf("prop-unknown%d %s\n", prop->type, prop->name); | |
356 | - break; | |
357 | - } | |
358 | - } | |
256 | + qdev_print_props(mon, dev, dev->info->props, "dev", indent); | |
257 | + qdev_print_props(mon, dev, dev->parent_bus->info->props, "bus", indent); | |
359 | 258 | if (dev->parent_bus->info->print_dev) |
360 | 259 | dev->parent_bus->info->print_dev(mon, dev, indent); |
361 | 260 | LIST_FOREACH(child, &dev->child_bus, sibling) { | ... | ... |
hw/qdev.h
... | ... | @@ -4,9 +4,11 @@ |
4 | 4 | #include "hw.h" |
5 | 5 | #include "sys-queue.h" |
6 | 6 | |
7 | -typedef struct DeviceInfo DeviceInfo; | |
7 | +typedef struct Property Property; | |
8 | + | |
9 | +typedef struct PropertyInfo PropertyInfo; | |
8 | 10 | |
9 | -typedef struct DeviceProperty DeviceProperty; | |
11 | +typedef struct DeviceInfo DeviceInfo; | |
10 | 12 | |
11 | 13 | typedef struct BusState BusState; |
12 | 14 | |
... | ... | @@ -17,7 +19,6 @@ typedef struct BusInfo BusInfo; |
17 | 19 | struct DeviceState { |
18 | 20 | DeviceInfo *info; |
19 | 21 | BusState *parent_bus; |
20 | - DeviceProperty *props; | |
21 | 22 | int num_gpio_out; |
22 | 23 | qemu_irq *gpio_out; |
23 | 24 | int num_gpio_in; |
... | ... | @@ -32,6 +33,7 @@ struct BusInfo { |
32 | 33 | const char *name; |
33 | 34 | size_t size; |
34 | 35 | bus_dev_printfn print_dev; |
36 | + Property *props; | |
35 | 37 | }; |
36 | 38 | |
37 | 39 | struct BusState { |
... | ... | @@ -42,18 +44,36 @@ struct BusState { |
42 | 44 | LIST_ENTRY(BusState) sibling; |
43 | 45 | }; |
44 | 46 | |
47 | +struct Property { | |
48 | + const char *name; | |
49 | + PropertyInfo *info; | |
50 | + int offset; | |
51 | + void *defval; | |
52 | +}; | |
53 | + | |
54 | +enum PropertyType { | |
55 | + PROP_TYPE_UNSPEC = 0, | |
56 | + PROP_TYPE_UINT16, | |
57 | + PROP_TYPE_UINT32, | |
58 | + PROP_TYPE_TADDR, | |
59 | + PROP_TYPE_MACADDR, | |
60 | + PROP_TYPE_PTR, | |
61 | +}; | |
62 | + | |
63 | +struct PropertyInfo { | |
64 | + const char *name; | |
65 | + size_t size; | |
66 | + enum PropertyType type; | |
67 | + int (*parse)(DeviceState *dev, Property *prop, const char *str); | |
68 | + int (*print)(DeviceState *dev, Property *prop, char *dest, size_t len); | |
69 | +}; | |
70 | + | |
45 | 71 | /*** Board API. This should go away once we have a machine config file. ***/ |
46 | 72 | |
47 | 73 | DeviceState *qdev_create(BusState *bus, const char *name); |
48 | 74 | void qdev_init(DeviceState *dev); |
49 | 75 | void qdev_free(DeviceState *dev); |
50 | 76 | |
51 | -/* Set properties between creation and init. */ | |
52 | -void qdev_set_prop_int(DeviceState *dev, const char *name, uint64_t value); | |
53 | -void qdev_set_prop_dev(DeviceState *dev, const char *name, DeviceState *value); | |
54 | -void qdev_set_prop_ptr(DeviceState *dev, const char *name, void *value); | |
55 | -void qdev_set_netdev(DeviceState *dev, NICInfo *nd); | |
56 | - | |
57 | 77 | qemu_irq qdev_get_gpio_in(DeviceState *dev, int n); |
58 | 78 | void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin); |
59 | 79 | |
... | ... | @@ -61,17 +81,6 @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); |
61 | 81 | |
62 | 82 | /*** Device API. ***/ |
63 | 83 | |
64 | -typedef enum { | |
65 | - PROP_TYPE_INT, | |
66 | - PROP_TYPE_PTR, | |
67 | - PROP_TYPE_DEV | |
68 | -} DevicePropType; | |
69 | - | |
70 | -typedef struct { | |
71 | - const char *name; | |
72 | - DevicePropType type; | |
73 | -} DevicePropList; | |
74 | - | |
75 | 84 | typedef void (*qdev_initfn)(DeviceState *dev, DeviceInfo *info); |
76 | 85 | typedef void (*SCSIAttachFn)(DeviceState *host, BlockDriverState *bdrv, |
77 | 86 | int unit); |
... | ... | @@ -79,7 +88,7 @@ typedef void (*SCSIAttachFn)(DeviceState *host, BlockDriverState *bdrv, |
79 | 88 | struct DeviceInfo { |
80 | 89 | const char *name; |
81 | 90 | size_t size; |
82 | - DevicePropList *props; | |
91 | + Property *props; | |
83 | 92 | |
84 | 93 | /* Private to qdev / bus. */ |
85 | 94 | qdev_initfn init; |
... | ... | @@ -99,10 +108,6 @@ void scsi_bus_new(DeviceState *host, SCSIAttachFn attach); |
99 | 108 | CharDriverState *qdev_init_chardev(DeviceState *dev); |
100 | 109 | |
101 | 110 | BusState *qdev_get_parent_bus(DeviceState *dev); |
102 | -uint64_t qdev_get_prop_int(DeviceState *dev, const char *name, uint64_t def); | |
103 | -DeviceState *qdev_get_prop_dev(DeviceState *dev, const char *name); | |
104 | -/* FIXME: Remove opaque pointer properties. */ | |
105 | -void *qdev_get_prop_ptr(DeviceState *dev, const char *name); | |
106 | 111 | |
107 | 112 | /* Convery from a base type to a parent type, with compile time checking. */ |
108 | 113 | #ifdef __GNUC__ |
... | ... | @@ -124,4 +129,22 @@ BusState *qbus_create(BusInfo *info, DeviceState *parent, const char *name); |
124 | 129 | |
125 | 130 | void do_info_qtree(Monitor *mon); |
126 | 131 | |
132 | +/*** qdev-properties.c ***/ | |
133 | + | |
134 | +extern PropertyInfo qdev_prop_uint16; | |
135 | +extern PropertyInfo qdev_prop_uint32; | |
136 | +extern PropertyInfo qdev_prop_hex32; | |
137 | +extern PropertyInfo qdev_prop_ptr; | |
138 | +extern PropertyInfo qdev_prop_macaddr; | |
139 | + | |
140 | +/* Set properties between creation and init. */ | |
141 | +void *qdev_get_prop_ptr(DeviceState *dev, Property *prop); | |
142 | +int qdev_prop_parse(DeviceState *dev, const char *name, const char *value); | |
143 | +void qdev_prop_set(DeviceState *dev, const char *name, void *src, enum PropertyType type); | |
144 | +void qdev_prop_set_uint16(DeviceState *dev, const char *name, uint16_t value); | |
145 | +void qdev_prop_set_uint32(DeviceState *dev, const char *name, uint32_t value); | |
146 | +/* FIXME: Remove opaque pointer properties. */ | |
147 | +void qdev_prop_set_ptr(DeviceState *dev, const char *name, void *value); | |
148 | +void qdev_prop_set_defaults(DeviceState *dev, Property *props); | |
149 | + | |
127 | 150 | #endif | ... | ... |
hw/slavio_intctl.c
... | ... | @@ -69,6 +69,7 @@ typedef struct SLAVIO_INTCTLState { |
69 | 69 | qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS]; |
70 | 70 | const uint32_t *intbit_to_level; |
71 | 71 | uint32_t cputimer_lbit, cputimer_mbit; |
72 | + uint32_t cputimer_bit; | |
72 | 73 | uint32_t pil_out[MAX_CPUS]; |
73 | 74 | SLAVIO_CPUINTCTLState slaves[MAX_CPUS]; |
74 | 75 | } SLAVIO_INTCTLState; |
... | ... | @@ -388,17 +389,15 @@ static void slavio_intctl_reset(void *opaque) |
388 | 389 | static void slavio_intctl_init1(SysBusDevice *dev) |
389 | 390 | { |
390 | 391 | SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev); |
391 | - int io_memory, cputimer; | |
392 | + int io_memory; | |
392 | 393 | unsigned int i, j; |
393 | 394 | |
394 | 395 | qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS); |
395 | 396 | io_memory = cpu_register_io_memory(slavio_intctlm_mem_read, |
396 | 397 | slavio_intctlm_mem_write, s); |
397 | 398 | sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory); |
398 | - s->intbit_to_level = qdev_get_prop_ptr(&dev->qdev, "intbit_to_level"); | |
399 | - cputimer = qdev_get_prop_int(&dev->qdev, "cputimer_bit", -1); | |
400 | - s->cputimer_mbit = 1 << cputimer; | |
401 | - s->cputimer_lbit = 1 << s->intbit_to_level[cputimer]; | |
399 | + s->cputimer_mbit = 1 << s->cputimer_bit; | |
400 | + s->cputimer_lbit = 1 << s->intbit_to_level[s->cputimer_bit]; | |
402 | 401 | |
403 | 402 | for (i = 0; i < MAX_CPUS; i++) { |
404 | 403 | for (j = 0; j < MAX_PILS; j++) { |
... | ... | @@ -427,8 +426,8 @@ DeviceState *slavio_intctl_init(target_phys_addr_t addr, |
427 | 426 | unsigned int i, j; |
428 | 427 | |
429 | 428 | dev = qdev_create(NULL, "slavio_intctl"); |
430 | - qdev_set_prop_ptr(dev, "intbit_to_level", (void *)intbit_to_level); | |
431 | - qdev_set_prop_int(dev, "cputimer_bit", cputimer); | |
429 | + qdev_prop_set_ptr(dev, "intbit_to_level", (void *)intbit_to_level); | |
430 | + qdev_prop_set_uint32(dev, "cputimer_bit", cputimer); | |
432 | 431 | qdev_init(dev); |
433 | 432 | |
434 | 433 | s = sysbus_from_qdev(dev); |
... | ... | @@ -450,10 +449,18 @@ static SysBusDeviceInfo slavio_intctl_info = { |
450 | 449 | .init = slavio_intctl_init1, |
451 | 450 | .qdev.name = "slavio_intctl", |
452 | 451 | .qdev.size = sizeof(SLAVIO_INTCTLState), |
453 | - .qdev.props = (DevicePropList[]) { | |
454 | - {.name = "intbit_to_level", .type = PROP_TYPE_PTR}, | |
455 | - {.name = "cputimer_bit", .type = PROP_TYPE_INT}, | |
456 | - {.name = NULL} | |
452 | + .qdev.props = (Property[]) { | |
453 | + { | |
454 | + .name = "intbit_to_level", | |
455 | + .info = &qdev_prop_ptr, | |
456 | + .offset = offsetof(SLAVIO_INTCTLState, intbit_to_level), | |
457 | + }, | |
458 | + { | |
459 | + .name = "cputimer_bit", | |
460 | + .info = &qdev_prop_uint32, | |
461 | + .offset = offsetof(SLAVIO_INTCTLState, cputimer_bit), | |
462 | + }, | |
463 | + {/* end of property list */} | |
457 | 464 | } |
458 | 465 | }; |
459 | 466 | ... | ... |
hw/slavio_misc.c
... | ... | @@ -564,18 +564,12 @@ static SysBusDeviceInfo slavio_misc_info = { |
564 | 564 | .init = slavio_misc_init1, |
565 | 565 | .qdev.name = "slavio_misc", |
566 | 566 | .qdev.size = sizeof(MiscState), |
567 | - .qdev.props = (DevicePropList[]) { | |
568 | - {.name = NULL} | |
569 | - } | |
570 | 567 | }; |
571 | 568 | |
572 | 569 | static SysBusDeviceInfo apc_info = { |
573 | 570 | .init = apc_init1, |
574 | 571 | .qdev.name = "apc", |
575 | 572 | .qdev.size = sizeof(MiscState), |
576 | - .qdev.props = (DevicePropList[]) { | |
577 | - {.name = NULL} | |
578 | - } | |
579 | 573 | }; |
580 | 574 | |
581 | 575 | static void slavio_misc_register_devices(void) | ... | ... |
hw/slavio_timer.c
... | ... | @@ -374,9 +374,9 @@ static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr, |
374 | 374 | SLAVIO_TIMERState *d; |
375 | 375 | |
376 | 376 | dev = qdev_create(NULL, "slavio_timer"); |
377 | - qdev_set_prop_int(dev, "slave_index", slave_index); | |
378 | - qdev_set_prop_int(dev, "num_slaves", num_slaves); | |
379 | - qdev_set_prop_ptr(dev, "master", master); | |
377 | + qdev_prop_set_uint32(dev, "slave_index", slave_index); | |
378 | + qdev_prop_set_uint32(dev, "num_slaves", num_slaves); | |
379 | + qdev_prop_set_ptr(dev, "master", master); | |
380 | 380 | qdev_init(dev); |
381 | 381 | s = sysbus_from_qdev(dev); |
382 | 382 | sysbus_connect_irq(s, 0, irq); |
... | ... | @@ -394,9 +394,6 @@ static void slavio_timer_init1(SysBusDevice *dev) |
394 | 394 | QEMUBH *bh; |
395 | 395 | |
396 | 396 | sysbus_init_irq(dev, &s->irq); |
397 | - s->num_slaves = qdev_get_prop_int(&dev->qdev, "num_slaves", 0); | |
398 | - s->slave_index = qdev_get_prop_int(&dev->qdev, "slave_index", 0); | |
399 | - s->master = qdev_get_prop_ptr(&dev->qdev, "master"); | |
400 | 397 | |
401 | 398 | if (!s->master || s->slave_index < s->master->num_slaves) { |
402 | 399 | bh = qemu_bh_new(slavio_timer_irq, s); |
... | ... | @@ -438,11 +435,23 @@ static SysBusDeviceInfo slavio_timer_info = { |
438 | 435 | .init = slavio_timer_init1, |
439 | 436 | .qdev.name = "slavio_timer", |
440 | 437 | .qdev.size = sizeof(SLAVIO_TIMERState), |
441 | - .qdev.props = (DevicePropList[]) { | |
442 | - {.name = "num_slaves", .type = PROP_TYPE_INT}, | |
443 | - {.name = "slave_index", .type = PROP_TYPE_INT}, | |
444 | - {.name = "master", .type = PROP_TYPE_PTR}, | |
445 | - {.name = NULL} | |
438 | + .qdev.props = (Property[]) { | |
439 | + { | |
440 | + .name = "num_slaves", | |
441 | + .info = &qdev_prop_uint32, | |
442 | + .offset = offsetof(SLAVIO_TIMERState, num_slaves), | |
443 | + }, | |
444 | + { | |
445 | + .name = "slave_index", | |
446 | + .info = &qdev_prop_uint32, | |
447 | + .offset = offsetof(SLAVIO_TIMERState, slave_index), | |
448 | + }, | |
449 | + { | |
450 | + .name = "master", | |
451 | + .info = &qdev_prop_ptr, | |
452 | + .offset = offsetof(SLAVIO_TIMERState, master), | |
453 | + }, | |
454 | + {/* end of property list */} | |
446 | 455 | } |
447 | 456 | }; |
448 | 457 | ... | ... |
hw/smbus_eeprom.c
... | ... | @@ -99,14 +99,20 @@ static void smbus_eeprom_init(SMBusDevice *dev) |
99 | 99 | { |
100 | 100 | SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *)dev; |
101 | 101 | |
102 | - /* FIXME: Should be a blob rather than a ptr. */ | |
103 | - eeprom->data = qdev_get_prop_ptr(&dev->i2c.qdev, "data"); | |
104 | 102 | eeprom->offset = 0; |
105 | 103 | } |
106 | 104 | |
107 | 105 | static SMBusDeviceInfo smbus_eeprom_info = { |
108 | 106 | .i2c.qdev.name = "smbus-eeprom", |
109 | 107 | .i2c.qdev.size = sizeof(SMBusEEPROMDevice), |
108 | + .i2c.qdev.props = (Property[]) { | |
109 | + { | |
110 | + .name = "data", | |
111 | + .info = &qdev_prop_ptr, | |
112 | + .offset = offsetof(SMBusEEPROMDevice, data), | |
113 | + }, | |
114 | + {/* end of list */} | |
115 | + }, | |
110 | 116 | .init = smbus_eeprom_init, |
111 | 117 | .quick_cmd = eeprom_quick_cmd, |
112 | 118 | .send_byte = eeprom_send_byte, | ... | ... |
hw/smc91c111.c
... | ... | @@ -733,7 +733,7 @@ void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq) |
733 | 733 | |
734 | 734 | qemu_check_nic_model(nd, "smc91c111"); |
735 | 735 | dev = qdev_create(NULL, "smc91c111"); |
736 | - qdev_set_netdev(dev, nd); | |
736 | + dev->nd = nd; | |
737 | 737 | qdev_init(dev); |
738 | 738 | s = sysbus_from_qdev(dev); |
739 | 739 | sysbus_mmio_map(s, 0, base); | ... | ... |
hw/sparc32_dma.c
... | ... | @@ -252,7 +252,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, |
252 | 252 | DMAState *d; |
253 | 253 | |
254 | 254 | dev = qdev_create(NULL, "sparc32_dma"); |
255 | - qdev_set_prop_ptr(dev, "iommu_opaque", iommu); | |
255 | + qdev_prop_set_ptr(dev, "iommu_opaque", iommu); | |
256 | 256 | qdev_init(dev); |
257 | 257 | s = sysbus_from_qdev(dev); |
258 | 258 | sysbus_connect_irq(s, 0, parent_irq); |
... | ... | @@ -271,7 +271,6 @@ static void sparc32_dma_init1(SysBusDevice *dev) |
271 | 271 | int dma_io_memory; |
272 | 272 | |
273 | 273 | sysbus_init_irq(dev, &s->irq); |
274 | - s->iommu = qdev_get_prop_ptr(&dev->qdev, "iommu_opaque"); | |
275 | 274 | |
276 | 275 | dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s); |
277 | 276 | sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory); |
... | ... | @@ -286,9 +285,13 @@ static SysBusDeviceInfo sparc32_dma_info = { |
286 | 285 | .init = sparc32_dma_init1, |
287 | 286 | .qdev.name = "sparc32_dma", |
288 | 287 | .qdev.size = sizeof(DMAState), |
289 | - .qdev.props = (DevicePropList[]) { | |
290 | - {.name = "iommu_opaque", .type = PROP_TYPE_PTR}, | |
291 | - {.name = NULL} | |
288 | + .qdev.props = (Property[]) { | |
289 | + { | |
290 | + .name = "iommu_opaque", | |
291 | + .info = &qdev_prop_ptr, | |
292 | + .offset = offsetof(DMAState, iommu), | |
293 | + }, | |
294 | + {/* end of property list */} | |
292 | 295 | } |
293 | 296 | }; |
294 | 297 | ... | ... |
hw/stellaris.c
... | ... | @@ -1378,7 +1378,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, |
1378 | 1378 | qemu_check_nic_model(&nd_table[0], "stellaris"); |
1379 | 1379 | |
1380 | 1380 | enet = qdev_create(NULL, "stellaris_enet"); |
1381 | - qdev_set_netdev(enet, &nd_table[0]); | |
1381 | + enet->nd = &nd_table[0]; | |
1382 | 1382 | qdev_init(enet); |
1383 | 1383 | sysbus_mmio_map(sysbus_from_qdev(enet), 0, 0x40048000); |
1384 | 1384 | sysbus_connect_irq(sysbus_from_qdev(enet), 0, pic[42]); | ... | ... |
hw/sun4m.c
... | ... | @@ -373,8 +373,7 @@ static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
373 | 373 | qemu_check_nic_model(&nd_table[0], "lance"); |
374 | 374 | |
375 | 375 | dev = qdev_create(NULL, "lance"); |
376 | - qdev_set_netdev(dev, nd); | |
377 | - qdev_set_prop_ptr(dev, "dma", dma_opaque); | |
376 | + dev->nd = nd; | |
378 | 377 | qdev_init(dev); |
379 | 378 | s = sysbus_from_qdev(dev); |
380 | 379 | sysbus_mmio_map(s, 0, leaddr); |
... | ... | @@ -410,9 +409,6 @@ static SysBusDeviceInfo idreg_info = { |
410 | 409 | .init = idreg_init1, |
411 | 410 | .qdev.name = "macio_idreg", |
412 | 411 | .qdev.size = sizeof(SysBusDevice), |
413 | - .qdev.props = (DevicePropList[]) { | |
414 | - {.name = NULL} | |
415 | - } | |
416 | 412 | }; |
417 | 413 | |
418 | 414 | static void idreg_register_devices(void) |
... | ... | @@ -468,8 +464,8 @@ static SysBusDeviceInfo prom_info = { |
468 | 464 | .init = prom_init1, |
469 | 465 | .qdev.name = "openprom", |
470 | 466 | .qdev.size = sizeof(SysBusDevice), |
471 | - .qdev.props = (DevicePropList[]) { | |
472 | - {.name = NULL} | |
467 | + .qdev.props = (Property[]) { | |
468 | + {/* end of property list */} | |
473 | 469 | } |
474 | 470 | }; |
475 | 471 | |
... | ... | @@ -480,12 +476,19 @@ static void prom_register_devices(void) |
480 | 476 | |
481 | 477 | device_init(prom_register_devices); |
482 | 478 | |
479 | +typedef struct RamDevice | |
480 | +{ | |
481 | + SysBusDevice busdev; | |
482 | + uint32_t size; | |
483 | +} RamDevice; | |
484 | + | |
483 | 485 | /* System RAM */ |
484 | 486 | static void ram_init1(SysBusDevice *dev) |
485 | 487 | { |
486 | 488 | ram_addr_t RAM_size, ram_offset; |
489 | + RamDevice *d = FROM_SYSBUS(RamDevice, dev); | |
487 | 490 | |
488 | - RAM_size = qdev_get_prop_int(&dev->qdev, "size", 0); | |
491 | + RAM_size = d->size; | |
489 | 492 | |
490 | 493 | ram_offset = qemu_ram_alloc(RAM_size); |
491 | 494 | sysbus_init_mmio(dev, RAM_size, ram_offset); |
... | ... | @@ -496,6 +499,7 @@ static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, |
496 | 499 | { |
497 | 500 | DeviceState *dev; |
498 | 501 | SysBusDevice *s; |
502 | + RamDevice *d; | |
499 | 503 | |
500 | 504 | /* allocate RAM */ |
501 | 505 | if ((uint64_t)RAM_size > max_mem) { |
... | ... | @@ -506,20 +510,26 @@ static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, |
506 | 510 | exit(1); |
507 | 511 | } |
508 | 512 | dev = qdev_create(NULL, "memory"); |
509 | - qdev_set_prop_int(dev, "size", RAM_size); | |
510 | 513 | qdev_init(dev); |
511 | 514 | s = sysbus_from_qdev(dev); |
512 | 515 | |
516 | + d = FROM_SYSBUS(RamDevice, s); | |
517 | + d->size = RAM_size; | |
518 | + | |
513 | 519 | sysbus_mmio_map(s, 0, addr); |
514 | 520 | } |
515 | 521 | |
516 | 522 | static SysBusDeviceInfo ram_info = { |
517 | 523 | .init = ram_init1, |
518 | 524 | .qdev.name = "memory", |
519 | - .qdev.size = sizeof(SysBusDevice), | |
520 | - .qdev.props = (DevicePropList[]) { | |
521 | - {.name = "size", .type = PROP_TYPE_INT}, | |
522 | - {.name = NULL} | |
525 | + .qdev.size = sizeof(RamDevice), | |
526 | + .qdev.props = (Property[]) { | |
527 | + { | |
528 | + .name = "size", | |
529 | + .info = &qdev_prop_uint32, | |
530 | + .offset = offsetof(RamDevice, size), | |
531 | + }, | |
532 | + {/* end of property list */} | |
523 | 533 | } |
524 | 534 | }; |
525 | 535 | ... | ... |
hw/syborg.c
... | ... | @@ -64,7 +64,7 @@ static void syborg_init(ram_addr_t ram_size, |
64 | 64 | sysbus_create_simple("syborg,rtc", 0xC0001000, NULL); |
65 | 65 | |
66 | 66 | dev = qdev_create(NULL, "syborg,timer"); |
67 | - qdev_set_prop_int(dev, "frequency", 1000000); | |
67 | + qdev_prop_set_uint32(dev, "frequency", 1000000); | |
68 | 68 | qdev_init(dev); |
69 | 69 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xC0002000); |
70 | 70 | sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[1]); |
... | ... | @@ -83,7 +83,7 @@ static void syborg_init(ram_addr_t ram_size, |
83 | 83 | |
84 | 84 | qemu_check_nic_model(&nd_table[0], "virtio"); |
85 | 85 | dev = qdev_create(NULL, "syborg,virtio-net"); |
86 | - qdev_set_netdev(dev, &nd_table[0]); | |
86 | + dev->nd = &nd_table[0]; | |
87 | 87 | qdev_init(dev); |
88 | 88 | s = sysbus_from_qdev(dev); |
89 | 89 | sysbus_mmio_map(s, 0, 0xc000c000); | ... | ... |
hw/syborg_fb.c
... | ... | @@ -76,8 +76,8 @@ typedef struct { |
76 | 76 | |
77 | 77 | uint32_t base; |
78 | 78 | uint32_t pitch; |
79 | - int rows; | |
80 | - int cols; | |
79 | + uint32_t rows; | |
80 | + uint32_t cols; | |
81 | 81 | int blank; |
82 | 82 | int bpp; |
83 | 83 | int rgb; /* 0 = BGR, 1 = RGB */ |
... | ... | @@ -507,41 +507,50 @@ static void syborg_fb_init(SysBusDevice *dev) |
507 | 507 | { |
508 | 508 | SyborgFBState *s = FROM_SYSBUS(SyborgFBState, dev); |
509 | 509 | int iomemtype; |
510 | - int width; | |
511 | - int height; | |
512 | 510 | |
513 | 511 | sysbus_init_irq(dev, &s->irq); |
514 | 512 | iomemtype = cpu_register_io_memory(syborg_fb_readfn, |
515 | 513 | syborg_fb_writefn, s); |
516 | 514 | sysbus_init_mmio(dev, 0x1000, iomemtype); |
517 | 515 | |
518 | - width = qdev_get_prop_int(&dev->qdev, "width", 0); | |
519 | - height = qdev_get_prop_int(&dev->qdev, "height", 0); | |
520 | - | |
521 | 516 | s->ds = graphic_console_init(syborg_fb_update_display, |
522 | 517 | syborg_fb_invalidate_display, |
523 | 518 | NULL, NULL, s); |
524 | 519 | |
525 | - if (width != 0 && height != 0) { | |
526 | - qemu_console_resize(s->ds, width, height); | |
520 | + if (s->cols != 0 && s->rows != 0) { | |
521 | + qemu_console_resize(s->ds, s->cols, s->rows); | |
527 | 522 | } |
528 | 523 | |
529 | - if (!width) | |
530 | - width = ds_get_width(s->ds); | |
531 | - if (!height) | |
532 | - height = ds_get_height(s->ds); | |
533 | - | |
534 | - s->cols = width; | |
535 | - s->rows = height; | |
524 | + if (!s->cols) | |
525 | + s->cols = ds_get_width(s->ds); | |
526 | + if (!s->rows) | |
527 | + s->rows = ds_get_height(s->ds); | |
536 | 528 | |
537 | 529 | register_savevm("syborg_framebuffer", -1, 1, |
538 | 530 | syborg_fb_save, syborg_fb_load, s); |
539 | 531 | } |
540 | 532 | |
533 | +static SysBusDeviceInfo syborg_fb_info = { | |
534 | + .init = syborg_fb_init, | |
535 | + .qdev.name = "syborg,framebuffer", | |
536 | + .qdev.size = sizeof(SyborgFBState), | |
537 | + .qdev.props = (Property[]) { | |
538 | + { | |
539 | + .name = "width", | |
540 | + .info = &qdev_prop_uint32, | |
541 | + .offset = offsetof(SyborgFBState, cols), | |
542 | + },{ | |
543 | + .name = "height", | |
544 | + .info = &qdev_prop_uint32, | |
545 | + .offset = offsetof(SyborgFBState, rows), | |
546 | + }, | |
547 | + {/* end of list */} | |
548 | + } | |
549 | +}; | |
550 | + | |
541 | 551 | static void syborg_fb_register_devices(void) |
542 | 552 | { |
543 | - sysbus_register_dev("syborg,framebuffer", sizeof(SyborgFBState), | |
544 | - syborg_fb_init); | |
553 | + sysbus_register_withprop(&syborg_fb_info); | |
545 | 554 | } |
546 | 555 | |
547 | 556 | device_init(syborg_fb_register_devices) | ... | ... |
hw/syborg_interrupt.c
... | ... | @@ -56,7 +56,7 @@ typedef struct { |
56 | 56 | typedef struct { |
57 | 57 | SysBusDevice busdev; |
58 | 58 | int pending_count; |
59 | - int num_irqs; | |
59 | + uint32_t num_irqs; | |
60 | 60 | syborg_int_flags *flags; |
61 | 61 | qemu_irq parent_irq; |
62 | 62 | } SyborgIntState; |
... | ... | @@ -208,7 +208,6 @@ static void syborg_int_init(SysBusDevice *dev) |
208 | 208 | int iomemtype; |
209 | 209 | |
210 | 210 | sysbus_init_irq(dev, &s->parent_irq); |
211 | - s->num_irqs = qdev_get_prop_int(&dev->qdev, "num-interrupts", 64); | |
212 | 211 | qdev_init_gpio_in(&dev->qdev, syborg_int_set_irq, s->num_irqs); |
213 | 212 | iomemtype = cpu_register_io_memory(syborg_int_readfn, |
214 | 213 | syborg_int_writefn, s); |
... | ... | @@ -218,10 +217,24 @@ static void syborg_int_init(SysBusDevice *dev) |
218 | 217 | register_savevm("syborg_int", -1, 1, syborg_int_save, syborg_int_load, s); |
219 | 218 | } |
220 | 219 | |
220 | +static SysBusDeviceInfo syborg_int_info = { | |
221 | + .init = syborg_int_init, | |
222 | + .qdev.name = "syborg,interrupt", | |
223 | + .qdev.size = sizeof(SyborgIntState), | |
224 | + .qdev.props = (Property[]) { | |
225 | + { | |
226 | + .name = "num-interrupts", | |
227 | + .info = &qdev_prop_uint32, | |
228 | + .offset = offsetof(SyborgIntState, num_irqs), | |
229 | + .defval = (uint32_t[]) { 64 }, | |
230 | + }, | |
231 | + {/* end of list */} | |
232 | + } | |
233 | +}; | |
234 | + | |
221 | 235 | static void syborg_interrupt_register_devices(void) |
222 | 236 | { |
223 | - sysbus_register_dev("syborg,interrupt", sizeof(SyborgIntState), | |
224 | - syborg_int_init); | |
237 | + sysbus_register_withprop(&syborg_int_info); | |
225 | 238 | } |
226 | 239 | |
227 | 240 | device_init(syborg_interrupt_register_devices) | ... | ... |
hw/syborg_keyboard.c
... | ... | @@ -53,7 +53,7 @@ typedef struct { |
53 | 53 | SysBusDevice busdev; |
54 | 54 | int int_enabled; |
55 | 55 | int extension_bit; |
56 | - int fifo_size; | |
56 | + uint32_t fifo_size; | |
57 | 57 | uint32_t *key_fifo; |
58 | 58 | int read_pos, read_count; |
59 | 59 | qemu_irq irq; |
... | ... | @@ -212,7 +212,6 @@ static void syborg_keyboard_init(SysBusDevice *dev) |
212 | 212 | iomemtype = cpu_register_io_memory(syborg_keyboard_readfn, |
213 | 213 | syborg_keyboard_writefn, s); |
214 | 214 | sysbus_init_mmio(dev, 0x1000, iomemtype); |
215 | - s->fifo_size = qdev_get_prop_int(&dev->qdev, "fifo-size", 16); | |
216 | 215 | if (s->fifo_size <= 0) { |
217 | 216 | fprintf(stderr, "syborg_keyboard: fifo too small\n"); |
218 | 217 | s->fifo_size = 16; |
... | ... | @@ -225,10 +224,24 @@ static void syborg_keyboard_init(SysBusDevice *dev) |
225 | 224 | syborg_keyboard_save, syborg_keyboard_load, s); |
226 | 225 | } |
227 | 226 | |
227 | +static SysBusDeviceInfo syborg_keyboard_info = { | |
228 | + .init = syborg_keyboard_init, | |
229 | + .qdev.name = "syborg,keyboard", | |
230 | + .qdev.size = sizeof(SyborgKeyboardState), | |
231 | + .qdev.props = (Property[]) { | |
232 | + { | |
233 | + .name = "fifo-size", | |
234 | + .info = &qdev_prop_uint32, | |
235 | + .offset = offsetof(SyborgKeyboardState, fifo_size), | |
236 | + .defval = (uint32_t[]) { 16 }, | |
237 | + }, | |
238 | + {/* end of list */} | |
239 | + } | |
240 | +}; | |
241 | + | |
228 | 242 | static void syborg_keyboard_register_devices(void) |
229 | 243 | { |
230 | - sysbus_register_dev("syborg,keyboard", sizeof(SyborgKeyboardState), | |
231 | - syborg_keyboard_init); | |
244 | + sysbus_register_withprop(&syborg_keyboard_info); | |
232 | 245 | } |
233 | 246 | |
234 | 247 | device_init(syborg_keyboard_register_devices) | ... | ... |
hw/syborg_pointer.c
... | ... | @@ -45,11 +45,11 @@ typedef struct { |
45 | 45 | typedef struct { |
46 | 46 | SysBusDevice busdev; |
47 | 47 | int int_enabled; |
48 | - int fifo_size; | |
48 | + uint32_t fifo_size; | |
49 | 49 | event_data *event_fifo; |
50 | 50 | int read_pos, read_count; |
51 | 51 | qemu_irq irq; |
52 | - int absolute; | |
52 | + uint32_t absolute; | |
53 | 53 | } SyborgPointerState; |
54 | 54 | |
55 | 55 | static void syborg_pointer_update(SyborgPointerState *s) |
... | ... | @@ -209,8 +209,6 @@ static void syborg_pointer_init(SysBusDevice *dev) |
209 | 209 | syborg_pointer_writefn, s); |
210 | 210 | sysbus_init_mmio(dev, 0x1000, iomemtype); |
211 | 211 | |
212 | - s->absolute = qdev_get_prop_int(&dev->qdev, "absolute", 1); | |
213 | - s->fifo_size = qdev_get_prop_int(&dev->qdev, "fifo-size", 16); | |
214 | 212 | if (s->fifo_size <= 0) { |
215 | 213 | fprintf(stderr, "syborg_pointer: fifo too small\n"); |
216 | 214 | s->fifo_size = 16; |
... | ... | @@ -224,10 +222,29 @@ static void syborg_pointer_init(SysBusDevice *dev) |
224 | 222 | syborg_pointer_save, syborg_pointer_load, s); |
225 | 223 | } |
226 | 224 | |
225 | +static SysBusDeviceInfo syborg_pointer_info = { | |
226 | + .init = syborg_pointer_init, | |
227 | + .qdev.name = "syborg,pointer", | |
228 | + .qdev.size = sizeof(SyborgPointerState), | |
229 | + .qdev.props = (Property[]) { | |
230 | + { | |
231 | + .name = "fifo-size", | |
232 | + .info = &qdev_prop_uint32, | |
233 | + .offset = offsetof(SyborgPointerState, fifo_size), | |
234 | + .defval = (uint32_t[]) { 16 }, | |
235 | + },{ | |
236 | + .name = "absolute", | |
237 | + .info = &qdev_prop_uint32, | |
238 | + .offset = offsetof(SyborgPointerState, absolute), | |
239 | + .defval = (uint32_t[]) { 1 }, | |
240 | + }, | |
241 | + {/* end of list */} | |
242 | + } | |
243 | +}; | |
244 | + | |
227 | 245 | static void syborg_pointer_register_devices(void) |
228 | 246 | { |
229 | - sysbus_register_dev("syborg,pointer", sizeof(SyborgPointerState), | |
230 | - syborg_pointer_init); | |
247 | + sysbus_register_withprop(&syborg_pointer_info); | |
231 | 248 | } |
232 | 249 | |
233 | 250 | device_init(syborg_pointer_register_devices) | ... | ... |
hw/syborg_serial.c
... | ... | @@ -59,7 +59,7 @@ enum { |
59 | 59 | typedef struct { |
60 | 60 | SysBusDevice busdev; |
61 | 61 | uint32_t int_enable; |
62 | - int fifo_size; | |
62 | + uint32_t fifo_size; | |
63 | 63 | uint32_t *read_fifo; |
64 | 64 | int read_pos; |
65 | 65 | int read_count; |
... | ... | @@ -329,7 +329,6 @@ static void syborg_serial_init(SysBusDevice *dev) |
329 | 329 | qemu_chr_add_handlers(s->chr, syborg_serial_can_receive, |
330 | 330 | syborg_serial_receive, syborg_serial_event, s); |
331 | 331 | } |
332 | - s->fifo_size = qdev_get_prop_int(&dev->qdev, "fifo-size", 16); | |
333 | 332 | if (s->fifo_size <= 0) { |
334 | 333 | fprintf(stderr, "syborg_serial: fifo too small\n"); |
335 | 334 | s->fifo_size = 16; |
... | ... | @@ -340,10 +339,24 @@ static void syborg_serial_init(SysBusDevice *dev) |
340 | 339 | syborg_serial_save, syborg_serial_load, s); |
341 | 340 | } |
342 | 341 | |
342 | +static SysBusDeviceInfo syborg_serial_info = { | |
343 | + .init = syborg_serial_init, | |
344 | + .qdev.name = "syborg,serial", | |
345 | + .qdev.size = sizeof(SyborgSerialState), | |
346 | + .qdev.props = (Property[]) { | |
347 | + { | |
348 | + .name = "fifo-size", | |
349 | + .info = &qdev_prop_uint32, | |
350 | + .offset = offsetof(SyborgSerialState, fifo_size), | |
351 | + .defval = (uint32_t[]) { 16 }, | |
352 | + }, | |
353 | + {/* end of list */} | |
354 | + } | |
355 | +}; | |
356 | + | |
343 | 357 | static void syborg_serial_register_devices(void) |
344 | 358 | { |
345 | - sysbus_register_dev("syborg,serial", sizeof(SyborgSerialState), | |
346 | - syborg_serial_init); | |
359 | + sysbus_register_withprop(&syborg_serial_info); | |
347 | 360 | } |
348 | 361 | |
349 | 362 | device_init(syborg_serial_register_devices) | ... | ... |
hw/syborg_timer.c
... | ... | @@ -209,7 +209,6 @@ static void syborg_timer_init(SysBusDevice *dev) |
209 | 209 | QEMUBH *bh; |
210 | 210 | int iomemtype; |
211 | 211 | |
212 | - s->freq = qdev_get_prop_int(&dev->qdev, "frequency", 0); | |
213 | 212 | if (s->freq == 0) { |
214 | 213 | fprintf(stderr, "syborg_timer: Zero/unset frequency\n"); |
215 | 214 | exit(1); |
... | ... | @@ -230,9 +229,13 @@ static SysBusDeviceInfo syborg_timer_info = { |
230 | 229 | .init = syborg_timer_init, |
231 | 230 | .qdev.name = "syborg,timer", |
232 | 231 | .qdev.size = sizeof(SyborgTimerState), |
233 | - .qdev.props = (DevicePropList[]) { | |
234 | - {.name = "frequency", .type = PROP_TYPE_INT}, | |
235 | - {.name = NULL} | |
232 | + .qdev.props = (Property[]) { | |
233 | + { | |
234 | + .name = "frequency", | |
235 | + .info = &qdev_prop_uint32, | |
236 | + .offset = offsetof(SyborgTimerState, freq), | |
237 | + }, | |
238 | + {/* end of list */} | |
236 | 239 | } |
237 | 240 | }; |
238 | 241 | ... | ... |
hw/tcx.c
... | ... | @@ -26,6 +26,7 @@ |
26 | 26 | #include "console.h" |
27 | 27 | #include "pixel_ops.h" |
28 | 28 | #include "sysbus.h" |
29 | +#include "qdev-addr.h" | |
29 | 30 | |
30 | 31 | #define MAXX 1024 |
31 | 32 | #define MAXY 768 |
... | ... | @@ -41,6 +42,7 @@ typedef struct TCXState { |
41 | 42 | uint8_t *vram; |
42 | 43 | uint32_t *vram24, *cplane; |
43 | 44 | ram_addr_t vram_offset, vram24_offset, cplane_offset; |
45 | + uint32_t vram_size; | |
44 | 46 | uint16_t width, height, depth; |
45 | 47 | uint8_t r[256], g[256], b[256]; |
46 | 48 | uint32_t palette[256]; |
... | ... | @@ -520,11 +522,11 @@ void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height, |
520 | 522 | SysBusDevice *s; |
521 | 523 | |
522 | 524 | dev = qdev_create(NULL, "SUNW,tcx"); |
523 | - qdev_set_prop_int(dev, "addr", addr); | |
524 | - qdev_set_prop_int(dev, "vram_size", vram_size); | |
525 | - qdev_set_prop_int(dev, "width", width); | |
526 | - qdev_set_prop_int(dev, "height", height); | |
527 | - qdev_set_prop_int(dev, "depth", depth); | |
525 | + qdev_prop_set_taddr(dev, "addr", addr); | |
526 | + qdev_prop_set_uint32(dev, "vram_size", vram_size); | |
527 | + qdev_prop_set_uint16(dev, "width", width); | |
528 | + qdev_prop_set_uint16(dev, "height", height); | |
529 | + qdev_prop_set_uint16(dev, "depth", depth); | |
528 | 530 | qdev_init(dev); |
529 | 531 | s = sysbus_from_qdev(dev); |
530 | 532 | /* 8-bit plane */ |
... | ... | @@ -551,22 +553,16 @@ static void tcx_init1(SysBusDevice *dev) |
551 | 553 | TCXState *s = FROM_SYSBUS(TCXState, dev); |
552 | 554 | int io_memory, dummy_memory; |
553 | 555 | ram_addr_t vram_offset; |
554 | - int size, vram_size; | |
556 | + int size; | |
555 | 557 | uint8_t *vram_base; |
556 | 558 | |
557 | - vram_size = qdev_get_prop_int(&dev->qdev, "vram_size", -1); | |
558 | - | |
559 | - vram_offset = qemu_ram_alloc(vram_size * (1 + 4 + 4)); | |
559 | + vram_offset = qemu_ram_alloc(s->vram_size * (1 + 4 + 4)); | |
560 | 560 | vram_base = qemu_get_ram_ptr(vram_offset); |
561 | - s->addr = qdev_get_prop_int(&dev->qdev, "addr", -1); | |
562 | 561 | s->vram_offset = vram_offset; |
563 | - s->width = qdev_get_prop_int(&dev->qdev, "width", -1); | |
564 | - s->height = qdev_get_prop_int(&dev->qdev, "height", -1); | |
565 | - s->depth = qdev_get_prop_int(&dev->qdev, "depth", -1); | |
566 | 562 | |
567 | 563 | /* 8-bit plane */ |
568 | 564 | s->vram = vram_base; |
569 | - size = vram_size; | |
565 | + size = s->vram_size; | |
570 | 566 | sysbus_init_mmio(dev, size, s->vram_offset); |
571 | 567 | vram_offset += size; |
572 | 568 | vram_base += size; |
... | ... | @@ -584,7 +580,7 @@ static void tcx_init1(SysBusDevice *dev) |
584 | 580 | |
585 | 581 | if (s->depth == 24) { |
586 | 582 | /* 24-bit plane */ |
587 | - size = vram_size * 4; | |
583 | + size = s->vram_size * 4; | |
588 | 584 | s->vram24 = (uint32_t *)vram_base; |
589 | 585 | s->vram24_offset = vram_offset; |
590 | 586 | sysbus_init_mmio(dev, size, vram_offset); |
... | ... | @@ -592,7 +588,7 @@ static void tcx_init1(SysBusDevice *dev) |
592 | 588 | vram_base += size; |
593 | 589 | |
594 | 590 | /* Control plane */ |
595 | - size = vram_size * 4; | |
591 | + size = s->vram_size * 4; | |
596 | 592 | s->cplane = (uint32_t *)vram_base; |
597 | 593 | s->cplane_offset = vram_offset; |
598 | 594 | sysbus_init_mmio(dev, size, vram_offset); |
... | ... | @@ -678,9 +674,44 @@ static void tcx24_screen_dump(void *opaque, const char *filename) |
678 | 674 | return; |
679 | 675 | } |
680 | 676 | |
677 | +static SysBusDeviceInfo tcx_info = { | |
678 | + .init = tcx_init1, | |
679 | + .qdev.name = "SUNW,tcx", | |
680 | + .qdev.size = sizeof(TCXState), | |
681 | + .qdev.props = (Property[]) { | |
682 | + { | |
683 | + .name = "addr", | |
684 | + .info = &qdev_prop_taddr, | |
685 | + .offset = offsetof(TCXState, addr), | |
686 | + .defval = (target_phys_addr_t[]) { -1 }, | |
687 | + },{ | |
688 | + .name = "vram_size", | |
689 | + .info = &qdev_prop_hex32, | |
690 | + .offset = offsetof(TCXState, vram_size), | |
691 | + .defval = (uint32_t[]) { -1 }, | |
692 | + },{ | |
693 | + .name = "width", | |
694 | + .info = &qdev_prop_uint16, | |
695 | + .offset = offsetof(TCXState, width), | |
696 | + .defval = (uint16_t[]) { -1 }, | |
697 | + },{ | |
698 | + .name = "height", | |
699 | + .info = &qdev_prop_uint16, | |
700 | + .offset = offsetof(TCXState, height), | |
701 | + .defval = (uint16_t[]) { -1 }, | |
702 | + },{ | |
703 | + .name = "depth", | |
704 | + .info = &qdev_prop_uint16, | |
705 | + .offset = offsetof(TCXState, depth), | |
706 | + .defval = (uint16_t[]) { -1 }, | |
707 | + }, | |
708 | + {/* end of list */} | |
709 | + } | |
710 | +}; | |
711 | + | |
681 | 712 | static void tcx_register_devices(void) |
682 | 713 | { |
683 | - sysbus_register_dev("SUNW,tcx", sizeof(TCXState), tcx_init1); | |
714 | + sysbus_register_withprop(&tcx_info); | |
684 | 715 | } |
685 | 716 | |
686 | 717 | device_init(tcx_register_devices) | ... | ... |
hw/xilinx.h
... | ... | @@ -8,7 +8,7 @@ xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr) |
8 | 8 | DeviceState *dev; |
9 | 9 | |
10 | 10 | dev = qdev_create(NULL, "xilinx,intc"); |
11 | - qdev_set_prop_int(dev, "kind-of-intr", kind_of_intr); | |
11 | + qdev_prop_set_uint32(dev, "kind-of-intr", kind_of_intr); | |
12 | 12 | qdev_init(dev); |
13 | 13 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); |
14 | 14 | sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); |
... | ... | @@ -22,8 +22,8 @@ xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int nr, int freq) |
22 | 22 | DeviceState *dev; |
23 | 23 | |
24 | 24 | dev = qdev_create(NULL, "xilinx,timer"); |
25 | - qdev_set_prop_int(dev, "nr-timers", nr); | |
26 | - qdev_set_prop_int(dev, "frequency", freq); | |
25 | + qdev_prop_set_uint32(dev, "nr-timers", nr); | |
26 | + qdev_prop_set_uint32(dev, "frequency", freq); | |
27 | 27 | qdev_init(dev); |
28 | 28 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); |
29 | 29 | sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); |
... | ... | @@ -40,9 +40,9 @@ xilinx_ethlite_create(NICInfo *nd, target_phys_addr_t base, qemu_irq irq, |
40 | 40 | qemu_check_nic_model(nd, "xilinx-ethlite"); |
41 | 41 | |
42 | 42 | dev = qdev_create(NULL, "xilinx,ethlite"); |
43 | - qdev_set_netdev(dev, nd); | |
44 | - qdev_set_prop_int(dev, "txpingpong", txpingpong); | |
45 | - qdev_set_prop_int(dev, "rxpingpong", rxpingpong); | |
43 | + dev->nd = nd; | |
44 | + qdev_prop_set_uint32(dev, "txpingpong", txpingpong); | |
45 | + qdev_prop_set_uint32(dev, "rxpingpong", rxpingpong); | |
46 | 46 | qdev_init(dev); |
47 | 47 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); |
48 | 48 | sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); | ... | ... |
hw/xilinx_ethlite.c
... | ... | @@ -53,8 +53,8 @@ struct xlx_ethlite |
53 | 53 | qemu_irq irq; |
54 | 54 | VLANClientState *vc; |
55 | 55 | |
56 | - unsigned int c_tx_pingpong; | |
57 | - unsigned int c_rx_pingpong; | |
56 | + uint32_t c_tx_pingpong; | |
57 | + uint32_t c_rx_pingpong; | |
58 | 58 | unsigned int txbuf; |
59 | 59 | unsigned int rxbuf; |
60 | 60 | |
... | ... | @@ -213,8 +213,6 @@ static void xilinx_ethlite_init(SysBusDevice *dev) |
213 | 213 | int regs; |
214 | 214 | |
215 | 215 | sysbus_init_irq(dev, &s->irq); |
216 | - s->c_tx_pingpong = qdev_get_prop_int(&dev->qdev, "txpingpong", 1); | |
217 | - s->c_rx_pingpong = qdev_get_prop_int(&dev->qdev, "rxpingpong", 1); | |
218 | 216 | s->rxbuf = 0; |
219 | 217 | |
220 | 218 | regs = cpu_register_io_memory(eth_read, eth_write, s); |
... | ... | @@ -225,10 +223,29 @@ static void xilinx_ethlite_init(SysBusDevice *dev) |
225 | 223 | eth_can_rx, eth_rx, NULL, eth_cleanup, s); |
226 | 224 | } |
227 | 225 | |
226 | +static SysBusDeviceInfo xilinx_ethlite_info = { | |
227 | + .init = xilinx_ethlite_init, | |
228 | + .qdev.name = "xilinx,ethlite", | |
229 | + .qdev.size = sizeof(struct xlx_ethlite), | |
230 | + .qdev.props = (Property[]) { | |
231 | + { | |
232 | + .name = "txpingpong", | |
233 | + .info = &qdev_prop_uint32, | |
234 | + .offset = offsetof(struct xlx_ethlite, c_tx_pingpong), | |
235 | + .defval = (uint32_t[]) { 1 }, | |
236 | + },{ | |
237 | + .name = "rxpingpong", | |
238 | + .info = &qdev_prop_uint32, | |
239 | + .offset = offsetof(struct xlx_ethlite, c_rx_pingpong), | |
240 | + .defval = (uint32_t[]) { 1 }, | |
241 | + }, | |
242 | + {/* end of list */} | |
243 | + } | |
244 | +}; | |
245 | + | |
228 | 246 | static void xilinx_ethlite_register(void) |
229 | 247 | { |
230 | - sysbus_register_dev("xilinx,ethlite", sizeof (struct xlx_ethlite), | |
231 | - xilinx_ethlite_init); | |
248 | + sysbus_register_withprop(&xilinx_ethlite_info); | |
232 | 249 | } |
233 | 250 | |
234 | 251 | device_init(xilinx_ethlite_register) | ... | ... |
hw/xilinx_intc.c
... | ... | @@ -150,7 +150,6 @@ static void xilinx_intc_init(SysBusDevice *dev) |
150 | 150 | struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev); |
151 | 151 | int pic_regs; |
152 | 152 | |
153 | - p->c_kind_of_intr = qdev_get_prop_int(&dev->qdev, "kind-of-intr", 0); | |
154 | 153 | qdev_init_gpio_in(&dev->qdev, irq_handler, 32); |
155 | 154 | sysbus_init_irq(dev, &p->parent_irq); |
156 | 155 | |
... | ... | @@ -158,10 +157,23 @@ static void xilinx_intc_init(SysBusDevice *dev) |
158 | 157 | sysbus_init_mmio(dev, R_MAX * 4, pic_regs); |
159 | 158 | } |
160 | 159 | |
160 | +static SysBusDeviceInfo xilinx_intc_info = { | |
161 | + .init = xilinx_intc_init, | |
162 | + .qdev.name = "xilinx,intc", | |
163 | + .qdev.size = sizeof(struct xlx_pic), | |
164 | + .qdev.props = (Property[]) { | |
165 | + { | |
166 | + .name = "kind-of-intr", | |
167 | + .info = &qdev_prop_uint32, | |
168 | + .offset = offsetof(struct xlx_pic, c_kind_of_intr), | |
169 | + }, | |
170 | + {/* end of list */} | |
171 | + } | |
172 | +}; | |
173 | + | |
161 | 174 | static void xilinx_intc_register(void) |
162 | 175 | { |
163 | - sysbus_register_dev("xilinx,intc", sizeof (struct xlx_pic), | |
164 | - xilinx_intc_init); | |
176 | + sysbus_register_withprop(&xilinx_intc_info); | |
165 | 177 | } |
166 | 178 | |
167 | 179 | device_init(xilinx_intc_register) | ... | ... |
hw/xilinx_timer.c
... | ... | @@ -61,7 +61,8 @@ struct timerblock |
61 | 61 | { |
62 | 62 | SysBusDevice busdev; |
63 | 63 | qemu_irq irq; |
64 | - unsigned int nr_timers; | |
64 | + uint32_t nr_timers; | |
65 | + uint32_t freq_hz; | |
65 | 66 | struct xlx_timer *timers; |
66 | 67 | }; |
67 | 68 | |
... | ... | @@ -192,14 +193,12 @@ static void xilinx_timer_init(SysBusDevice *dev) |
192 | 193 | { |
193 | 194 | struct timerblock *t = FROM_SYSBUS(typeof (*t), dev); |
194 | 195 | unsigned int i; |
195 | - int timer_regs, freq_hz; | |
196 | + int timer_regs; | |
196 | 197 | |
197 | 198 | /* All timers share a single irq line. */ |
198 | 199 | sysbus_init_irq(dev, &t->irq); |
199 | 200 | |
200 | 201 | /* Init all the ptimers. */ |
201 | - freq_hz = qdev_get_prop_int(&dev->qdev, "frequency", 2); | |
202 | - t->nr_timers = qdev_get_prop_int(&dev->qdev, "nr-timers", 2); | |
203 | 202 | t->timers = qemu_mallocz(sizeof t->timers[0] * t->nr_timers); |
204 | 203 | for (i = 0; i < t->nr_timers; i++) { |
205 | 204 | struct xlx_timer *xt = &t->timers[i]; |
... | ... | @@ -208,17 +207,36 @@ static void xilinx_timer_init(SysBusDevice *dev) |
208 | 207 | xt->nr = i; |
209 | 208 | xt->bh = qemu_bh_new(timer_hit, xt); |
210 | 209 | xt->ptimer = ptimer_init(xt->bh); |
211 | - ptimer_set_freq(xt->ptimer, freq_hz); | |
210 | + ptimer_set_freq(xt->ptimer, t->freq_hz); | |
212 | 211 | } |
213 | 212 | |
214 | 213 | timer_regs = cpu_register_io_memory(timer_read, timer_write, t); |
215 | 214 | sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs); |
216 | 215 | } |
217 | 216 | |
217 | +static SysBusDeviceInfo xilinx_timer_info = { | |
218 | + .init = xilinx_timer_init, | |
219 | + .qdev.name = "xilinx,timer", | |
220 | + .qdev.size = sizeof(struct timerblock), | |
221 | + .qdev.props = (Property[]) { | |
222 | + { | |
223 | + .name = "frequency", | |
224 | + .info = &qdev_prop_uint32, | |
225 | + .offset = offsetof(struct timerblock, freq_hz), | |
226 | + .defval = (uint32_t[]) { 2 }, | |
227 | + },{ | |
228 | + .name = "nr-timers", | |
229 | + .info = &qdev_prop_uint32, | |
230 | + .offset = offsetof(struct timerblock, nr_timers), | |
231 | + .defval = (uint32_t[]) { 2 }, | |
232 | + }, | |
233 | + {/* end of list */} | |
234 | + } | |
235 | +}; | |
236 | + | |
218 | 237 | static void xilinx_timer_register(void) |
219 | 238 | { |
220 | - sysbus_register_dev("xilinx,timer", sizeof (struct timerblock), | |
221 | - xilinx_timer_init); | |
239 | + sysbus_register_withprop(&xilinx_timer_info); | |
222 | 240 | } |
223 | 241 | |
224 | 242 | device_init(xilinx_timer_register) | ... | ... |