gwj / at91sam9263 · Commits

Signed-off-by: Filip Navara <filip.navara@gmail.com>

i) in function gen_bx_im, the last line (should be line 695 in your git HEAD) should be "tcg_gen_movi_i32..." instead of "tcg_gen_mov_i32". Otherwise BX/BLX immediate instructions will segfault QEMU.

ii) you have a resource leak in disas_vfp_insn; on line 3129 in your git HEAD, you have allocated a new temporary (addr) but if the if-expression on line 3129 is true, it will not be released - I fixed this by adding a "dead_tmp(addr);" line between lines 3141 and 3142 (i.e. the last line of the if-block).

iii) you have another resource issue in disas_thumb_insn; line 8306 should read "if (op != 0xf) dead_tmp(tmp);" instead of just plain "dead_tmp(tmp);" -- this is because in the above code the temporary variable tmp is not initialized if op==0xf and calling dead_tmp on it will cause problems.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

The old code resulted in wrong escape sequences:

#define CONFIG_QEMU_SHAREDIR "c:\Program Files\Qemu"

gcc warnings:

vl.c:5708:20: warning: unknown escape sequence '\P'
vl.c:5708:20: warning: unknown escape sequence '\Q'

Windows can handle slash (/) path separators,
and QEMU already adds directories using slash,
so there is no need to fight with the correct number
of backslashes.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>

- Change long/unsigned long to intptr_t/uintptr_t where needed
- Use PRIuPTR instead of %zu for printf
- Rework parsing of UUIDs
- Add support for Win64 ABI to TCG

Add support for constant propagation to TCG. This has to be paired with the liveness
analysis to remove the dead code. Not all possible operations are covered, but the
most common ones are. This improves the code generation for several ARM instructions,
like MVN (immediate), and it may help other targets as well.

v1 -> v2:
Added profiling code and hopefully fixed for 64-bit TCG targets.
v2 -> v3:
Another attempt at fixing the support for 64-bit TCG targets.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Since no target uses ICOUNT_TEMP anymore there's no reason to keep it.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

The goal is eventually to get rid of all cpu_T register usage and to use
just short-lived tmp/tmp2 registers. This patch converts all the places where
cpu_T was used in the Thumb code and replaces it with explicit TCG register
allocation.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Uninitialized register was used instead of proper TCG variable.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16
helpers used fixed registers to return values. This patch replaces that with
TCG code, so T0/T1 is no longer directly used by the helper functions.

Bugs in the gen_neon_unzip register load code were also fixed.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

The encoding of 'IA' and 'DB' conditions was swapped.
SRS instruction must store banked SPSR instead of CPSR at the specific address.
Missing 'return' statement at the end of RFE handling.
Fixed write-back code to reference correct registers.

From: Hyeonsung Jang <hsjang@ok-labs.com>
Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Signed-off-by: Filip Navara <filip.navara@gmail.com>

The temporary variable cache in no longer need since tcg_temp_free was introduced.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Currently each read/write of ARM register involves a LD/ST TCG operation. This
patch uses TCG memory-backed registers to represent the ARM register set. With
memory-backed registers the LD/ST operations are transparently generated by TCG
and host registers could be used to optimize the generated code.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Only very simple emulation of the LCD controller is included.

The controller features the standard HD44780 interface and supports character
output on four lines using a static 5x7 font and optional backlight controlled
by signal on a separate pin.

Capabilities such as custom characters, cursor and 5x10 fonts are not
implemented. Saving/loading of device state is not implemented either.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

The board scheme is available at
http://support.dce.felk.cvut.cz/e-kurzy/file.php/19/cviceni/Schema.pdf

Only the AT91SAM7X microcontroller, rotary encoder, matrix keyboard and
their connections are implemented.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

The Ethernet controller is implemented as a device on the system bus. It uses
DMA to read and write data from the main memory for packet queues.

Most of the controller features are implemented with the following exceptions:
- Statistics and related registers
- Support of VLAN tags
- Support for transmitting jumbo frames
- Recognizing of MAC addresses by a hash function

The emulation is based on the AT91SAM7X specification and also supports
registers present in the older AT91RM9200 controller - notably the TAR
register for sending a single frame by writing a physical memory
address into it.

EMAC also provides management interface for directly talking to the PHY chip.
The emulation of PHY chip is currently hard-coded in the EMAC emulation and
behaves as a DM9161 chip. Only few registers of the PHY chip are implemented.
Nevertheless it's enough to run the Atmel examples and even FreeRTOS demos.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

Only the timer part of the the Timer/Counter block is implemented since there
is no interface for connection of external clocks in QEMU, so there is nothing
to measure. The minimal implementation is done using host timers and an
internal counter.

This implementation is sufficient for running the Atmel examples,
but leaves a lot to be desired.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

The system controller in AT91 is composed of several devices and they are all
connected to single IRQ pin on the Advanced Interrupt Controller. This pseudo-
device allows multiplexing an IRQ pin by sending logic OR of all the inputs
to a single output pin.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

This patch introduces emulation of the AT91 reset controller. The behavior
and external interface to the reset controller is not emulated though and
only the features necessary to start the system are implemented.

Internal registers are maintained and partially emulated. The NRST status
bit is always asserted, even if a command to de-assert it is written
to the control register.

This emulation is sufficient to support running FreeRTOS and a sample code
from Atmel.

Signed-off-by: Filip Navara <filip.navara@gmail.com>

This patch implements the RTT used on AT91 microcontrollers. All documented features are implemented.

Signed-off-by: Filip Navara <filip.navara@gmail.com>