gwj / at91sam9263 · Commits

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3685 c046a42c-6fe2-441c-8c8c-71466251a162

Catch wrong/unknown NOR flash command sequences, by Thorsten Zitterell.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3684 c046a42c-6fe2-441c-8c8c-71466251a162

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3683 c046a42c-6fe2-441c-8c8c-71466251a162

Remove meaningless define from cpu.h
Misc cleanups.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162

ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.
Make those CPUs and PowerPC 440 available for user-mode emulation,
  thus providing a way of testing their implementation specific instructions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3681 c046a42c-6fe2-441c-8c8c-71466251a162

(but do not provide any actual implementation).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162

in order to implement Freescale cores.
Fix efsadd / efssub opcodes.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3679 c046a42c-6fe2-441c-8c8c-71466251a162

Remove TARGET_PPC64 dependency and add code provision to be able
  to define a fake 32 bits CPU with hypervisor feature support.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3678 c046a42c-6fe2-441c-8c8c-71466251a162

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3677 c046a42c-6fe2-441c-8c8c-71466251a162

Don't error out on reading GPCR register, just warn (Thorsten Zitterell).
Don't zero a memory that's already zeroed.


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…ax7310 and s3c gpios).
Convert spitz and gumstix boards to use new api.
Remove now obsolete gpio_handler_t definition.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3670 c046a42c-6fe2-441c-8c8c-71466251a162

Add a note from Fabrice in slow_st template.


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typedefed enums.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3660 c046a42c-6fe2-441c-8c8c-71466251a162

Use proper INPUT_NB definitions to allocate PowerPC input pins structure,
  fixing a buffer overflow in the 6xx bus case.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3659 c046a42c-6fe2-441c-8c8c-71466251a162

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3658 c046a42c-6fe2-441c-8c8c-71466251a162

add CPU selection feature, choose the correct default CPU and set
the 32/64 bits computation mode properly.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3657 c046a42c-6fe2-441c-8c8c-71466251a162

Always make the hypervisor timers available.
Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases
that cannot be properly handled with the current PowerPC CPU definition.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3655 c046a42c-6fe2-441c-8c8c-71466251a162

available for full system emulation, then removing all #if TARGET_PPC64H
  from micro-ops and code translator.
Add new macros to dramatically simplify memory access tables definitions
  in target-ppc/translate.c.


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r172: Enable boot mode in the exception handler for both SuperSparc and TurboSparc
r173: More CPU definitions
r174: Add Sparc64 CPU identification
r175: Add SPARCserver 600MP emulation
r176: Update OHW interface to version 3.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3649 c046a42c-6fe2-441c-8c8c-71466251a162

Use common ABI description file with OpenBIOS.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3648 c046a42c-6fe2-441c-8c8c-71466251a162

now that the SPE extension is available for all targets,
 we always need to have some 64 bits temporary registers.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3647 c046a42c-6fe2-441c-8c8c-71466251a162

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