gwj / at91sam9263 · Commits

Commit 05332d70fd7488459e4b80c73ff7547b3a1a7ce6

Authored by j_mayer
1 parent a4f30719

A little more granularity in PowerPC instructions definition is needed 

in order to implement Freescale cores.
Fix efsadd / efssub opcodes.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3679 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 84 additions and 66 deletions
target-ppc/translate.c
  View file @05332d7
... ... @@ -462,8 +462,12 @@ enum {
462 462 /* Fixed-point unit extensions */
463 463 /* PowerPC 602 specific */
464 464 PPC_602_SPEC = 0x0000000000000400ULL,
465   - /* PowerPC 2.03 specification extensions */
466   - PPC_203 = 0x0000000000000800ULL,
  465 + /* isel instruction */
  466 + PPC_ISEL = 0x0000000000000800ULL,
  467 + /* popcntb instruction */
  468 + PPC_POPCNTB = 0x0000000000001000ULL,
  469 + /* string load / store */
  470 + PPC_STRING = 0x0000000000002000ULL,
467 471  
468 472 /* Floating-point unit extensions */
469 473 /* Optional floating point instructions */
... ... @@ -480,12 +484,10 @@ enum {
480 484 /* Vector/SIMD extensions */
481 485 /* Altivec support */
482 486 PPC_ALTIVEC = 0x0000000001000000ULL,
483   - /* e500 vector instructions */
484   - PPC_E500_VECTOR = 0x0000000002000000ULL,
485 487 /* PowerPC 2.03 SPE extension */
486   - PPC_SPE = 0x0000000004000000ULL,
  488 + PPC_SPE = 0x0000000002000000ULL,
487 489 /* PowerPC 2.03 SPE floating-point extension */
488   - PPC_SPEFPU = 0x0000000008000000ULL,
  490 + PPC_SPEFPU = 0x0000000004000000ULL,
489 491  
490 492 /* Optional memory control instructions */
491 493 PPC_MEM_TLBIA = 0x0000000010000000ULL,
... ... @@ -497,52 +499,64 @@ enum {
497 499 PPC_MEM_EIEIO = 0x0000000100000000ULL,
498 500  
499 501 /* Cache control instructions */
500   - PPC_CACHE = 0x0000001000000000ULL,
  502 + PPC_CACHE = 0x00000002000000000ULL,
501 503 /* icbi instruction */
502   - PPC_CACHE_ICBI = 0x0000002000000000ULL,
  504 + PPC_CACHE_ICBI = 0x0000000400000000ULL,
503 505 /* dcbz instruction with fixed cache line size */
504   - PPC_CACHE_DCBZ = 0x0000004000000000ULL,
  506 + PPC_CACHE_DCBZ = 0x0000000800000000ULL,
505 507 /* dcbz instruction with tunable cache line size */
506   - PPC_CACHE_DCBZT = 0x0000008000000000ULL,
  508 + PPC_CACHE_DCBZT = 0x0000001000000000ULL,
507 509 /* dcba instruction */
508   - PPC_CACHE_DCBA = 0x0000010000000000ULL,
  510 + PPC_CACHE_DCBA = 0x0000002000000000ULL,
  511 + /* Freescale cache locking instructions */
  512 + PPC_CACHE_LOCK = 0x0000004000000000ULL,
509 513  
510 514 /* MMU related extensions */
511 515 /* external control instructions */
512   - PPC_EXTERN = 0x0000100000000000ULL,
  516 + PPC_EXTERN = 0x0000010000000000ULL,
513 517 /* segment register access instructions */
514   - PPC_SEGMENT = 0x0000200000000000ULL,
  518 + PPC_SEGMENT = 0x0000020000000000ULL,
515 519 /* PowerPC 6xx TLB management instructions */
516   - PPC_6xx_TLB = 0x0000400000000000ULL,
  520 + PPC_6xx_TLB = 0x0000040000000000ULL,
517 521 /* PowerPC 74xx TLB management instructions */
518   - PPC_74xx_TLB = 0x0000800000000000ULL,
  522 + PPC_74xx_TLB = 0x0000080000000000ULL,
519 523 /* PowerPC 40x TLB management instructions */
520   - PPC_40x_TLB = 0x0001000000000000ULL,
  524 + PPC_40x_TLB = 0x0000100000000000ULL,
521 525 /* segment register access instructions for PowerPC 64 "bridge" */
522   - PPC_SEGMENT_64B = 0x0002000000000000ULL,
  526 + PPC_SEGMENT_64B = 0x0000200000000000ULL,
523 527 /* SLB management */
524   - PPC_SLBI = 0x0004000000000000ULL,
  528 + PPC_SLBI = 0x0000400000000000ULL,
525 529  
526 530 /* Embedded PowerPC dedicated instructions */
527   - PPC_EMB_COMMON = 0x0010000000000000ULL,
  531 + PPC_WRTEE = 0x0001000000000000ULL,
528 532 /* PowerPC 40x exception model */
529   - PPC_40x_EXCP = 0x0020000000000000ULL,
  533 + PPC_40x_EXCP = 0x0002000000000000ULL,
530 534 /* PowerPC 405 Mac instructions */
531   - PPC_405_MAC = 0x0040000000000000ULL,
  535 + PPC_405_MAC = 0x0004000000000000ULL,
532 536 /* PowerPC 440 specific instructions */
533   - PPC_440_SPEC = 0x0080000000000000ULL,
  537 + PPC_440_SPEC = 0x0008000000000000ULL,
534 538 /* BookE (embedded) PowerPC specification */
535   - PPC_BOOKE = 0x0100000000000000ULL,
536   - /* More BookE (embedded) instructions... */
537   - PPC_BOOKE_EXT = 0x0200000000000000ULL,
  539 + PPC_BOOKE = 0x0010000000000000ULL,
  540 + /* mfapidi instruction */
  541 + PPC_MFAPIDI = 0x0020000000000000ULL,
  542 + /* tlbiva instruction */
  543 + PPC_TLBIVA = 0x0040000000000000ULL,
  544 + /* tlbivax instruction */
  545 + PPC_TLBIVAX = 0x0080000000000000ULL,
538 546 /* PowerPC 4xx dedicated instructions */
539   - PPC_4xx_COMMON = 0x0400000000000000ULL,
  547 + PPC_4xx_COMMON = 0x0100000000000000ULL,
540 548 /* PowerPC 40x ibct instructions */
541   - PPC_40x_ICBT = 0x0800000000000000ULL,
  549 + PPC_40x_ICBT = 0x0200000000000000ULL,
542 550 /* rfmci is not implemented in all BookE PowerPC */
543   - PPC_RFMCI = 0x1000000000000000ULL,
  551 + PPC_RFMCI = 0x0400000000000000ULL,
  552 + /* rfdi instruction */
  553 + PPC_RFDI = 0x0800000000000000ULL,
  554 + /* DCR accesses */
  555 + PPC_DCR = 0x1000000000000000ULL,
  556 + /* DCR extended accesse */
  557 + PPC_DCRX = 0x2000000000000000ULL,
544 558 /* user-mode DCR access, implemented in PowerPC 460 */
545   - PPC_DCRUX = 0x2000000000000000ULL,
  559 + PPC_DCRUX = 0x4000000000000000ULL,
546 560 };
547 561  
548 562 /*****************************************************************************/
... ... @@ -1119,7 +1133,7 @@ GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1119 1133 }
1120 1134  
1121 1135 /* isel (PowerPC 2.03 specification) */
1122   -GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
  1136 +GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_ISEL)
1123 1137 {
1124 1138 uint32_t bi = rC(ctx->opcode);
1125 1139 uint32_t mask;
... ... @@ -1342,7 +1356,7 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1342 1356 }
1343 1357  
1344 1358 /* popcntb : PowerPC 2.03 specification */
1345   -GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
  1359 +GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1346 1360 {
1347 1361 gen_op_load_gpr_T0(rS(ctx->opcode));
1348 1362 #if defined(TARGET_PPC64)
... ... @@ -2457,7 +2471,7 @@ static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2457 2471 * In an other hand, IBM says this is valid, but rA won't be loaded.
2458 2472 * For now, I'll follow the spec...
2459 2473 */
2460   -GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
  2474 +GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
2461 2475 {
2462 2476 int nb = NB(ctx->opcode);
2463 2477 int start = rD(ctx->opcode);
... ... @@ -2482,7 +2496,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2482 2496 }
2483 2497  
2484 2498 /* lswx */
2485   -GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
  2499 +GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
2486 2500 {
2487 2501 int ra = rA(ctx->opcode);
2488 2502 int rb = rB(ctx->opcode);
... ... @@ -2498,7 +2512,7 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2498 2512 }
2499 2513  
2500 2514 /* stswi */
2501   -GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
  2515 +GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
2502 2516 {
2503 2517 int nb = NB(ctx->opcode);
2504 2518  
... ... @@ -2512,7 +2526,7 @@ GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2512 2526 }
2513 2527  
2514 2528 /* stswx */
2515   -GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
  2529 +GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
2516 2530 {
2517 2531 /* NIP cannot be restored if the memory exception comes from an helper */
2518 2532 gen_update_nip(ctx, ctx->nip - 4);
... ... @@ -4520,14 +4534,14 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4520 4534  
4521 4535 /* BookE specific instructions */
4522 4536 /* XXX: not implemented on 440 ? */
4523   -GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
  4537 +GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
4524 4538 {
4525 4539 /* XXX: TODO */
4526 4540 GEN_EXCP_INVAL(ctx);
4527 4541 }
4528 4542  
4529 4543 /* XXX: not implemented on 440 ? */
4530   -GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
  4544 +GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
4531 4545 {
4532 4546 #if defined(CONFIG_USER_ONLY)
4533 4547 GEN_EXCP_PRIVOPC(ctx);
... ... @@ -4723,7 +4737,7 @@ GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
4723 4737 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
4724 4738  
4725 4739 /* mfdcr */
4726   -GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
  4740 +GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
4727 4741 {
4728 4742 #if defined(CONFIG_USER_ONLY)
4729 4743 GEN_EXCP_PRIVREG(ctx);
... ... @@ -4741,7 +4755,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
4741 4755 }
4742 4756  
4743 4757 /* mtdcr */
4744   -GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
  4758 +GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
4745 4759 {
4746 4760 #if defined(CONFIG_USER_ONLY)
4747 4761 GEN_EXCP_PRIVREG(ctx);
... ... @@ -4760,7 +4774,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
4760 4774  
4761 4775 /* mfdcrx */
4762 4776 /* XXX: not implemented on 440 ? */
4763   -GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
  4777 +GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
4764 4778 {
4765 4779 #if defined(CONFIG_USER_ONLY)
4766 4780 GEN_EXCP_PRIVREG(ctx);
... ... @@ -4778,7 +4792,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
4778 4792  
4779 4793 /* mtdcrx */
4780 4794 /* XXX: not implemented on 440 ? */
4781   -GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
  4795 +GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
4782 4796 {
4783 4797 #if defined(CONFIG_USER_ONLY)
4784 4798 GEN_EXCP_PRIVREG(ctx);
... ... @@ -4912,7 +4926,7 @@ GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4912 4926  
4913 4927 /* BookE specific */
4914 4928 /* XXX: not implemented on 440 ? */
4915   -GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
  4929 +GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
4916 4930 {
4917 4931 #if defined(CONFIG_USER_ONLY)
4918 4932 GEN_EXCP_PRIVOPC(ctx);
... ... @@ -5088,7 +5102,7 @@ GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5088 5102 }
5089 5103  
5090 5104 /* wrtee */
5091   -GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
  5105 +GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
5092 5106 {
5093 5107 #if defined(CONFIG_USER_ONLY)
5094 5108 GEN_EXCP_PRIVOPC(ctx);
... ... @@ -5107,7 +5121,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
5107 5121 }
5108 5122  
5109 5123 /* wrteei */
5110   -GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
  5124 +GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
5111 5125 {
5112 5126 #if defined(CONFIG_USER_ONLY)
5113 5127 GEN_EXCP_PRIVOPC(ctx);
... ... @@ -5943,7 +5957,7 @@ GEN_SPEOP_COMP(efststlt);
5943 5957 GEN_SPEOP_COMP(efststeq);
5944 5958  
5945 5959 /* Opcodes definitions */
5946   -GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
  5960 +GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
5947 5961 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
5948 5962 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
5949 5963 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
... ...
target-ppc/translate_init.c
  View file @05332d7
... ... @@ -2648,11 +2648,11 @@ static int check_pow_hid0 (CPUPPCState *env)
2648 2648 /* PowerPC implementations definitions */
2649 2649  
2650 2650 /* PowerPC 40x instruction set */
2651   -#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON | \
  2651 +#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_WRTEE | \
2652 2652 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)
2653 2653  
2654 2654 /* PowerPC 401 */
2655   -#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
  2655 +#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2656 2656 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2657 2657 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2658 2658 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
... ... @@ -2676,7 +2676,7 @@ static void init_proc_401 (CPUPPCState *env)
2676 2676 }
2677 2677  
2678 2678 /* PowerPC 401x2 */
2679   -#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
  2679 +#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2680 2680 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2681 2681 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2682 2682 PPC_CACHE_DCBA | PPC_MFTB | \
... ... @@ -2709,7 +2709,7 @@ static void init_proc_401x2 (CPUPPCState *env)
2709 2709 }
2710 2710  
2711 2711 /* PowerPC 401x3 */
2712   -#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
  2712 +#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2713 2713 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2714 2714 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2715 2715 PPC_CACHE_DCBA | PPC_MFTB | \
... ... @@ -2738,7 +2738,7 @@ static void init_proc_401x3 (CPUPPCState *env)
2738 2738 }
2739 2739  
2740 2740 /* IOP480 */
2741   -#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
  2741 +#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2742 2742 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2743 2743 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2744 2744 PPC_CACHE_DCBA | \
... ... @@ -2771,7 +2771,7 @@ static void init_proc_IOP480 (CPUPPCState *env)
2771 2771 }
2772 2772  
2773 2773 /* PowerPC 403 */
2774   -#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
  2774 +#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2775 2775 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2776 2776 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2777 2777 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
... ... @@ -2800,7 +2800,7 @@ static void init_proc_403 (CPUPPCState *env)
2800 2800 }
2801 2801  
2802 2802 /* PowerPC 403 GCX */
2803   -#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
  2803 +#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2804 2804 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2805 2805 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2806 2806 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
... ... @@ -2844,7 +2844,8 @@ static void init_proc_403GCX (CPUPPCState *env)
2844 2844 }
2845 2845  
2846 2846 /* PowerPC 405 */
2847   -#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
  2847 +#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  2848 + PPC_MFTB | \
2848 2849 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2849 2850 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2850 2851 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
... ... @@ -2889,7 +2890,7 @@ static void init_proc_405 (CPUPPCState *env)
2889 2890 }
2890 2891  
2891 2892 /* PowerPC 440 EP */
2892   -#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
  2893 +#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2893 2894 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2894 2895 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2895 2896 PPC_440_SPEC | PPC_RFMCI)
... ... @@ -2939,10 +2940,11 @@ static void init_proc_440EP (CPUPPCState *env)
2939 2940 }
2940 2941  
2941 2942 /* PowerPC 440 GP */
2942   -#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
  2943 +#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | PPC_STRING | \
  2944 + PPC_DCR | PPC_DCRX | \
2943 2945 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2944   - PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2945   - PPC_405_MAC | PPC_440_SPEC)
  2946 + PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
  2947 + PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
2946 2948 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2947 2949 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2948 2950 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
... ... @@ -2971,7 +2973,7 @@ static void init_proc_440GP (CPUPPCState *env)
2971 2973 }
2972 2974  
2973 2975 /* PowerPC 440x4 */
2974   -#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
  2976 +#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2975 2977 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2976 2978 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2977 2979 PPC_440_SPEC)
... ... @@ -3004,7 +3006,7 @@ static void init_proc_440x4 (CPUPPCState *env)
3004 3006 }
3005 3007  
3006 3008 /* PowerPC 440x5 */
3007   -#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
  3009 +#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3008 3010 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3009 3011 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3010 3012 PPC_440_SPEC | PPC_RFMCI)
... ... @@ -3054,10 +3056,11 @@ static void init_proc_440x5 (CPUPPCState *env)
3054 3056 }
3055 3057  
3056 3058 /* PowerPC 460 (guessed) */
3057   -#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
  3059 +#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | PPC_STRING | \
  3060 + PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3058 3061 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3059   - PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3060   - PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
  3062 + PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
  3063 + PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
3061 3064 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3062 3065 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3063 3066 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
... ... @@ -3110,13 +3113,14 @@ static void init_proc_460 (CPUPPCState *env)
3110 3113 }
3111 3114  
3112 3115 /* PowerPC 460F (guessed) */
3113   -#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
  3116 +#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | PPC_STRING | \
  3117 + PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3114 3118 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3115 3119 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3116 3120 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3117 3121 PPC_FLOAT_STFIWX | \
3118   - PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3119   - PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
  3122 + PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
  3123 + PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
3120 3124 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3121 3125 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3122 3126 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
... ... @@ -3231,7 +3235,7 @@ static void init_proc_e500 (CPUPPCState *env)
3231 3235  
3232 3236 /* Non-embedded PowerPC */
3233 3237 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3234   -#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | \
  3238 +#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | \
3235 3239 PPC_CACHE | PPC_CACHE_ICBI | \
3236 3240 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3237 3241 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
... ...