Commit 4c1b1bfe30dab7bc08e3ff8f179f8e11be9d7f04

Authored by j_mayer
1 parent 80d11f44

Improve PowerPC instructions set dump.

Remove meaningless define from cpu.h
Misc cleanups.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc/cpu.h
... ... @@ -434,7 +434,6 @@ union ppc_tlb_t {
434 434 #if defined(PPC_EMULATE_32BITS_HYPV)
435 435 #define MSR_HVB (1ULL << MSR_THV)
436 436 #define msr_hv msr_thv
437   -#define
438 437 #else
439 438 #define MSR_HVB (0ULL)
440 439 #define msr_hv (0)
... ...
target-ppc/translate_init.c
... ... @@ -45,7 +45,7 @@ struct ppc_def_t {
45 45 uint32_t flags;
46 46 int bfd_mach;
47 47 void (*init_proc)(CPUPPCState *env);
48   - int (*check_pow)(CPUPPCState *env);
  48 + int (*check_pow)(CPUPPCState *env);
49 49 };
50 50  
51 51 /* For user-mode emulation, we don't emulate any IRQ controller */
... ... @@ -3837,7 +3837,6 @@ static void init_proc_G2LE (CPUPPCState *env)
3837 3837 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE)
3838 3838 #define check_pow_e200 check_pow_hid0
3839 3839  
3840   -
3841 3840 __attribute__ (( unused ))
3842 3841 static void init_proc_e200 (CPUPPCState *env)
3843 3842 {
... ... @@ -8007,6 +8006,10 @@ static int register_direct_insn (opc_handler_t **ppc_opcodes,
8007 8006 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8008 8007 printf("*** ERROR: opcode %02x already assigned in main "
8009 8008 "opcode table\n", idx);
  8009 +#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
  8010 + printf(" Registered handler '%s' - new handler '%s'\n",
  8011 + ppc_opcodes[idx]->oname, handler->oname);
  8012 +#endif
8010 8013 return -1;
8011 8014 }
8012 8015  
... ... @@ -8027,6 +8030,10 @@ static int register_ind_in_table (opc_handler_t **table,
8027 8030 if (!is_indirect_opcode(table[idx1])) {
8028 8031 printf("*** ERROR: idx %02x already assigned to a direct "
8029 8032 "opcode\n", idx1);
  8033 +#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
  8034 + printf(" Registered handler '%s' - new handler '%s'\n",
  8035 + ind_table(table[idx1])[idx2]->oname, handler->oname);
  8036 +#endif
8030 8037 return -1;
8031 8038 }
8032 8039 }
... ... @@ -8034,6 +8041,10 @@ static int register_ind_in_table (opc_handler_t **table,
8034 8041 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8035 8042 printf("*** ERROR: opcode %02x already assigned in "
8036 8043 "opcode table %02x\n", idx2, idx1);
  8044 +#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
  8045 + printf(" Registered handler '%s' - new handler '%s'\n",
  8046 + ind_table(table[idx1])[idx2]->oname, handler->oname);
  8047 +#endif
8037 8048 return -1;
8038 8049 }
8039 8050  
... ... @@ -8156,6 +8167,7 @@ static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
8156 8167 static void dump_ppc_insns (CPUPPCState *env)
8157 8168 {
8158 8169 opc_handler_t **table, *handler;
  8170 + const unsigned char *p, *q;
8159 8171 uint8_t opc1, opc2, opc3;
8160 8172  
8161 8173 printf("Instructions set:\n");
... ... @@ -8176,9 +8188,35 @@ static void dump_ppc_insns (CPUPPCState *env)
8176 8188 for (opc3 = 0; opc3 < 0x20; opc3++) {
8177 8189 handler = table[opc3];
8178 8190 if (handler->handler != &gen_invalid) {
8179   - printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
8180   - opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
8181   - handler->oname);
  8191 + /* Special hack to properly dump SPE insns */
  8192 + p = strchr(handler->oname, '_');
  8193 + if (p == NULL) {
  8194 + printf("INSN: %02x %02x %02x (%02d %04d) : "
  8195 + "%s\n",
  8196 + opc1, opc2, opc3, opc1,
  8197 + (opc3 << 5) | opc2,
  8198 + handler->oname);
  8199 + } else {
  8200 + q = "speundef";
  8201 + if ((p - handler->oname) != strlen(q) ||
  8202 + memcmp(handler->oname, q, strlen(q)) != 0) {
  8203 + /* First instruction */
  8204 + printf("INSN: %02x %02x %02x (%02d %04d) : "
  8205 + "%.*s\n",
  8206 + opc1, opc2 << 1, opc3, opc1,
  8207 + (opc3 << 6) | (opc2 << 1),
  8208 + (int)(p - handler->oname),
  8209 + handler->oname);
  8210 + }
  8211 + if (strcmp(p + 1, q) != 0) {
  8212 + /* Second instruction */
  8213 + printf("INSN: %02x %02x %02x (%02d %04d) : "
  8214 + "%s\n",
  8215 + opc1, (opc2 << 1) | 1, opc3, opc1,
  8216 + (opc3 << 6) | (opc2 << 1) | 1,
  8217 + p + 1);
  8218 + }
  8219 + }
8182 8220 }
8183 8221 }
8184 8222 } else {
... ... @@ -8393,7 +8431,7 @@ static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
8393 8431 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
8394 8432 /* We check '>=' instead of '>' because the PPC_defs table
8395 8433 * is ordered by increasing revision.
8396   - * Then, we will match the higher revision compatible
  8434 + * Then, we will match the higher revision compatible
8397 8435 * with the requested PVR
8398 8436 */
8399 8437 if (match >= best_match) {
... ...