gwj / at91sam9263 · Commits

Commit 80d11f4467c49c593c9356b97de6c0b4e12d73c1

Authored by j_mayer
1 parent b4095fed

Add definitions for Freescale PowerPC implementations, 

ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.
Make those CPUs and PowerPC 440 available for user-mode emulation,
  thus providing a way of testing their implementation specific instructions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3681 c046a42c-6fe2-441c-8c8c-71466251a162
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target-ppc/cpu.h
  View file @80d11f4
... ... @@ -822,394 +822,447 @@ static inline int cpu_mmu_index (CPUState *env)
822 822 #define xer_bc env->xer[0]
823 823  
824 824 /* SPR definitions */
825   -#define SPR_MQ (0x000)
826   -#define SPR_XER (0x001)
827   -#define SPR_601_VRTCU (0x004)
828   -#define SPR_601_VRTCL (0x005)
829   -#define SPR_601_UDECR (0x006)
830   -#define SPR_LR (0x008)
831   -#define SPR_CTR (0x009)
832   -#define SPR_DSISR (0x012)
833   -#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
834   -#define SPR_601_RTCU (0x014)
835   -#define SPR_601_RTCL (0x015)
836   -#define SPR_DECR (0x016)
837   -#define SPR_SDR1 (0x019)
838   -#define SPR_SRR0 (0x01A)
839   -#define SPR_SRR1 (0x01B)
840   -#define SPR_AMR (0x01D)
841   -#define SPR_BOOKE_PID (0x030)
842   -#define SPR_BOOKE_DECAR (0x036)
843   -#define SPR_BOOKE_CSRR0 (0x03A)
844   -#define SPR_BOOKE_CSRR1 (0x03B)
845   -#define SPR_BOOKE_DEAR (0x03D)
846   -#define SPR_BOOKE_ESR (0x03E)
847   -#define SPR_BOOKE_IVPR (0x03F)
848   -#define SPR_8xx_EIE (0x050)
849   -#define SPR_8xx_EID (0x051)
850   -#define SPR_8xx_NRE (0x052)
851   -#define SPR_CTRL (0x088)
852   -#define SPR_58x_CMPA (0x090)
853   -#define SPR_58x_CMPB (0x091)
854   -#define SPR_58x_CMPC (0x092)
855   -#define SPR_58x_CMPD (0x093)
856   -#define SPR_58x_ICR (0x094)
857   -#define SPR_58x_DER (0x094)
858   -#define SPR_58x_COUNTA (0x096)
859   -#define SPR_58x_COUNTB (0x097)
860   -#define SPR_UCTRL (0x098)
861   -#define SPR_58x_CMPE (0x098)
862   -#define SPR_58x_CMPF (0x099)
863   -#define SPR_58x_CMPG (0x09A)
864   -#define SPR_58x_CMPH (0x09B)
865   -#define SPR_58x_LCTRL1 (0x09C)
866   -#define SPR_58x_LCTRL2 (0x09D)
867   -#define SPR_58x_ICTRL (0x09E)
868   -#define SPR_58x_BAR (0x09F)
869   -#define SPR_VRSAVE (0x100)
870   -#define SPR_USPRG0 (0x100)
871   -#define SPR_USPRG1 (0x101)
872   -#define SPR_USPRG2 (0x102)
873   -#define SPR_USPRG3 (0x103)
874   -#define SPR_USPRG4 (0x104)
875   -#define SPR_USPRG5 (0x105)
876   -#define SPR_USPRG6 (0x106)
877   -#define SPR_USPRG7 (0x107)
878   -#define SPR_VTBL (0x10C)
879   -#define SPR_VTBU (0x10D)
880   -#define SPR_SPRG0 (0x110)
881   -#define SPR_SPRG1 (0x111)
882   -#define SPR_SPRG2 (0x112)
883   -#define SPR_SPRG3 (0x113)
884   -#define SPR_SPRG4 (0x114)
885   -#define SPR_SCOMC (0x114)
886   -#define SPR_SPRG5 (0x115)
887   -#define SPR_SCOMD (0x115)
888   -#define SPR_SPRG6 (0x116)
889   -#define SPR_SPRG7 (0x117)
890   -#define SPR_ASR (0x118)
891   -#define SPR_EAR (0x11A)
892   -#define SPR_TBL (0x11C)
893   -#define SPR_TBU (0x11D)
894   -#define SPR_TBU40 (0x11E)
895   -#define SPR_SVR (0x11E)
896   -#define SPR_BOOKE_PIR (0x11E)
897   -#define SPR_PVR (0x11F)
898   -#define SPR_HSPRG0 (0x130)
899   -#define SPR_BOOKE_DBSR (0x130)
900   -#define SPR_HSPRG1 (0x131)
901   -#define SPR_HDSISR (0x132)
902   -#define SPR_HDAR (0x133)
903   -#define SPR_BOOKE_DBCR0 (0x134)
904   -#define SPR_IBCR (0x135)
905   -#define SPR_PURR (0x135)
906   -#define SPR_BOOKE_DBCR1 (0x135)
907   -#define SPR_DBCR (0x136)
908   -#define SPR_HDEC (0x136)
909   -#define SPR_BOOKE_DBCR2 (0x136)
910   -#define SPR_HIOR (0x137)
911   -#define SPR_MBAR (0x137)
912   -#define SPR_RMOR (0x138)
913   -#define SPR_BOOKE_IAC1 (0x138)
914   -#define SPR_HRMOR (0x139)
915   -#define SPR_BOOKE_IAC2 (0x139)
916   -#define SPR_HSRR0 (0x13A)
917   -#define SPR_BOOKE_IAC3 (0x13A)
918   -#define SPR_HSRR1 (0x13B)
919   -#define SPR_BOOKE_IAC4 (0x13B)
920   -#define SPR_LPCR (0x13C)
921   -#define SPR_BOOKE_DAC1 (0x13C)
922   -#define SPR_LPIDR (0x13D)
923   -#define SPR_DABR2 (0x13D)
924   -#define SPR_BOOKE_DAC2 (0x13D)
925   -#define SPR_BOOKE_DVC1 (0x13E)
926   -#define SPR_BOOKE_DVC2 (0x13F)
927   -#define SPR_BOOKE_TSR (0x150)
928   -#define SPR_BOOKE_TCR (0x154)
929   -#define SPR_BOOKE_IVOR0 (0x190)
930   -#define SPR_BOOKE_IVOR1 (0x191)
931   -#define SPR_BOOKE_IVOR2 (0x192)
932   -#define SPR_BOOKE_IVOR3 (0x193)
933   -#define SPR_BOOKE_IVOR4 (0x194)
934   -#define SPR_BOOKE_IVOR5 (0x195)
935   -#define SPR_BOOKE_IVOR6 (0x196)
936   -#define SPR_BOOKE_IVOR7 (0x197)
937   -#define SPR_BOOKE_IVOR8 (0x198)
938   -#define SPR_BOOKE_IVOR9 (0x199)
939   -#define SPR_BOOKE_IVOR10 (0x19A)
940   -#define SPR_BOOKE_IVOR11 (0x19B)
941   -#define SPR_BOOKE_IVOR12 (0x19C)
942   -#define SPR_BOOKE_IVOR13 (0x19D)
943   -#define SPR_BOOKE_IVOR14 (0x19E)
944   -#define SPR_BOOKE_IVOR15 (0x19F)
945   -#define SPR_BOOKE_SPEFSCR (0x200)
946   -#define SPR_E500_BBEAR (0x201)
947   -#define SPR_E500_BBTAR (0x202)
948   -#define SPR_ATBL (0x20E)
949   -#define SPR_ATBU (0x20F)
950   -#define SPR_IBAT0U (0x210)
951   -#define SPR_BOOKE_IVOR32 (0x210)
952   -#define SPR_IBAT0L (0x211)
953   -#define SPR_BOOKE_IVOR33 (0x211)
954   -#define SPR_IBAT1U (0x212)
955   -#define SPR_BOOKE_IVOR34 (0x212)
956   -#define SPR_IBAT1L (0x213)
957   -#define SPR_BOOKE_IVOR35 (0x213)
958   -#define SPR_IBAT2U (0x214)
959   -#define SPR_BOOKE_IVOR36 (0x214)
960   -#define SPR_IBAT2L (0x215)
961   -#define SPR_E500_L1CFG0 (0x215)
962   -#define SPR_BOOKE_IVOR37 (0x215)
963   -#define SPR_IBAT3U (0x216)
964   -#define SPR_E500_L1CFG1 (0x216)
965   -#define SPR_IBAT3L (0x217)
966   -#define SPR_DBAT0U (0x218)
967   -#define SPR_DBAT0L (0x219)
968   -#define SPR_DBAT1U (0x21A)
969   -#define SPR_DBAT1L (0x21B)
970   -#define SPR_DBAT2U (0x21C)
971   -#define SPR_DBAT2L (0x21D)
972   -#define SPR_DBAT3U (0x21E)
973   -#define SPR_DBAT3L (0x21F)
974   -#define SPR_IBAT4U (0x230)
975   -#define SPR_IBAT4L (0x231)
976   -#define SPR_IBAT5U (0x232)
977   -#define SPR_IBAT5L (0x233)
978   -#define SPR_IBAT6U (0x234)
979   -#define SPR_IBAT6L (0x235)
980   -#define SPR_IBAT7U (0x236)
981   -#define SPR_IBAT7L (0x237)
982   -#define SPR_DBAT4U (0x238)
983   -#define SPR_DBAT4L (0x239)
984   -#define SPR_DBAT5U (0x23A)
985   -#define SPR_BOOKE_MCSRR0 (0x23A)
986   -#define SPR_DBAT5L (0x23B)
987   -#define SPR_BOOKE_MCSRR1 (0x23B)
988   -#define SPR_DBAT6U (0x23C)
989   -#define SPR_BOOKE_MCSR (0x23C)
990   -#define SPR_DBAT6L (0x23D)
991   -#define SPR_E500_MCAR (0x23D)
992   -#define SPR_DBAT7U (0x23E)
993   -#define SPR_BOOKE_DSRR0 (0x23E)
994   -#define SPR_DBAT7L (0x23F)
995   -#define SPR_BOOKE_DSRR1 (0x23F)
996   -#define SPR_BOOKE_SPRG8 (0x25C)
997   -#define SPR_BOOKE_SPRG9 (0x25D)
998   -#define SPR_BOOKE_MAS0 (0x270)
999   -#define SPR_BOOKE_MAS1 (0x271)
1000   -#define SPR_BOOKE_MAS2 (0x272)
1001   -#define SPR_BOOKE_MAS3 (0x273)
1002   -#define SPR_BOOKE_MAS4 (0x274)
1003   -#define SPR_BOOKE_MAS6 (0x276)
1004   -#define SPR_BOOKE_PID1 (0x279)
1005   -#define SPR_BOOKE_PID2 (0x27A)
1006   -#define SPR_BOOKE_TLB0CFG (0x2B0)
1007   -#define SPR_BOOKE_TLB1CFG (0x2B1)
1008   -#define SPR_BOOKE_TLB2CFG (0x2B2)
1009   -#define SPR_BOOKE_TLB3CFG (0x2B3)
1010   -#define SPR_BOOKE_EPR (0x2BE)
1011   -#define SPR_PERF0 (0x300)
1012   -#define SPR_PERF1 (0x301)
1013   -#define SPR_PERF2 (0x302)
1014   -#define SPR_PERF3 (0x303)
1015   -#define SPR_PERF4 (0x304)
1016   -#define SPR_PERF5 (0x305)
1017   -#define SPR_PERF6 (0x306)
1018   -#define SPR_PERF7 (0x307)
1019   -#define SPR_PERF8 (0x308)
1020   -#define SPR_PERF9 (0x309)
1021   -#define SPR_PERFA (0x30A)
1022   -#define SPR_PERFB (0x30B)
1023   -#define SPR_PERFC (0x30C)
1024   -#define SPR_PERFD (0x30D)
1025   -#define SPR_PERFE (0x30E)
1026   -#define SPR_PERFF (0x30F)
1027   -#define SPR_UPERF0 (0x310)
1028   -#define SPR_UPERF1 (0x311)
1029   -#define SPR_UPERF2 (0x312)
1030   -#define SPR_UPERF3 (0x313)
1031   -#define SPR_UPERF4 (0x314)
1032   -#define SPR_UPERF5 (0x315)
1033   -#define SPR_UPERF6 (0x316)
1034   -#define SPR_UPERF7 (0x317)
1035   -#define SPR_UPERF8 (0x318)
1036   -#define SPR_UPERF9 (0x319)
1037   -#define SPR_UPERFA (0x31A)
1038   -#define SPR_UPERFB (0x31B)
1039   -#define SPR_UPERFC (0x31C)
1040   -#define SPR_UPERFD (0x31D)
1041   -#define SPR_UPERFE (0x31E)
1042   -#define SPR_UPERFF (0x31F)
1043   -#define SPR_440_INV0 (0x370)
1044   -#define SPR_440_INV1 (0x371)
1045   -#define SPR_440_INV2 (0x372)
1046   -#define SPR_440_INV3 (0x373)
1047   -#define SPR_440_ITV0 (0x374)
1048   -#define SPR_440_ITV1 (0x375)
1049   -#define SPR_440_ITV2 (0x376)
1050   -#define SPR_440_ITV3 (0x377)
1051   -#define SPR_440_CCR1 (0x378)
1052   -#define SPR_DCRIPR (0x37B)
1053   -#define SPR_PPR (0x380)
1054   -#define SPR_440_DNV0 (0x390)
1055   -#define SPR_440_DNV1 (0x391)
1056   -#define SPR_440_DNV2 (0x392)
1057   -#define SPR_440_DNV3 (0x393)
1058   -#define SPR_440_DTV0 (0x394)
1059   -#define SPR_440_DTV1 (0x395)
1060   -#define SPR_440_DTV2 (0x396)
1061   -#define SPR_440_DTV3 (0x397)
1062   -#define SPR_440_DVLIM (0x398)
1063   -#define SPR_440_IVLIM (0x399)
1064   -#define SPR_440_RSTCFG (0x39B)
1065   -#define SPR_BOOKE_DCDBTRL (0x39C)
1066   -#define SPR_BOOKE_DCDBTRH (0x39D)
1067   -#define SPR_BOOKE_ICDBTRL (0x39E)
1068   -#define SPR_BOOKE_ICDBTRH (0x39F)
1069   -#define SPR_UMMCR2 (0x3A0)
1070   -#define SPR_UPMC5 (0x3A1)
1071   -#define SPR_UPMC6 (0x3A2)
1072   -#define SPR_UBAMR (0x3A7)
1073   -#define SPR_UMMCR0 (0x3A8)
1074   -#define SPR_UPMC1 (0x3A9)
1075   -#define SPR_UPMC2 (0x3AA)
1076   -#define SPR_USIAR (0x3AB)
1077   -#define SPR_UMMCR1 (0x3AC)
1078   -#define SPR_UPMC3 (0x3AD)
1079   -#define SPR_UPMC4 (0x3AE)
1080   -#define SPR_USDA (0x3AF)
1081   -#define SPR_40x_ZPR (0x3B0)
1082   -#define SPR_BOOKE_MAS7 (0x3B0)
1083   -#define SPR_620_PMR0 (0x3B0)
1084   -#define SPR_MMCR2 (0x3B0)
1085   -#define SPR_PMC5 (0x3B1)
1086   -#define SPR_40x_PID (0x3B1)
1087   -#define SPR_620_PMR1 (0x3B1)
1088   -#define SPR_PMC6 (0x3B2)
1089   -#define SPR_440_MMUCR (0x3B2)
1090   -#define SPR_620_PMR2 (0x3B2)
1091   -#define SPR_4xx_CCR0 (0x3B3)
1092   -#define SPR_BOOKE_EPLC (0x3B3)
1093   -#define SPR_620_PMR3 (0x3B3)
1094   -#define SPR_405_IAC3 (0x3B4)
1095   -#define SPR_BOOKE_EPSC (0x3B4)
1096   -#define SPR_620_PMR4 (0x3B4)
1097   -#define SPR_405_IAC4 (0x3B5)
1098   -#define SPR_620_PMR5 (0x3B5)
1099   -#define SPR_405_DVC1 (0x3B6)
1100   -#define SPR_620_PMR6 (0x3B6)
1101   -#define SPR_405_DVC2 (0x3B7)
1102   -#define SPR_620_PMR7 (0x3B7)
1103   -#define SPR_BAMR (0x3B7)
1104   -#define SPR_MMCR0 (0x3B8)
1105   -#define SPR_620_PMR8 (0x3B8)
1106   -#define SPR_PMC1 (0x3B9)
1107   -#define SPR_40x_SGR (0x3B9)
1108   -#define SPR_620_PMR9 (0x3B9)
1109   -#define SPR_PMC2 (0x3BA)
1110   -#define SPR_40x_DCWR (0x3BA)
1111   -#define SPR_620_PMRA (0x3BA)
1112   -#define SPR_SIAR (0x3BB)
1113   -#define SPR_405_SLER (0x3BB)
1114   -#define SPR_620_PMRB (0x3BB)
1115   -#define SPR_MMCR1 (0x3BC)
1116   -#define SPR_405_SU0R (0x3BC)
1117   -#define SPR_620_PMRC (0x3BC)
1118   -#define SPR_401_SKR (0x3BC)
1119   -#define SPR_PMC3 (0x3BD)
1120   -#define SPR_405_DBCR1 (0x3BD)
1121   -#define SPR_620_PMRD (0x3BD)
1122   -#define SPR_PMC4 (0x3BE)
1123   -#define SPR_620_PMRE (0x3BE)
1124   -#define SPR_SDA (0x3BF)
1125   -#define SPR_620_PMRF (0x3BF)
1126   -#define SPR_403_VTBL (0x3CC)
1127   -#define SPR_403_VTBU (0x3CD)
1128   -#define SPR_DMISS (0x3D0)
1129   -#define SPR_DCMP (0x3D1)
1130   -#define SPR_HASH1 (0x3D2)
1131   -#define SPR_HASH2 (0x3D3)
1132   -#define SPR_BOOKE_ICDBDR (0x3D3)
1133   -#define SPR_TLBMISS (0x3D4)
1134   -#define SPR_IMISS (0x3D4)
1135   -#define SPR_40x_ESR (0x3D4)
1136   -#define SPR_PTEHI (0x3D5)
1137   -#define SPR_ICMP (0x3D5)
1138   -#define SPR_40x_DEAR (0x3D5)
1139   -#define SPR_PTELO (0x3D6)
1140   -#define SPR_RPA (0x3D6)
1141   -#define SPR_40x_EVPR (0x3D6)
1142   -#define SPR_L3PM (0x3D7)
1143   -#define SPR_403_CDBCR (0x3D7)
1144   -#define SPR_L3OHCR (0x3D8)
1145   -#define SPR_TCR (0x3D8)
1146   -#define SPR_40x_TSR (0x3D8)
1147   -#define SPR_IBR (0x3DA)
1148   -#define SPR_40x_TCR (0x3DA)
1149   -#define SPR_ESASRR (0x3DB)
1150   -#define SPR_40x_PIT (0x3DB)
1151   -#define SPR_403_TBL (0x3DC)
1152   -#define SPR_403_TBU (0x3DD)
1153   -#define SPR_SEBR (0x3DE)
1154   -#define SPR_40x_SRR2 (0x3DE)
1155   -#define SPR_SER (0x3DF)
1156   -#define SPR_40x_SRR3 (0x3DF)
1157   -#define SPR_L3ITCR0 (0x3E8)
1158   -#define SPR_L3ITCR1 (0x3E9)
1159   -#define SPR_L3ITCR2 (0x3EA)
1160   -#define SPR_L3ITCR3 (0x3EB)
1161   -#define SPR_HID0 (0x3F0)
1162   -#define SPR_40x_DBSR (0x3F0)
1163   -#define SPR_HID1 (0x3F1)
1164   -#define SPR_IABR (0x3F2)
1165   -#define SPR_40x_DBCR0 (0x3F2)
1166   -#define SPR_601_HID2 (0x3F2)
1167   -#define SPR_E500_L1CSR0 (0x3F2)
1168   -#define SPR_ICTRL (0x3F3)
1169   -#define SPR_HID2 (0x3F3)
1170   -#define SPR_E500_L1CSR1 (0x3F3)
1171   -#define SPR_440_DBDR (0x3F3)
1172   -#define SPR_LDSTDB (0x3F4)
1173   -#define SPR_40x_IAC1 (0x3F4)
1174   -#define SPR_MMUCSR0 (0x3F4)
1175   -#define SPR_DABR (0x3F5)
  825 +#define SPR_MQ (0x000)
  826 +#define SPR_XER (0x001)
  827 +#define SPR_601_VRTCU (0x004)
  828 +#define SPR_601_VRTCL (0x005)
  829 +#define SPR_601_UDECR (0x006)
  830 +#define SPR_LR (0x008)
  831 +#define SPR_CTR (0x009)
  832 +#define SPR_DSISR (0x012)
  833 +#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
  834 +#define SPR_601_RTCU (0x014)
  835 +#define SPR_601_RTCL (0x015)
  836 +#define SPR_DECR (0x016)
  837 +#define SPR_SDR1 (0x019)
  838 +#define SPR_SRR0 (0x01A)
  839 +#define SPR_SRR1 (0x01B)
  840 +#define SPR_AMR (0x01D)
  841 +#define SPR_BOOKE_PID (0x030)
  842 +#define SPR_BOOKE_DECAR (0x036)
  843 +#define SPR_BOOKE_CSRR0 (0x03A)
  844 +#define SPR_BOOKE_CSRR1 (0x03B)
  845 +#define SPR_BOOKE_DEAR (0x03D)
  846 +#define SPR_BOOKE_ESR (0x03E)
  847 +#define SPR_BOOKE_IVPR (0x03F)
  848 +#define SPR_MPC_EIE (0x050)
  849 +#define SPR_MPC_EID (0x051)
  850 +#define SPR_MPC_NRI (0x052)
  851 +#define SPR_CTRL (0x088)
  852 +#define SPR_MPC_CMPA (0x090)
  853 +#define SPR_MPC_CMPB (0x091)
  854 +#define SPR_MPC_CMPC (0x092)
  855 +#define SPR_MPC_CMPD (0x093)
  856 +#define SPR_MPC_ECR (0x094)
  857 +#define SPR_MPC_DER (0x095)
  858 +#define SPR_MPC_COUNTA (0x096)
  859 +#define SPR_MPC_COUNTB (0x097)
  860 +#define SPR_UCTRL (0x098)
  861 +#define SPR_MPC_CMPE (0x098)
  862 +#define SPR_MPC_CMPF (0x099)
  863 +#define SPR_MPC_CMPG (0x09A)
  864 +#define SPR_MPC_CMPH (0x09B)
  865 +#define SPR_MPC_LCTRL1 (0x09C)
  866 +#define SPR_MPC_LCTRL2 (0x09D)
  867 +#define SPR_MPC_ICTRL (0x09E)
  868 +#define SPR_MPC_BAR (0x09F)
  869 +#define SPR_VRSAVE (0x100)
  870 +#define SPR_USPRG0 (0x100)
  871 +#define SPR_USPRG1 (0x101)
  872 +#define SPR_USPRG2 (0x102)
  873 +#define SPR_USPRG3 (0x103)
  874 +#define SPR_USPRG4 (0x104)
  875 +#define SPR_USPRG5 (0x105)
  876 +#define SPR_USPRG6 (0x106)
  877 +#define SPR_USPRG7 (0x107)
  878 +#define SPR_VTBL (0x10C)
  879 +#define SPR_VTBU (0x10D)
  880 +#define SPR_SPRG0 (0x110)
  881 +#define SPR_SPRG1 (0x111)
  882 +#define SPR_SPRG2 (0x112)
  883 +#define SPR_SPRG3 (0x113)
  884 +#define SPR_SPRG4 (0x114)
  885 +#define SPR_SCOMC (0x114)
  886 +#define SPR_SPRG5 (0x115)
  887 +#define SPR_SCOMD (0x115)
  888 +#define SPR_SPRG6 (0x116)
  889 +#define SPR_SPRG7 (0x117)
  890 +#define SPR_ASR (0x118)
  891 +#define SPR_EAR (0x11A)
  892 +#define SPR_TBL (0x11C)
  893 +#define SPR_TBU (0x11D)
  894 +#define SPR_TBU40 (0x11E)
  895 +#define SPR_SVR (0x11E)
  896 +#define SPR_BOOKE_PIR (0x11E)
  897 +#define SPR_PVR (0x11F)
  898 +#define SPR_HSPRG0 (0x130)
  899 +#define SPR_BOOKE_DBSR (0x130)
  900 +#define SPR_HSPRG1 (0x131)
  901 +#define SPR_HDSISR (0x132)
  902 +#define SPR_HDAR (0x133)
  903 +#define SPR_BOOKE_DBCR0 (0x134)
  904 +#define SPR_IBCR (0x135)
  905 +#define SPR_PURR (0x135)
  906 +#define SPR_BOOKE_DBCR1 (0x135)
  907 +#define SPR_DBCR (0x136)
  908 +#define SPR_HDEC (0x136)
  909 +#define SPR_BOOKE_DBCR2 (0x136)
  910 +#define SPR_HIOR (0x137)
  911 +#define SPR_MBAR (0x137)
  912 +#define SPR_RMOR (0x138)
  913 +#define SPR_BOOKE_IAC1 (0x138)
  914 +#define SPR_HRMOR (0x139)
  915 +#define SPR_BOOKE_IAC2 (0x139)
  916 +#define SPR_HSRR0 (0x13A)
  917 +#define SPR_BOOKE_IAC3 (0x13A)
  918 +#define SPR_HSRR1 (0x13B)
  919 +#define SPR_BOOKE_IAC4 (0x13B)
  920 +#define SPR_LPCR (0x13C)
  921 +#define SPR_BOOKE_DAC1 (0x13C)
  922 +#define SPR_LPIDR (0x13D)
  923 +#define SPR_DABR2 (0x13D)
  924 +#define SPR_BOOKE_DAC2 (0x13D)
  925 +#define SPR_BOOKE_DVC1 (0x13E)
  926 +#define SPR_BOOKE_DVC2 (0x13F)
  927 +#define SPR_BOOKE_TSR (0x150)
  928 +#define SPR_BOOKE_TCR (0x154)
  929 +#define SPR_BOOKE_IVOR0 (0x190)
  930 +#define SPR_BOOKE_IVOR1 (0x191)
  931 +#define SPR_BOOKE_IVOR2 (0x192)
  932 +#define SPR_BOOKE_IVOR3 (0x193)
  933 +#define SPR_BOOKE_IVOR4 (0x194)
  934 +#define SPR_BOOKE_IVOR5 (0x195)
  935 +#define SPR_BOOKE_IVOR6 (0x196)
  936 +#define SPR_BOOKE_IVOR7 (0x197)
  937 +#define SPR_BOOKE_IVOR8 (0x198)
  938 +#define SPR_BOOKE_IVOR9 (0x199)
  939 +#define SPR_BOOKE_IVOR10 (0x19A)
  940 +#define SPR_BOOKE_IVOR11 (0x19B)
  941 +#define SPR_BOOKE_IVOR12 (0x19C)
  942 +#define SPR_BOOKE_IVOR13 (0x19D)
  943 +#define SPR_BOOKE_IVOR14 (0x19E)
  944 +#define SPR_BOOKE_IVOR15 (0x19F)
  945 +#define SPR_BOOKE_SPEFSCR (0x200)
  946 +#define SPR_Exxx_BBEAR (0x201)
  947 +#define SPR_Exxx_BBTAR (0x202)
  948 +#define SPR_Exxx_L1CFG0 (0x203)
  949 +#define SPR_Exxx_NPIDR (0x205)
  950 +#define SPR_ATBL (0x20E)
  951 +#define SPR_ATBU (0x20F)
  952 +#define SPR_IBAT0U (0x210)
  953 +#define SPR_BOOKE_IVOR32 (0x210)
  954 +#define SPR_RCPU_MI_GRA (0x210)
  955 +#define SPR_IBAT0L (0x211)
  956 +#define SPR_BOOKE_IVOR33 (0x211)
  957 +#define SPR_IBAT1U (0x212)
  958 +#define SPR_BOOKE_IVOR34 (0x212)
  959 +#define SPR_IBAT1L (0x213)
  960 +#define SPR_BOOKE_IVOR35 (0x213)
  961 +#define SPR_IBAT2U (0x214)
  962 +#define SPR_BOOKE_IVOR36 (0x214)
  963 +#define SPR_IBAT2L (0x215)
  964 +#define SPR_BOOKE_IVOR37 (0x215)
  965 +#define SPR_IBAT3U (0x216)
  966 +#define SPR_IBAT3L (0x217)
  967 +#define SPR_DBAT0U (0x218)
  968 +#define SPR_RCPU_L2U_GRA (0x218)
  969 +#define SPR_DBAT0L (0x219)
  970 +#define SPR_DBAT1U (0x21A)
  971 +#define SPR_DBAT1L (0x21B)
  972 +#define SPR_DBAT2U (0x21C)
  973 +#define SPR_DBAT2L (0x21D)
  974 +#define SPR_DBAT3U (0x21E)
  975 +#define SPR_DBAT3L (0x21F)
  976 +#define SPR_IBAT4U (0x230)
  977 +#define SPR_RPCU_BBCMCR (0x230)
  978 +#define SPR_MPC_IC_CST (0x230)
  979 +#define SPR_Exxx_CTXCR (0x230)
  980 +#define SPR_IBAT4L (0x231)
  981 +#define SPR_MPC_IC_ADR (0x231)
  982 +#define SPR_Exxx_DBCR3 (0x231)
  983 +#define SPR_IBAT5U (0x232)
  984 +#define SPR_MPC_IC_DAT (0x232)
  985 +#define SPR_Exxx_DBCNT (0x232)
  986 +#define SPR_IBAT5L (0x233)
  987 +#define SPR_IBAT6U (0x234)
  988 +#define SPR_IBAT6L (0x235)
  989 +#define SPR_IBAT7U (0x236)
  990 +#define SPR_IBAT7L (0x237)
  991 +#define SPR_DBAT4U (0x238)
  992 +#define SPR_RCPU_L2U_MCR (0x238)
  993 +#define SPR_MPC_DC_CST (0x238)
  994 +#define SPR_Exxx_ALTCTXCR (0x238)
  995 +#define SPR_DBAT4L (0x239)
  996 +#define SPR_MPC_DC_ADR (0x239)
  997 +#define SPR_DBAT5U (0x23A)
  998 +#define SPR_BOOKE_MCSRR0 (0x23A)
  999 +#define SPR_MPC_DC_DAT (0x23A)
  1000 +#define SPR_DBAT5L (0x23B)
  1001 +#define SPR_BOOKE_MCSRR1 (0x23B)
  1002 +#define SPR_DBAT6U (0x23C)
  1003 +#define SPR_BOOKE_MCSR (0x23C)
  1004 +#define SPR_DBAT6L (0x23D)
  1005 +#define SPR_Exxx_MCAR (0x23D)
  1006 +#define SPR_DBAT7U (0x23E)
  1007 +#define SPR_BOOKE_DSRR0 (0x23E)
  1008 +#define SPR_DBAT7L (0x23F)
  1009 +#define SPR_BOOKE_DSRR1 (0x23F)
  1010 +#define SPR_BOOKE_SPRG8 (0x25C)
  1011 +#define SPR_BOOKE_SPRG9 (0x25D)
  1012 +#define SPR_BOOKE_MAS0 (0x270)
  1013 +#define SPR_BOOKE_MAS1 (0x271)
  1014 +#define SPR_BOOKE_MAS2 (0x272)
  1015 +#define SPR_BOOKE_MAS3 (0x273)
  1016 +#define SPR_BOOKE_MAS4 (0x274)
  1017 +#define SPR_BOOKE_MAS5 (0x275)
  1018 +#define SPR_BOOKE_MAS6 (0x276)
  1019 +#define SPR_BOOKE_PID1 (0x279)
  1020 +#define SPR_BOOKE_PID2 (0x27A)
  1021 +#define SPR_MPC_DPDR (0x280)
  1022 +#define SPR_MPC_IMMR (0x288)
  1023 +#define SPR_BOOKE_TLB0CFG (0x2B0)
  1024 +#define SPR_BOOKE_TLB1CFG (0x2B1)
  1025 +#define SPR_BOOKE_TLB2CFG (0x2B2)
  1026 +#define SPR_BOOKE_TLB3CFG (0x2B3)
  1027 +#define SPR_BOOKE_EPR (0x2BE)
  1028 +#define SPR_PERF0 (0x300)
  1029 +#define SPR_RCPU_MI_RBA0 (0x300)
  1030 +#define SPR_MPC_MI_CTR (0x300)
  1031 +#define SPR_PERF1 (0x301)
  1032 +#define SPR_RCPU_MI_RBA1 (0x301)
  1033 +#define SPR_PERF2 (0x302)
  1034 +#define SPR_RCPU_MI_RBA2 (0x302)
  1035 +#define SPR_MPC_MI_AP (0x302)
  1036 +#define SPR_PERF3 (0x303)
  1037 +#define SPR_RCPU_MI_RBA3 (0x303)
  1038 +#define SPR_MPC_MI_EPN (0x303)
  1039 +#define SPR_PERF4 (0x304)
  1040 +#define SPR_PERF5 (0x305)
  1041 +#define SPR_MPC_MI_TWC (0x305)
  1042 +#define SPR_PERF6 (0x306)
  1043 +#define SPR_MPC_MI_RPN (0x306)
  1044 +#define SPR_PERF7 (0x307)
  1045 +#define SPR_PERF8 (0x308)
  1046 +#define SPR_RCPU_L2U_RBA0 (0x308)
  1047 +#define SPR_MPC_MD_CTR (0x308)
  1048 +#define SPR_PERF9 (0x309)
  1049 +#define SPR_RCPU_L2U_RBA1 (0x309)
  1050 +#define SPR_MPC_MD_CASID (0x309)
  1051 +#define SPR_PERFA (0x30A)
  1052 +#define SPR_RCPU_L2U_RBA2 (0x30A)
  1053 +#define SPR_MPC_MD_AP (0x30A)
  1054 +#define SPR_PERFB (0x30B)
  1055 +#define SPR_RCPU_L2U_RBA3 (0x30B)
  1056 +#define SPR_MPC_MD_EPN (0x30B)
  1057 +#define SPR_PERFC (0x30C)
  1058 +#define SPR_MPC_MD_TWB (0x30C)
  1059 +#define SPR_PERFD (0x30D)
  1060 +#define SPR_MPC_MD_TWC (0x30D)
  1061 +#define SPR_PERFE (0x30E)
  1062 +#define SPR_MPC_MD_RPN (0x30E)
  1063 +#define SPR_PERFF (0x30F)
  1064 +#define SPR_MPC_MD_TW (0x30F)
  1065 +#define SPR_UPERF0 (0x310)
  1066 +#define SPR_UPERF1 (0x311)
  1067 +#define SPR_UPERF2 (0x312)
  1068 +#define SPR_UPERF3 (0x313)
  1069 +#define SPR_UPERF4 (0x314)
  1070 +#define SPR_UPERF5 (0x315)
  1071 +#define SPR_UPERF6 (0x316)
  1072 +#define SPR_UPERF7 (0x317)
  1073 +#define SPR_UPERF8 (0x318)
  1074 +#define SPR_UPERF9 (0x319)
  1075 +#define SPR_UPERFA (0x31A)
  1076 +#define SPR_UPERFB (0x31B)
  1077 +#define SPR_UPERFC (0x31C)
  1078 +#define SPR_UPERFD (0x31D)
  1079 +#define SPR_UPERFE (0x31E)
  1080 +#define SPR_UPERFF (0x31F)
  1081 +#define SPR_RCPU_MI_RA0 (0x320)
  1082 +#define SPR_MPC_MI_DBCAM (0x320)
  1083 +#define SPR_RCPU_MI_RA1 (0x321)
  1084 +#define SPR_MPC_MI_DBRAM0 (0x321)
  1085 +#define SPR_RCPU_MI_RA2 (0x322)
  1086 +#define SPR_MPC_MI_DBRAM1 (0x322)
  1087 +#define SPR_RCPU_MI_RA3 (0x323)
  1088 +#define SPR_RCPU_L2U_RA0 (0x328)
  1089 +#define SPR_MPC_MD_DBCAM (0x328)
  1090 +#define SPR_RCPU_L2U_RA1 (0x329)
  1091 +#define SPR_MPC_MD_DBRAM0 (0x329)
  1092 +#define SPR_RCPU_L2U_RA2 (0x32A)
  1093 +#define SPR_MPC_MD_DBRAM1 (0x32A)
  1094 +#define SPR_RCPU_L2U_RA3 (0x32B)
  1095 +#define SPR_440_INV0 (0x370)
  1096 +#define SPR_440_INV1 (0x371)
  1097 +#define SPR_440_INV2 (0x372)
  1098 +#define SPR_440_INV3 (0x373)
  1099 +#define SPR_440_ITV0 (0x374)
  1100 +#define SPR_440_ITV1 (0x375)
  1101 +#define SPR_440_ITV2 (0x376)
  1102 +#define SPR_440_ITV3 (0x377)
  1103 +#define SPR_440_CCR1 (0x378)
  1104 +#define SPR_DCRIPR (0x37B)
  1105 +#define SPR_PPR (0x380)
  1106 +#define SPR_440_DNV0 (0x390)
  1107 +#define SPR_440_DNV1 (0x391)
  1108 +#define SPR_440_DNV2 (0x392)
  1109 +#define SPR_440_DNV3 (0x393)
  1110 +#define SPR_440_DTV0 (0x394)
  1111 +#define SPR_440_DTV1 (0x395)
  1112 +#define SPR_440_DTV2 (0x396)
  1113 +#define SPR_440_DTV3 (0x397)
  1114 +#define SPR_440_DVLIM (0x398)
  1115 +#define SPR_440_IVLIM (0x399)
  1116 +#define SPR_440_RSTCFG (0x39B)
  1117 +#define SPR_BOOKE_DCDBTRL (0x39C)
  1118 +#define SPR_BOOKE_DCDBTRH (0x39D)
  1119 +#define SPR_BOOKE_ICDBTRL (0x39E)
  1120 +#define SPR_BOOKE_ICDBTRH (0x39F)
  1121 +#define SPR_UMMCR2 (0x3A0)
  1122 +#define SPR_UPMC5 (0x3A1)
  1123 +#define SPR_UPMC6 (0x3A2)
  1124 +#define SPR_UBAMR (0x3A7)
  1125 +#define SPR_UMMCR0 (0x3A8)
  1126 +#define SPR_UPMC1 (0x3A9)
  1127 +#define SPR_UPMC2 (0x3AA)
  1128 +#define SPR_USIAR (0x3AB)
  1129 +#define SPR_UMMCR1 (0x3AC)
  1130 +#define SPR_UPMC3 (0x3AD)
  1131 +#define SPR_UPMC4 (0x3AE)
  1132 +#define SPR_USDA (0x3AF)
  1133 +#define SPR_40x_ZPR (0x3B0)
  1134 +#define SPR_BOOKE_MAS7 (0x3B0)
  1135 +#define SPR_620_PMR0 (0x3B0)
  1136 +#define SPR_MMCR2 (0x3B0)
  1137 +#define SPR_PMC5 (0x3B1)
  1138 +#define SPR_40x_PID (0x3B1)
  1139 +#define SPR_620_PMR1 (0x3B1)
  1140 +#define SPR_PMC6 (0x3B2)
  1141 +#define SPR_440_MMUCR (0x3B2)
  1142 +#define SPR_620_PMR2 (0x3B2)
  1143 +#define SPR_4xx_CCR0 (0x3B3)
  1144 +#define SPR_BOOKE_EPLC (0x3B3)
  1145 +#define SPR_620_PMR3 (0x3B3)
  1146 +#define SPR_405_IAC3 (0x3B4)
  1147 +#define SPR_BOOKE_EPSC (0x3B4)
  1148 +#define SPR_620_PMR4 (0x3B4)
  1149 +#define SPR_405_IAC4 (0x3B5)
  1150 +#define SPR_620_PMR5 (0x3B5)
  1151 +#define SPR_405_DVC1 (0x3B6)
  1152 +#define SPR_620_PMR6 (0x3B6)
  1153 +#define SPR_405_DVC2 (0x3B7)
  1154 +#define SPR_620_PMR7 (0x3B7)
  1155 +#define SPR_BAMR (0x3B7)
  1156 +#define SPR_MMCR0 (0x3B8)
  1157 +#define SPR_620_PMR8 (0x3B8)
  1158 +#define SPR_PMC1 (0x3B9)
  1159 +#define SPR_40x_SGR (0x3B9)
  1160 +#define SPR_620_PMR9 (0x3B9)
  1161 +#define SPR_PMC2 (0x3BA)
  1162 +#define SPR_40x_DCWR (0x3BA)
  1163 +#define SPR_620_PMRA (0x3BA)
  1164 +#define SPR_SIAR (0x3BB)
  1165 +#define SPR_405_SLER (0x3BB)
  1166 +#define SPR_620_PMRB (0x3BB)
  1167 +#define SPR_MMCR1 (0x3BC)
  1168 +#define SPR_405_SU0R (0x3BC)
  1169 +#define SPR_620_PMRC (0x3BC)
  1170 +#define SPR_401_SKR (0x3BC)
  1171 +#define SPR_PMC3 (0x3BD)
  1172 +#define SPR_405_DBCR1 (0x3BD)
  1173 +#define SPR_620_PMRD (0x3BD)
  1174 +#define SPR_PMC4 (0x3BE)
  1175 +#define SPR_620_PMRE (0x3BE)
  1176 +#define SPR_SDA (0x3BF)
  1177 +#define SPR_620_PMRF (0x3BF)
  1178 +#define SPR_403_VTBL (0x3CC)
  1179 +#define SPR_403_VTBU (0x3CD)
  1180 +#define SPR_DMISS (0x3D0)
  1181 +#define SPR_DCMP (0x3D1)
  1182 +#define SPR_HASH1 (0x3D2)
  1183 +#define SPR_HASH2 (0x3D3)
  1184 +#define SPR_BOOKE_ICDBDR (0x3D3)
  1185 +#define SPR_TLBMISS (0x3D4)
  1186 +#define SPR_IMISS (0x3D4)
  1187 +#define SPR_40x_ESR (0x3D4)
  1188 +#define SPR_PTEHI (0x3D5)
  1189 +#define SPR_ICMP (0x3D5)
  1190 +#define SPR_40x_DEAR (0x3D5)
  1191 +#define SPR_PTELO (0x3D6)
  1192 +#define SPR_RPA (0x3D6)
  1193 +#define SPR_40x_EVPR (0x3D6)
  1194 +#define SPR_L3PM (0x3D7)
  1195 +#define SPR_403_CDBCR (0x3D7)
  1196 +#define SPR_L3OHCR (0x3D8)
  1197 +#define SPR_TCR (0x3D8)
  1198 +#define SPR_40x_TSR (0x3D8)
  1199 +#define SPR_IBR (0x3DA)
  1200 +#define SPR_40x_TCR (0x3DA)
  1201 +#define SPR_ESASRR (0x3DB)
  1202 +#define SPR_40x_PIT (0x3DB)
  1203 +#define SPR_403_TBL (0x3DC)
  1204 +#define SPR_403_TBU (0x3DD)
  1205 +#define SPR_SEBR (0x3DE)
  1206 +#define SPR_40x_SRR2 (0x3DE)
  1207 +#define SPR_SER (0x3DF)
  1208 +#define SPR_40x_SRR3 (0x3DF)
  1209 +#define SPR_L3ITCR0 (0x3E8)
  1210 +#define SPR_L3ITCR1 (0x3E9)
  1211 +#define SPR_L3ITCR2 (0x3EA)
  1212 +#define SPR_L3ITCR3 (0x3EB)
  1213 +#define SPR_HID0 (0x3F0)
  1214 +#define SPR_40x_DBSR (0x3F0)
  1215 +#define SPR_HID1 (0x3F1)
  1216 +#define SPR_IABR (0x3F2)
  1217 +#define SPR_40x_DBCR0 (0x3F2)
  1218 +#define SPR_601_HID2 (0x3F2)
  1219 +#define SPR_Exxx_L1CSR0 (0x3F2)
  1220 +#define SPR_ICTRL (0x3F3)
  1221 +#define SPR_HID2 (0x3F3)
  1222 +#define SPR_Exxx_L1CSR1 (0x3F3)
  1223 +#define SPR_440_DBDR (0x3F3)
  1224 +#define SPR_LDSTDB (0x3F4)
  1225 +#define SPR_40x_IAC1 (0x3F4)
  1226 +#define SPR_MMUCSR0 (0x3F4)
  1227 +#define SPR_DABR (0x3F5)
1176 1228 #define DABR_MASK (~(target_ulong)0x7)
1177   -#define SPR_E500_BUCSR (0x3F5)
1178   -#define SPR_40x_IAC2 (0x3F5)
1179   -#define SPR_601_HID5 (0x3F5)
1180   -#define SPR_40x_DAC1 (0x3F6)
1181   -#define SPR_MSSCR0 (0x3F6)
1182   -#define SPR_970_HID5 (0x3F6)
1183   -#define SPR_MSSSR0 (0x3F7)
1184   -#define SPR_DABRX (0x3F7)
1185   -#define SPR_40x_DAC2 (0x3F7)
1186   -#define SPR_MMUCFG (0x3F7)
1187   -#define SPR_LDSTCR (0x3F8)
1188   -#define SPR_L2PMCR (0x3F8)
1189   -#define SPR_750_HID2 (0x3F8)
1190   -#define SPR_620_HID8 (0x3F8)
1191   -#define SPR_L2CR (0x3F9)
1192   -#define SPR_620_HID9 (0x3F9)
1193   -#define SPR_L3CR (0x3FA)
1194   -#define SPR_IABR2 (0x3FA)
1195   -#define SPR_40x_DCCR (0x3FA)
1196   -#define SPR_ICTC (0x3FB)
1197   -#define SPR_40x_ICCR (0x3FB)
1198   -#define SPR_THRM1 (0x3FC)
1199   -#define SPR_403_PBL1 (0x3FC)
1200   -#define SPR_SP (0x3FD)
1201   -#define SPR_THRM2 (0x3FD)
1202   -#define SPR_403_PBU1 (0x3FD)
1203   -#define SPR_604_HID13 (0x3FD)
1204   -#define SPR_LT (0x3FE)
1205   -#define SPR_THRM3 (0x3FE)
1206   -#define SPR_FPECR (0x3FE)
1207   -#define SPR_403_PBL2 (0x3FE)
1208   -#define SPR_PIR (0x3FF)
1209   -#define SPR_403_PBU2 (0x3FF)
1210   -#define SPR_601_HID15 (0x3FF)
1211   -#define SPR_604_HID15 (0x3FF)
1212   -#define SPR_E500_SVR (0x3FF)
  1229 +#define SPR_Exxx_BUCSR (0x3F5)
  1230 +#define SPR_40x_IAC2 (0x3F5)
  1231 +#define SPR_601_HID5 (0x3F5)
  1232 +#define SPR_40x_DAC1 (0x3F6)
  1233 +#define SPR_MSSCR0 (0x3F6)
  1234 +#define SPR_970_HID5 (0x3F6)
  1235 +#define SPR_MSSSR0 (0x3F7)
  1236 +#define SPR_DABRX (0x3F7)
  1237 +#define SPR_40x_DAC2 (0x3F7)
  1238 +#define SPR_MMUCFG (0x3F7)
  1239 +#define SPR_LDSTCR (0x3F8)
  1240 +#define SPR_L2PMCR (0x3F8)
  1241 +#define SPR_750_HID2 (0x3F8)
  1242 +#define SPR_620_HID8 (0x3F8)
  1243 +#define SPR_Exxx_L1FINV0 (0x3F8)
  1244 +#define SPR_L2CR (0x3F9)
  1245 +#define SPR_620_HID9 (0x3F9)
  1246 +#define SPR_L3CR (0x3FA)
  1247 +#define SPR_IABR2 (0x3FA)
  1248 +#define SPR_40x_DCCR (0x3FA)
  1249 +#define SPR_ICTC (0x3FB)
  1250 +#define SPR_40x_ICCR (0x3FB)
  1251 +#define SPR_THRM1 (0x3FC)
  1252 +#define SPR_403_PBL1 (0x3FC)
  1253 +#define SPR_SP (0x3FD)
  1254 +#define SPR_THRM2 (0x3FD)
  1255 +#define SPR_403_PBU1 (0x3FD)
  1256 +#define SPR_604_HID13 (0x3FD)
  1257 +#define SPR_LT (0x3FE)
  1258 +#define SPR_THRM3 (0x3FE)
  1259 +#define SPR_RCPU_FPECR (0x3FE)
  1260 +#define SPR_403_PBL2 (0x3FE)
  1261 +#define SPR_PIR (0x3FF)
  1262 +#define SPR_403_PBU2 (0x3FF)
  1263 +#define SPR_601_HID15 (0x3FF)
  1264 +#define SPR_604_HID15 (0x3FF)
  1265 +#define SPR_E500_SVR (0x3FF)
1213 1266  
1214 1267 /*****************************************************************************/
1215 1268 /* Memory access type :
... ...