gwj / at91sam9263 · Commits

Commit 80d11f4467c49c593c9356b97de6c0b4e12d73c1

Authored by j_mayer
1 parent b4095fed

Add definitions for Freescale PowerPC implementations, 

ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.
Make those CPUs and PowerPC 440 available for user-mode emulation,
  thus providing a way of testing their implementation specific instructions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3681 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 3936 additions and 2292 deletions
target-ppc/cpu.h
  View file @80d11f4
... ... @@ -822,394 +822,447 @@ static inline int cpu_mmu_index (CPUState *env)
822 822 #define xer_bc env->xer[0]
823 823  
824 824 /* SPR definitions */
825   -#define SPR_MQ (0x000)
826   -#define SPR_XER (0x001)
827   -#define SPR_601_VRTCU (0x004)
828   -#define SPR_601_VRTCL (0x005)
829   -#define SPR_601_UDECR (0x006)
830   -#define SPR_LR (0x008)
831   -#define SPR_CTR (0x009)
832   -#define SPR_DSISR (0x012)
833   -#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
834   -#define SPR_601_RTCU (0x014)
835   -#define SPR_601_RTCL (0x015)
836   -#define SPR_DECR (0x016)
837   -#define SPR_SDR1 (0x019)
838   -#define SPR_SRR0 (0x01A)
839   -#define SPR_SRR1 (0x01B)
840   -#define SPR_AMR (0x01D)
841   -#define SPR_BOOKE_PID (0x030)
842   -#define SPR_BOOKE_DECAR (0x036)
843   -#define SPR_BOOKE_CSRR0 (0x03A)
844   -#define SPR_BOOKE_CSRR1 (0x03B)
845   -#define SPR_BOOKE_DEAR (0x03D)
846   -#define SPR_BOOKE_ESR (0x03E)
847   -#define SPR_BOOKE_IVPR (0x03F)
848   -#define SPR_8xx_EIE (0x050)
849   -#define SPR_8xx_EID (0x051)
850   -#define SPR_8xx_NRE (0x052)
851   -#define SPR_CTRL (0x088)
852   -#define SPR_58x_CMPA (0x090)
853   -#define SPR_58x_CMPB (0x091)
854   -#define SPR_58x_CMPC (0x092)
855   -#define SPR_58x_CMPD (0x093)
856   -#define SPR_58x_ICR (0x094)
857   -#define SPR_58x_DER (0x094)
858   -#define SPR_58x_COUNTA (0x096)
859   -#define SPR_58x_COUNTB (0x097)
860   -#define SPR_UCTRL (0x098)
861   -#define SPR_58x_CMPE (0x098)
862   -#define SPR_58x_CMPF (0x099)
863   -#define SPR_58x_CMPG (0x09A)
864   -#define SPR_58x_CMPH (0x09B)
865   -#define SPR_58x_LCTRL1 (0x09C)
866   -#define SPR_58x_LCTRL2 (0x09D)
867   -#define SPR_58x_ICTRL (0x09E)
868   -#define SPR_58x_BAR (0x09F)
869   -#define SPR_VRSAVE (0x100)
870   -#define SPR_USPRG0 (0x100)
871   -#define SPR_USPRG1 (0x101)
872   -#define SPR_USPRG2 (0x102)
873   -#define SPR_USPRG3 (0x103)
874   -#define SPR_USPRG4 (0x104)
875   -#define SPR_USPRG5 (0x105)
876   -#define SPR_USPRG6 (0x106)
877   -#define SPR_USPRG7 (0x107)
878   -#define SPR_VTBL (0x10C)
879   -#define SPR_VTBU (0x10D)
880   -#define SPR_SPRG0 (0x110)
881   -#define SPR_SPRG1 (0x111)
882   -#define SPR_SPRG2 (0x112)
883   -#define SPR_SPRG3 (0x113)
884   -#define SPR_SPRG4 (0x114)
885   -#define SPR_SCOMC (0x114)
886   -#define SPR_SPRG5 (0x115)
887   -#define SPR_SCOMD (0x115)
888   -#define SPR_SPRG6 (0x116)
889   -#define SPR_SPRG7 (0x117)
890   -#define SPR_ASR (0x118)
891   -#define SPR_EAR (0x11A)
892   -#define SPR_TBL (0x11C)
893   -#define SPR_TBU (0x11D)
894   -#define SPR_TBU40 (0x11E)
895   -#define SPR_SVR (0x11E)
896   -#define SPR_BOOKE_PIR (0x11E)
897   -#define SPR_PVR (0x11F)
898   -#define SPR_HSPRG0 (0x130)
899   -#define SPR_BOOKE_DBSR (0x130)
900   -#define SPR_HSPRG1 (0x131)
901   -#define SPR_HDSISR (0x132)
902   -#define SPR_HDAR (0x133)
903   -#define SPR_BOOKE_DBCR0 (0x134)
904   -#define SPR_IBCR (0x135)
905   -#define SPR_PURR (0x135)
906   -#define SPR_BOOKE_DBCR1 (0x135)
907   -#define SPR_DBCR (0x136)
908   -#define SPR_HDEC (0x136)
909   -#define SPR_BOOKE_DBCR2 (0x136)
910   -#define SPR_HIOR (0x137)
911   -#define SPR_MBAR (0x137)
912   -#define SPR_RMOR (0x138)
913   -#define SPR_BOOKE_IAC1 (0x138)
914   -#define SPR_HRMOR (0x139)
915   -#define SPR_BOOKE_IAC2 (0x139)
916   -#define SPR_HSRR0 (0x13A)
917   -#define SPR_BOOKE_IAC3 (0x13A)
918   -#define SPR_HSRR1 (0x13B)
919   -#define SPR_BOOKE_IAC4 (0x13B)
920   -#define SPR_LPCR (0x13C)
921   -#define SPR_BOOKE_DAC1 (0x13C)
922   -#define SPR_LPIDR (0x13D)
923   -#define SPR_DABR2 (0x13D)
924   -#define SPR_BOOKE_DAC2 (0x13D)
925   -#define SPR_BOOKE_DVC1 (0x13E)
926   -#define SPR_BOOKE_DVC2 (0x13F)
927   -#define SPR_BOOKE_TSR (0x150)
928   -#define SPR_BOOKE_TCR (0x154)
929   -#define SPR_BOOKE_IVOR0 (0x190)
930   -#define SPR_BOOKE_IVOR1 (0x191)
931   -#define SPR_BOOKE_IVOR2 (0x192)
932   -#define SPR_BOOKE_IVOR3 (0x193)
933   -#define SPR_BOOKE_IVOR4 (0x194)
934   -#define SPR_BOOKE_IVOR5 (0x195)
935   -#define SPR_BOOKE_IVOR6 (0x196)
936   -#define SPR_BOOKE_IVOR7 (0x197)
937   -#define SPR_BOOKE_IVOR8 (0x198)
938   -#define SPR_BOOKE_IVOR9 (0x199)
939   -#define SPR_BOOKE_IVOR10 (0x19A)
940   -#define SPR_BOOKE_IVOR11 (0x19B)
941   -#define SPR_BOOKE_IVOR12 (0x19C)
942   -#define SPR_BOOKE_IVOR13 (0x19D)
943   -#define SPR_BOOKE_IVOR14 (0x19E)
944   -#define SPR_BOOKE_IVOR15 (0x19F)
945   -#define SPR_BOOKE_SPEFSCR (0x200)
946   -#define SPR_E500_BBEAR (0x201)
947   -#define SPR_E500_BBTAR (0x202)
948   -#define SPR_ATBL (0x20E)
949   -#define SPR_ATBU (0x20F)
950   -#define SPR_IBAT0U (0x210)
951   -#define SPR_BOOKE_IVOR32 (0x210)
952   -#define SPR_IBAT0L (0x211)
953   -#define SPR_BOOKE_IVOR33 (0x211)
954   -#define SPR_IBAT1U (0x212)
955   -#define SPR_BOOKE_IVOR34 (0x212)
956   -#define SPR_IBAT1L (0x213)
957   -#define SPR_BOOKE_IVOR35 (0x213)
958   -#define SPR_IBAT2U (0x214)
959   -#define SPR_BOOKE_IVOR36 (0x214)
960   -#define SPR_IBAT2L (0x215)
961   -#define SPR_E500_L1CFG0 (0x215)
962   -#define SPR_BOOKE_IVOR37 (0x215)
963   -#define SPR_IBAT3U (0x216)
964   -#define SPR_E500_L1CFG1 (0x216)
965   -#define SPR_IBAT3L (0x217)
966   -#define SPR_DBAT0U (0x218)
967   -#define SPR_DBAT0L (0x219)
968   -#define SPR_DBAT1U (0x21A)
969   -#define SPR_DBAT1L (0x21B)
970   -#define SPR_DBAT2U (0x21C)
971   -#define SPR_DBAT2L (0x21D)
972   -#define SPR_DBAT3U (0x21E)
973   -#define SPR_DBAT3L (0x21F)
974   -#define SPR_IBAT4U (0x230)
975   -#define SPR_IBAT4L (0x231)
976   -#define SPR_IBAT5U (0x232)
977   -#define SPR_IBAT5L (0x233)
978   -#define SPR_IBAT6U (0x234)
979   -#define SPR_IBAT6L (0x235)
980   -#define SPR_IBAT7U (0x236)
981   -#define SPR_IBAT7L (0x237)
982   -#define SPR_DBAT4U (0x238)
983   -#define SPR_DBAT4L (0x239)
984   -#define SPR_DBAT5U (0x23A)
985   -#define SPR_BOOKE_MCSRR0 (0x23A)
986   -#define SPR_DBAT5L (0x23B)
987   -#define SPR_BOOKE_MCSRR1 (0x23B)
988   -#define SPR_DBAT6U (0x23C)
989   -#define SPR_BOOKE_MCSR (0x23C)
990   -#define SPR_DBAT6L (0x23D)
991   -#define SPR_E500_MCAR (0x23D)
992   -#define SPR_DBAT7U (0x23E)
993   -#define SPR_BOOKE_DSRR0 (0x23E)
994   -#define SPR_DBAT7L (0x23F)
995   -#define SPR_BOOKE_DSRR1 (0x23F)
996   -#define SPR_BOOKE_SPRG8 (0x25C)
997   -#define SPR_BOOKE_SPRG9 (0x25D)
998   -#define SPR_BOOKE_MAS0 (0x270)
999   -#define SPR_BOOKE_MAS1 (0x271)
1000   -#define SPR_BOOKE_MAS2 (0x272)
1001   -#define SPR_BOOKE_MAS3 (0x273)
1002   -#define SPR_BOOKE_MAS4 (0x274)
1003   -#define SPR_BOOKE_MAS6 (0x276)
1004   -#define SPR_BOOKE_PID1 (0x279)
1005   -#define SPR_BOOKE_PID2 (0x27A)
1006   -#define SPR_BOOKE_TLB0CFG (0x2B0)
1007   -#define SPR_BOOKE_TLB1CFG (0x2B1)
1008   -#define SPR_BOOKE_TLB2CFG (0x2B2)
1009   -#define SPR_BOOKE_TLB3CFG (0x2B3)
1010   -#define SPR_BOOKE_EPR (0x2BE)
1011   -#define SPR_PERF0 (0x300)
1012   -#define SPR_PERF1 (0x301)
1013   -#define SPR_PERF2 (0x302)
1014   -#define SPR_PERF3 (0x303)
1015   -#define SPR_PERF4 (0x304)
1016   -#define SPR_PERF5 (0x305)
1017   -#define SPR_PERF6 (0x306)
1018   -#define SPR_PERF7 (0x307)
1019   -#define SPR_PERF8 (0x308)
1020   -#define SPR_PERF9 (0x309)
1021   -#define SPR_PERFA (0x30A)
1022   -#define SPR_PERFB (0x30B)
1023   -#define SPR_PERFC (0x30C)
1024   -#define SPR_PERFD (0x30D)
1025   -#define SPR_PERFE (0x30E)
1026   -#define SPR_PERFF (0x30F)
1027   -#define SPR_UPERF0 (0x310)
1028   -#define SPR_UPERF1 (0x311)
1029   -#define SPR_UPERF2 (0x312)
1030   -#define SPR_UPERF3 (0x313)
1031   -#define SPR_UPERF4 (0x314)
1032   -#define SPR_UPERF5 (0x315)
1033   -#define SPR_UPERF6 (0x316)
1034   -#define SPR_UPERF7 (0x317)
1035   -#define SPR_UPERF8 (0x318)
1036   -#define SPR_UPERF9 (0x319)
1037   -#define SPR_UPERFA (0x31A)
1038   -#define SPR_UPERFB (0x31B)
1039   -#define SPR_UPERFC (0x31C)
1040   -#define SPR_UPERFD (0x31D)
1041   -#define SPR_UPERFE (0x31E)
1042   -#define SPR_UPERFF (0x31F)
1043   -#define SPR_440_INV0 (0x370)
1044   -#define SPR_440_INV1 (0x371)
1045   -#define SPR_440_INV2 (0x372)
1046   -#define SPR_440_INV3 (0x373)
1047   -#define SPR_440_ITV0 (0x374)
1048   -#define SPR_440_ITV1 (0x375)
1049   -#define SPR_440_ITV2 (0x376)
1050   -#define SPR_440_ITV3 (0x377)
1051   -#define SPR_440_CCR1 (0x378)
1052   -#define SPR_DCRIPR (0x37B)
1053   -#define SPR_PPR (0x380)
1054   -#define SPR_440_DNV0 (0x390)
1055   -#define SPR_440_DNV1 (0x391)
1056   -#define SPR_440_DNV2 (0x392)
1057   -#define SPR_440_DNV3 (0x393)
1058   -#define SPR_440_DTV0 (0x394)
1059   -#define SPR_440_DTV1 (0x395)
1060   -#define SPR_440_DTV2 (0x396)
1061   -#define SPR_440_DTV3 (0x397)
1062   -#define SPR_440_DVLIM (0x398)
1063   -#define SPR_440_IVLIM (0x399)
1064   -#define SPR_440_RSTCFG (0x39B)
1065   -#define SPR_BOOKE_DCDBTRL (0x39C)
1066   -#define SPR_BOOKE_DCDBTRH (0x39D)
1067   -#define SPR_BOOKE_ICDBTRL (0x39E)
1068   -#define SPR_BOOKE_ICDBTRH (0x39F)
1069   -#define SPR_UMMCR2 (0x3A0)
1070   -#define SPR_UPMC5 (0x3A1)
1071   -#define SPR_UPMC6 (0x3A2)
1072   -#define SPR_UBAMR (0x3A7)
1073   -#define SPR_UMMCR0 (0x3A8)
1074   -#define SPR_UPMC1 (0x3A9)
1075   -#define SPR_UPMC2 (0x3AA)
1076   -#define SPR_USIAR (0x3AB)
1077   -#define SPR_UMMCR1 (0x3AC)
1078   -#define SPR_UPMC3 (0x3AD)
1079   -#define SPR_UPMC4 (0x3AE)
1080   -#define SPR_USDA (0x3AF)
1081   -#define SPR_40x_ZPR (0x3B0)
1082   -#define SPR_BOOKE_MAS7 (0x3B0)
1083   -#define SPR_620_PMR0 (0x3B0)
1084   -#define SPR_MMCR2 (0x3B0)
1085   -#define SPR_PMC5 (0x3B1)
1086   -#define SPR_40x_PID (0x3B1)
1087   -#define SPR_620_PMR1 (0x3B1)
1088   -#define SPR_PMC6 (0x3B2)
1089   -#define SPR_440_MMUCR (0x3B2)
1090   -#define SPR_620_PMR2 (0x3B2)
1091   -#define SPR_4xx_CCR0 (0x3B3)
1092   -#define SPR_BOOKE_EPLC (0x3B3)
1093   -#define SPR_620_PMR3 (0x3B3)
1094   -#define SPR_405_IAC3 (0x3B4)
1095   -#define SPR_BOOKE_EPSC (0x3B4)
1096   -#define SPR_620_PMR4 (0x3B4)
1097   -#define SPR_405_IAC4 (0x3B5)
1098   -#define SPR_620_PMR5 (0x3B5)
1099   -#define SPR_405_DVC1 (0x3B6)
1100   -#define SPR_620_PMR6 (0x3B6)
1101   -#define SPR_405_DVC2 (0x3B7)
1102   -#define SPR_620_PMR7 (0x3B7)
1103   -#define SPR_BAMR (0x3B7)
1104   -#define SPR_MMCR0 (0x3B8)
1105   -#define SPR_620_PMR8 (0x3B8)
1106   -#define SPR_PMC1 (0x3B9)
1107   -#define SPR_40x_SGR (0x3B9)
1108   -#define SPR_620_PMR9 (0x3B9)
1109   -#define SPR_PMC2 (0x3BA)
1110   -#define SPR_40x_DCWR (0x3BA)
1111   -#define SPR_620_PMRA (0x3BA)
1112   -#define SPR_SIAR (0x3BB)
1113   -#define SPR_405_SLER (0x3BB)
1114   -#define SPR_620_PMRB (0x3BB)
1115   -#define SPR_MMCR1 (0x3BC)
1116   -#define SPR_405_SU0R (0x3BC)
1117   -#define SPR_620_PMRC (0x3BC)
1118   -#define SPR_401_SKR (0x3BC)
1119   -#define SPR_PMC3 (0x3BD)
1120   -#define SPR_405_DBCR1 (0x3BD)
1121   -#define SPR_620_PMRD (0x3BD)
1122   -#define SPR_PMC4 (0x3BE)
1123   -#define SPR_620_PMRE (0x3BE)
1124   -#define SPR_SDA (0x3BF)
1125   -#define SPR_620_PMRF (0x3BF)
1126   -#define SPR_403_VTBL (0x3CC)
1127   -#define SPR_403_VTBU (0x3CD)
1128   -#define SPR_DMISS (0x3D0)
1129   -#define SPR_DCMP (0x3D1)
1130   -#define SPR_HASH1 (0x3D2)
1131   -#define SPR_HASH2 (0x3D3)
1132   -#define SPR_BOOKE_ICDBDR (0x3D3)
1133   -#define SPR_TLBMISS (0x3D4)
1134   -#define SPR_IMISS (0x3D4)
1135   -#define SPR_40x_ESR (0x3D4)
1136   -#define SPR_PTEHI (0x3D5)
1137   -#define SPR_ICMP (0x3D5)
1138   -#define SPR_40x_DEAR (0x3D5)
1139   -#define SPR_PTELO (0x3D6)
1140   -#define SPR_RPA (0x3D6)
1141   -#define SPR_40x_EVPR (0x3D6)
1142   -#define SPR_L3PM (0x3D7)
1143   -#define SPR_403_CDBCR (0x3D7)
1144   -#define SPR_L3OHCR (0x3D8)
1145   -#define SPR_TCR (0x3D8)
1146   -#define SPR_40x_TSR (0x3D8)
1147   -#define SPR_IBR (0x3DA)
1148   -#define SPR_40x_TCR (0x3DA)
1149   -#define SPR_ESASRR (0x3DB)
1150   -#define SPR_40x_PIT (0x3DB)
1151   -#define SPR_403_TBL (0x3DC)
1152   -#define SPR_403_TBU (0x3DD)
1153   -#define SPR_SEBR (0x3DE)
1154   -#define SPR_40x_SRR2 (0x3DE)
1155   -#define SPR_SER (0x3DF)
1156   -#define SPR_40x_SRR3 (0x3DF)
1157   -#define SPR_L3ITCR0 (0x3E8)
1158   -#define SPR_L3ITCR1 (0x3E9)
1159   -#define SPR_L3ITCR2 (0x3EA)
1160   -#define SPR_L3ITCR3 (0x3EB)
1161   -#define SPR_HID0 (0x3F0)
1162   -#define SPR_40x_DBSR (0x3F0)
1163   -#define SPR_HID1 (0x3F1)
1164   -#define SPR_IABR (0x3F2)
1165   -#define SPR_40x_DBCR0 (0x3F2)
1166   -#define SPR_601_HID2 (0x3F2)
1167   -#define SPR_E500_L1CSR0 (0x3F2)
1168   -#define SPR_ICTRL (0x3F3)
1169   -#define SPR_HID2 (0x3F3)
1170   -#define SPR_E500_L1CSR1 (0x3F3)
1171   -#define SPR_440_DBDR (0x3F3)
1172   -#define SPR_LDSTDB (0x3F4)
1173   -#define SPR_40x_IAC1 (0x3F4)
1174   -#define SPR_MMUCSR0 (0x3F4)
1175   -#define SPR_DABR (0x3F5)
  825 +#define SPR_MQ (0x000)
  826 +#define SPR_XER (0x001)
  827 +#define SPR_601_VRTCU (0x004)
  828 +#define SPR_601_VRTCL (0x005)
  829 +#define SPR_601_UDECR (0x006)
  830 +#define SPR_LR (0x008)
  831 +#define SPR_CTR (0x009)
  832 +#define SPR_DSISR (0x012)
  833 +#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
  834 +#define SPR_601_RTCU (0x014)
  835 +#define SPR_601_RTCL (0x015)
  836 +#define SPR_DECR (0x016)
  837 +#define SPR_SDR1 (0x019)
  838 +#define SPR_SRR0 (0x01A)
  839 +#define SPR_SRR1 (0x01B)
  840 +#define SPR_AMR (0x01D)
  841 +#define SPR_BOOKE_PID (0x030)
  842 +#define SPR_BOOKE_DECAR (0x036)
  843 +#define SPR_BOOKE_CSRR0 (0x03A)
  844 +#define SPR_BOOKE_CSRR1 (0x03B)
  845 +#define SPR_BOOKE_DEAR (0x03D)
  846 +#define SPR_BOOKE_ESR (0x03E)
  847 +#define SPR_BOOKE_IVPR (0x03F)
  848 +#define SPR_MPC_EIE (0x050)
  849 +#define SPR_MPC_EID (0x051)
  850 +#define SPR_MPC_NRI (0x052)
  851 +#define SPR_CTRL (0x088)
  852 +#define SPR_MPC_CMPA (0x090)
  853 +#define SPR_MPC_CMPB (0x091)
  854 +#define SPR_MPC_CMPC (0x092)
  855 +#define SPR_MPC_CMPD (0x093)
  856 +#define SPR_MPC_ECR (0x094)
  857 +#define SPR_MPC_DER (0x095)
  858 +#define SPR_MPC_COUNTA (0x096)
  859 +#define SPR_MPC_COUNTB (0x097)
  860 +#define SPR_UCTRL (0x098)
  861 +#define SPR_MPC_CMPE (0x098)
  862 +#define SPR_MPC_CMPF (0x099)
  863 +#define SPR_MPC_CMPG (0x09A)
  864 +#define SPR_MPC_CMPH (0x09B)
  865 +#define SPR_MPC_LCTRL1 (0x09C)
  866 +#define SPR_MPC_LCTRL2 (0x09D)
  867 +#define SPR_MPC_ICTRL (0x09E)
  868 +#define SPR_MPC_BAR (0x09F)
  869 +#define SPR_VRSAVE (0x100)
  870 +#define SPR_USPRG0 (0x100)
  871 +#define SPR_USPRG1 (0x101)
  872 +#define SPR_USPRG2 (0x102)
  873 +#define SPR_USPRG3 (0x103)
  874 +#define SPR_USPRG4 (0x104)
  875 +#define SPR_USPRG5 (0x105)
  876 +#define SPR_USPRG6 (0x106)
  877 +#define SPR_USPRG7 (0x107)
  878 +#define SPR_VTBL (0x10C)
  879 +#define SPR_VTBU (0x10D)
  880 +#define SPR_SPRG0 (0x110)
  881 +#define SPR_SPRG1 (0x111)
  882 +#define SPR_SPRG2 (0x112)
  883 +#define SPR_SPRG3 (0x113)
  884 +#define SPR_SPRG4 (0x114)
  885 +#define SPR_SCOMC (0x114)
  886 +#define SPR_SPRG5 (0x115)
  887 +#define SPR_SCOMD (0x115)
  888 +#define SPR_SPRG6 (0x116)
  889 +#define SPR_SPRG7 (0x117)
  890 +#define SPR_ASR (0x118)
  891 +#define SPR_EAR (0x11A)
  892 +#define SPR_TBL (0x11C)
  893 +#define SPR_TBU (0x11D)
  894 +#define SPR_TBU40 (0x11E)
  895 +#define SPR_SVR (0x11E)
  896 +#define SPR_BOOKE_PIR (0x11E)
  897 +#define SPR_PVR (0x11F)
  898 +#define SPR_HSPRG0 (0x130)
  899 +#define SPR_BOOKE_DBSR (0x130)
  900 +#define SPR_HSPRG1 (0x131)
  901 +#define SPR_HDSISR (0x132)
  902 +#define SPR_HDAR (0x133)
  903 +#define SPR_BOOKE_DBCR0 (0x134)
  904 +#define SPR_IBCR (0x135)
  905 +#define SPR_PURR (0x135)
  906 +#define SPR_BOOKE_DBCR1 (0x135)
  907 +#define SPR_DBCR (0x136)
  908 +#define SPR_HDEC (0x136)
  909 +#define SPR_BOOKE_DBCR2 (0x136)
  910 +#define SPR_HIOR (0x137)
  911 +#define SPR_MBAR (0x137)
  912 +#define SPR_RMOR (0x138)
  913 +#define SPR_BOOKE_IAC1 (0x138)
  914 +#define SPR_HRMOR (0x139)
  915 +#define SPR_BOOKE_IAC2 (0x139)
  916 +#define SPR_HSRR0 (0x13A)
  917 +#define SPR_BOOKE_IAC3 (0x13A)
  918 +#define SPR_HSRR1 (0x13B)
  919 +#define SPR_BOOKE_IAC4 (0x13B)
  920 +#define SPR_LPCR (0x13C)
  921 +#define SPR_BOOKE_DAC1 (0x13C)
  922 +#define SPR_LPIDR (0x13D)
  923 +#define SPR_DABR2 (0x13D)
  924 +#define SPR_BOOKE_DAC2 (0x13D)
  925 +#define SPR_BOOKE_DVC1 (0x13E)
  926 +#define SPR_BOOKE_DVC2 (0x13F)
  927 +#define SPR_BOOKE_TSR (0x150)
  928 +#define SPR_BOOKE_TCR (0x154)
  929 +#define SPR_BOOKE_IVOR0 (0x190)
  930 +#define SPR_BOOKE_IVOR1 (0x191)
  931 +#define SPR_BOOKE_IVOR2 (0x192)
  932 +#define SPR_BOOKE_IVOR3 (0x193)
  933 +#define SPR_BOOKE_IVOR4 (0x194)
  934 +#define SPR_BOOKE_IVOR5 (0x195)
  935 +#define SPR_BOOKE_IVOR6 (0x196)
  936 +#define SPR_BOOKE_IVOR7 (0x197)
  937 +#define SPR_BOOKE_IVOR8 (0x198)
  938 +#define SPR_BOOKE_IVOR9 (0x199)
  939 +#define SPR_BOOKE_IVOR10 (0x19A)
  940 +#define SPR_BOOKE_IVOR11 (0x19B)
  941 +#define SPR_BOOKE_IVOR12 (0x19C)
  942 +#define SPR_BOOKE_IVOR13 (0x19D)
  943 +#define SPR_BOOKE_IVOR14 (0x19E)
  944 +#define SPR_BOOKE_IVOR15 (0x19F)
  945 +#define SPR_BOOKE_SPEFSCR (0x200)
  946 +#define SPR_Exxx_BBEAR (0x201)
  947 +#define SPR_Exxx_BBTAR (0x202)
  948 +#define SPR_Exxx_L1CFG0 (0x203)
  949 +#define SPR_Exxx_NPIDR (0x205)
  950 +#define SPR_ATBL (0x20E)
  951 +#define SPR_ATBU (0x20F)
  952 +#define SPR_IBAT0U (0x210)
  953 +#define SPR_BOOKE_IVOR32 (0x210)
  954 +#define SPR_RCPU_MI_GRA (0x210)
  955 +#define SPR_IBAT0L (0x211)
  956 +#define SPR_BOOKE_IVOR33 (0x211)
  957 +#define SPR_IBAT1U (0x212)
  958 +#define SPR_BOOKE_IVOR34 (0x212)
  959 +#define SPR_IBAT1L (0x213)
  960 +#define SPR_BOOKE_IVOR35 (0x213)
  961 +#define SPR_IBAT2U (0x214)
  962 +#define SPR_BOOKE_IVOR36 (0x214)
  963 +#define SPR_IBAT2L (0x215)
  964 +#define SPR_BOOKE_IVOR37 (0x215)
  965 +#define SPR_IBAT3U (0x216)
  966 +#define SPR_IBAT3L (0x217)
  967 +#define SPR_DBAT0U (0x218)
  968 +#define SPR_RCPU_L2U_GRA (0x218)
  969 +#define SPR_DBAT0L (0x219)
  970 +#define SPR_DBAT1U (0x21A)
  971 +#define SPR_DBAT1L (0x21B)
  972 +#define SPR_DBAT2U (0x21C)
  973 +#define SPR_DBAT2L (0x21D)
  974 +#define SPR_DBAT3U (0x21E)
  975 +#define SPR_DBAT3L (0x21F)
  976 +#define SPR_IBAT4U (0x230)
  977 +#define SPR_RPCU_BBCMCR (0x230)
  978 +#define SPR_MPC_IC_CST (0x230)
  979 +#define SPR_Exxx_CTXCR (0x230)
  980 +#define SPR_IBAT4L (0x231)
  981 +#define SPR_MPC_IC_ADR (0x231)
  982 +#define SPR_Exxx_DBCR3 (0x231)
  983 +#define SPR_IBAT5U (0x232)
  984 +#define SPR_MPC_IC_DAT (0x232)
  985 +#define SPR_Exxx_DBCNT (0x232)
  986 +#define SPR_IBAT5L (0x233)
  987 +#define SPR_IBAT6U (0x234)
  988 +#define SPR_IBAT6L (0x235)
  989 +#define SPR_IBAT7U (0x236)
  990 +#define SPR_IBAT7L (0x237)
  991 +#define SPR_DBAT4U (0x238)
  992 +#define SPR_RCPU_L2U_MCR (0x238)
  993 +#define SPR_MPC_DC_CST (0x238)
  994 +#define SPR_Exxx_ALTCTXCR (0x238)
  995 +#define SPR_DBAT4L (0x239)
  996 +#define SPR_MPC_DC_ADR (0x239)
  997 +#define SPR_DBAT5U (0x23A)
  998 +#define SPR_BOOKE_MCSRR0 (0x23A)
  999 +#define SPR_MPC_DC_DAT (0x23A)
  1000 +#define SPR_DBAT5L (0x23B)
  1001 +#define SPR_BOOKE_MCSRR1 (0x23B)
  1002 +#define SPR_DBAT6U (0x23C)
  1003 +#define SPR_BOOKE_MCSR (0x23C)
  1004 +#define SPR_DBAT6L (0x23D)
  1005 +#define SPR_Exxx_MCAR (0x23D)
  1006 +#define SPR_DBAT7U (0x23E)
  1007 +#define SPR_BOOKE_DSRR0 (0x23E)
  1008 +#define SPR_DBAT7L (0x23F)
  1009 +#define SPR_BOOKE_DSRR1 (0x23F)
  1010 +#define SPR_BOOKE_SPRG8 (0x25C)
  1011 +#define SPR_BOOKE_SPRG9 (0x25D)
  1012 +#define SPR_BOOKE_MAS0 (0x270)
  1013 +#define SPR_BOOKE_MAS1 (0x271)
  1014 +#define SPR_BOOKE_MAS2 (0x272)
  1015 +#define SPR_BOOKE_MAS3 (0x273)
  1016 +#define SPR_BOOKE_MAS4 (0x274)
  1017 +#define SPR_BOOKE_MAS5 (0x275)
  1018 +#define SPR_BOOKE_MAS6 (0x276)
  1019 +#define SPR_BOOKE_PID1 (0x279)
  1020 +#define SPR_BOOKE_PID2 (0x27A)
  1021 +#define SPR_MPC_DPDR (0x280)
  1022 +#define SPR_MPC_IMMR (0x288)
  1023 +#define SPR_BOOKE_TLB0CFG (0x2B0)
  1024 +#define SPR_BOOKE_TLB1CFG (0x2B1)
  1025 +#define SPR_BOOKE_TLB2CFG (0x2B2)
  1026 +#define SPR_BOOKE_TLB3CFG (0x2B3)
  1027 +#define SPR_BOOKE_EPR (0x2BE)
  1028 +#define SPR_PERF0 (0x300)
  1029 +#define SPR_RCPU_MI_RBA0 (0x300)
  1030 +#define SPR_MPC_MI_CTR (0x300)
  1031 +#define SPR_PERF1 (0x301)
  1032 +#define SPR_RCPU_MI_RBA1 (0x301)
  1033 +#define SPR_PERF2 (0x302)
  1034 +#define SPR_RCPU_MI_RBA2 (0x302)
  1035 +#define SPR_MPC_MI_AP (0x302)
  1036 +#define SPR_PERF3 (0x303)
  1037 +#define SPR_RCPU_MI_RBA3 (0x303)
  1038 +#define SPR_MPC_MI_EPN (0x303)
  1039 +#define SPR_PERF4 (0x304)
  1040 +#define SPR_PERF5 (0x305)
  1041 +#define SPR_MPC_MI_TWC (0x305)
  1042 +#define SPR_PERF6 (0x306)
  1043 +#define SPR_MPC_MI_RPN (0x306)
  1044 +#define SPR_PERF7 (0x307)
  1045 +#define SPR_PERF8 (0x308)
  1046 +#define SPR_RCPU_L2U_RBA0 (0x308)
  1047 +#define SPR_MPC_MD_CTR (0x308)
  1048 +#define SPR_PERF9 (0x309)
  1049 +#define SPR_RCPU_L2U_RBA1 (0x309)
  1050 +#define SPR_MPC_MD_CASID (0x309)
  1051 +#define SPR_PERFA (0x30A)
  1052 +#define SPR_RCPU_L2U_RBA2 (0x30A)
  1053 +#define SPR_MPC_MD_AP (0x30A)
  1054 +#define SPR_PERFB (0x30B)
  1055 +#define SPR_RCPU_L2U_RBA3 (0x30B)
  1056 +#define SPR_MPC_MD_EPN (0x30B)
  1057 +#define SPR_PERFC (0x30C)
  1058 +#define SPR_MPC_MD_TWB (0x30C)
  1059 +#define SPR_PERFD (0x30D)
  1060 +#define SPR_MPC_MD_TWC (0x30D)
  1061 +#define SPR_PERFE (0x30E)
  1062 +#define SPR_MPC_MD_RPN (0x30E)
  1063 +#define SPR_PERFF (0x30F)
  1064 +#define SPR_MPC_MD_TW (0x30F)
  1065 +#define SPR_UPERF0 (0x310)
  1066 +#define SPR_UPERF1 (0x311)
  1067 +#define SPR_UPERF2 (0x312)
  1068 +#define SPR_UPERF3 (0x313)
  1069 +#define SPR_UPERF4 (0x314)
  1070 +#define SPR_UPERF5 (0x315)
  1071 +#define SPR_UPERF6 (0x316)
  1072 +#define SPR_UPERF7 (0x317)
  1073 +#define SPR_UPERF8 (0x318)
  1074 +#define SPR_UPERF9 (0x319)
  1075 +#define SPR_UPERFA (0x31A)
  1076 +#define SPR_UPERFB (0x31B)
  1077 +#define SPR_UPERFC (0x31C)
  1078 +#define SPR_UPERFD (0x31D)
  1079 +#define SPR_UPERFE (0x31E)
  1080 +#define SPR_UPERFF (0x31F)
  1081 +#define SPR_RCPU_MI_RA0 (0x320)
  1082 +#define SPR_MPC_MI_DBCAM (0x320)
  1083 +#define SPR_RCPU_MI_RA1 (0x321)
  1084 +#define SPR_MPC_MI_DBRAM0 (0x321)
  1085 +#define SPR_RCPU_MI_RA2 (0x322)
  1086 +#define SPR_MPC_MI_DBRAM1 (0x322)
  1087 +#define SPR_RCPU_MI_RA3 (0x323)
  1088 +#define SPR_RCPU_L2U_RA0 (0x328)
  1089 +#define SPR_MPC_MD_DBCAM (0x328)
  1090 +#define SPR_RCPU_L2U_RA1 (0x329)
  1091 +#define SPR_MPC_MD_DBRAM0 (0x329)
  1092 +#define SPR_RCPU_L2U_RA2 (0x32A)
  1093 +#define SPR_MPC_MD_DBRAM1 (0x32A)
  1094 +#define SPR_RCPU_L2U_RA3 (0x32B)
  1095 +#define SPR_440_INV0 (0x370)
  1096 +#define SPR_440_INV1 (0x371)
  1097 +#define SPR_440_INV2 (0x372)
  1098 +#define SPR_440_INV3 (0x373)
  1099 +#define SPR_440_ITV0 (0x374)
  1100 +#define SPR_440_ITV1 (0x375)
  1101 +#define SPR_440_ITV2 (0x376)
  1102 +#define SPR_440_ITV3 (0x377)
  1103 +#define SPR_440_CCR1 (0x378)
  1104 +#define SPR_DCRIPR (0x37B)
  1105 +#define SPR_PPR (0x380)
  1106 +#define SPR_440_DNV0 (0x390)
  1107 +#define SPR_440_DNV1 (0x391)
  1108 +#define SPR_440_DNV2 (0x392)
  1109 +#define SPR_440_DNV3 (0x393)
  1110 +#define SPR_440_DTV0 (0x394)
  1111 +#define SPR_440_DTV1 (0x395)
  1112 +#define SPR_440_DTV2 (0x396)
  1113 +#define SPR_440_DTV3 (0x397)
  1114 +#define SPR_440_DVLIM (0x398)
  1115 +#define SPR_440_IVLIM (0x399)
  1116 +#define SPR_440_RSTCFG (0x39B)
  1117 +#define SPR_BOOKE_DCDBTRL (0x39C)
  1118 +#define SPR_BOOKE_DCDBTRH (0x39D)
  1119 +#define SPR_BOOKE_ICDBTRL (0x39E)
  1120 +#define SPR_BOOKE_ICDBTRH (0x39F)
  1121 +#define SPR_UMMCR2 (0x3A0)
  1122 +#define SPR_UPMC5 (0x3A1)
  1123 +#define SPR_UPMC6 (0x3A2)
  1124 +#define SPR_UBAMR (0x3A7)
  1125 +#define SPR_UMMCR0 (0x3A8)
  1126 +#define SPR_UPMC1 (0x3A9)
  1127 +#define SPR_UPMC2 (0x3AA)
  1128 +#define SPR_USIAR (0x3AB)
  1129 +#define SPR_UMMCR1 (0x3AC)
  1130 +#define SPR_UPMC3 (0x3AD)
  1131 +#define SPR_UPMC4 (0x3AE)
  1132 +#define SPR_USDA (0x3AF)
  1133 +#define SPR_40x_ZPR (0x3B0)
  1134 +#define SPR_BOOKE_MAS7 (0x3B0)
  1135 +#define SPR_620_PMR0 (0x3B0)
  1136 +#define SPR_MMCR2 (0x3B0)
  1137 +#define SPR_PMC5 (0x3B1)
  1138 +#define SPR_40x_PID (0x3B1)
  1139 +#define SPR_620_PMR1 (0x3B1)
  1140 +#define SPR_PMC6 (0x3B2)
  1141 +#define SPR_440_MMUCR (0x3B2)
  1142 +#define SPR_620_PMR2 (0x3B2)
  1143 +#define SPR_4xx_CCR0 (0x3B3)
  1144 +#define SPR_BOOKE_EPLC (0x3B3)
  1145 +#define SPR_620_PMR3 (0x3B3)
  1146 +#define SPR_405_IAC3 (0x3B4)
  1147 +#define SPR_BOOKE_EPSC (0x3B4)
  1148 +#define SPR_620_PMR4 (0x3B4)
  1149 +#define SPR_405_IAC4 (0x3B5)
  1150 +#define SPR_620_PMR5 (0x3B5)
  1151 +#define SPR_405_DVC1 (0x3B6)
  1152 +#define SPR_620_PMR6 (0x3B6)
  1153 +#define SPR_405_DVC2 (0x3B7)
  1154 +#define SPR_620_PMR7 (0x3B7)
  1155 +#define SPR_BAMR (0x3B7)
  1156 +#define SPR_MMCR0 (0x3B8)
  1157 +#define SPR_620_PMR8 (0x3B8)
  1158 +#define SPR_PMC1 (0x3B9)
  1159 +#define SPR_40x_SGR (0x3B9)
  1160 +#define SPR_620_PMR9 (0x3B9)
  1161 +#define SPR_PMC2 (0x3BA)
  1162 +#define SPR_40x_DCWR (0x3BA)
  1163 +#define SPR_620_PMRA (0x3BA)
  1164 +#define SPR_SIAR (0x3BB)
  1165 +#define SPR_405_SLER (0x3BB)
  1166 +#define SPR_620_PMRB (0x3BB)
  1167 +#define SPR_MMCR1 (0x3BC)
  1168 +#define SPR_405_SU0R (0x3BC)
  1169 +#define SPR_620_PMRC (0x3BC)
  1170 +#define SPR_401_SKR (0x3BC)
  1171 +#define SPR_PMC3 (0x3BD)
  1172 +#define SPR_405_DBCR1 (0x3BD)
  1173 +#define SPR_620_PMRD (0x3BD)
  1174 +#define SPR_PMC4 (0x3BE)
  1175 +#define SPR_620_PMRE (0x3BE)
  1176 +#define SPR_SDA (0x3BF)
  1177 +#define SPR_620_PMRF (0x3BF)
  1178 +#define SPR_403_VTBL (0x3CC)
  1179 +#define SPR_403_VTBU (0x3CD)
  1180 +#define SPR_DMISS (0x3D0)
  1181 +#define SPR_DCMP (0x3D1)
  1182 +#define SPR_HASH1 (0x3D2)
  1183 +#define SPR_HASH2 (0x3D3)
  1184 +#define SPR_BOOKE_ICDBDR (0x3D3)
  1185 +#define SPR_TLBMISS (0x3D4)
  1186 +#define SPR_IMISS (0x3D4)
  1187 +#define SPR_40x_ESR (0x3D4)
  1188 +#define SPR_PTEHI (0x3D5)
  1189 +#define SPR_ICMP (0x3D5)
  1190 +#define SPR_40x_DEAR (0x3D5)
  1191 +#define SPR_PTELO (0x3D6)
  1192 +#define SPR_RPA (0x3D6)
  1193 +#define SPR_40x_EVPR (0x3D6)
  1194 +#define SPR_L3PM (0x3D7)
  1195 +#define SPR_403_CDBCR (0x3D7)
  1196 +#define SPR_L3OHCR (0x3D8)
  1197 +#define SPR_TCR (0x3D8)
  1198 +#define SPR_40x_TSR (0x3D8)
  1199 +#define SPR_IBR (0x3DA)
  1200 +#define SPR_40x_TCR (0x3DA)
  1201 +#define SPR_ESASRR (0x3DB)
  1202 +#define SPR_40x_PIT (0x3DB)
  1203 +#define SPR_403_TBL (0x3DC)
  1204 +#define SPR_403_TBU (0x3DD)
  1205 +#define SPR_SEBR (0x3DE)
  1206 +#define SPR_40x_SRR2 (0x3DE)
  1207 +#define SPR_SER (0x3DF)
  1208 +#define SPR_40x_SRR3 (0x3DF)
  1209 +#define SPR_L3ITCR0 (0x3E8)
  1210 +#define SPR_L3ITCR1 (0x3E9)
  1211 +#define SPR_L3ITCR2 (0x3EA)
  1212 +#define SPR_L3ITCR3 (0x3EB)
  1213 +#define SPR_HID0 (0x3F0)
  1214 +#define SPR_40x_DBSR (0x3F0)
  1215 +#define SPR_HID1 (0x3F1)
  1216 +#define SPR_IABR (0x3F2)
  1217 +#define SPR_40x_DBCR0 (0x3F2)
  1218 +#define SPR_601_HID2 (0x3F2)
  1219 +#define SPR_Exxx_L1CSR0 (0x3F2)
  1220 +#define SPR_ICTRL (0x3F3)
  1221 +#define SPR_HID2 (0x3F3)
  1222 +#define SPR_Exxx_L1CSR1 (0x3F3)
  1223 +#define SPR_440_DBDR (0x3F3)
  1224 +#define SPR_LDSTDB (0x3F4)
  1225 +#define SPR_40x_IAC1 (0x3F4)
  1226 +#define SPR_MMUCSR0 (0x3F4)
  1227 +#define SPR_DABR (0x3F5)
1176 1228 #define DABR_MASK (~(target_ulong)0x7)
1177   -#define SPR_E500_BUCSR (0x3F5)
1178   -#define SPR_40x_IAC2 (0x3F5)
1179   -#define SPR_601_HID5 (0x3F5)
1180   -#define SPR_40x_DAC1 (0x3F6)
1181   -#define SPR_MSSCR0 (0x3F6)
1182   -#define SPR_970_HID5 (0x3F6)
1183   -#define SPR_MSSSR0 (0x3F7)
1184   -#define SPR_DABRX (0x3F7)
1185   -#define SPR_40x_DAC2 (0x3F7)
1186   -#define SPR_MMUCFG (0x3F7)
1187   -#define SPR_LDSTCR (0x3F8)
1188   -#define SPR_L2PMCR (0x3F8)
1189   -#define SPR_750_HID2 (0x3F8)
1190   -#define SPR_620_HID8 (0x3F8)
1191   -#define SPR_L2CR (0x3F9)
1192   -#define SPR_620_HID9 (0x3F9)
1193   -#define SPR_L3CR (0x3FA)
1194   -#define SPR_IABR2 (0x3FA)
1195   -#define SPR_40x_DCCR (0x3FA)
1196   -#define SPR_ICTC (0x3FB)
1197   -#define SPR_40x_ICCR (0x3FB)
1198   -#define SPR_THRM1 (0x3FC)
1199   -#define SPR_403_PBL1 (0x3FC)
1200   -#define SPR_SP (0x3FD)
1201   -#define SPR_THRM2 (0x3FD)
1202   -#define SPR_403_PBU1 (0x3FD)
1203   -#define SPR_604_HID13 (0x3FD)
1204   -#define SPR_LT (0x3FE)
1205   -#define SPR_THRM3 (0x3FE)
1206   -#define SPR_FPECR (0x3FE)
1207   -#define SPR_403_PBL2 (0x3FE)
1208   -#define SPR_PIR (0x3FF)
1209   -#define SPR_403_PBU2 (0x3FF)
1210   -#define SPR_601_HID15 (0x3FF)
1211   -#define SPR_604_HID15 (0x3FF)
1212   -#define SPR_E500_SVR (0x3FF)
  1229 +#define SPR_Exxx_BUCSR (0x3F5)
  1230 +#define SPR_40x_IAC2 (0x3F5)
  1231 +#define SPR_601_HID5 (0x3F5)
  1232 +#define SPR_40x_DAC1 (0x3F6)
  1233 +#define SPR_MSSCR0 (0x3F6)
  1234 +#define SPR_970_HID5 (0x3F6)
  1235 +#define SPR_MSSSR0 (0x3F7)
  1236 +#define SPR_DABRX (0x3F7)
  1237 +#define SPR_40x_DAC2 (0x3F7)
  1238 +#define SPR_MMUCFG (0x3F7)
  1239 +#define SPR_LDSTCR (0x3F8)
  1240 +#define SPR_L2PMCR (0x3F8)
  1241 +#define SPR_750_HID2 (0x3F8)
  1242 +#define SPR_620_HID8 (0x3F8)
  1243 +#define SPR_Exxx_L1FINV0 (0x3F8)
  1244 +#define SPR_L2CR (0x3F9)
  1245 +#define SPR_620_HID9 (0x3F9)
  1246 +#define SPR_L3CR (0x3FA)
  1247 +#define SPR_IABR2 (0x3FA)
  1248 +#define SPR_40x_DCCR (0x3FA)
  1249 +#define SPR_ICTC (0x3FB)
  1250 +#define SPR_40x_ICCR (0x3FB)
  1251 +#define SPR_THRM1 (0x3FC)
  1252 +#define SPR_403_PBL1 (0x3FC)
  1253 +#define SPR_SP (0x3FD)
  1254 +#define SPR_THRM2 (0x3FD)
  1255 +#define SPR_403_PBU1 (0x3FD)
  1256 +#define SPR_604_HID13 (0x3FD)
  1257 +#define SPR_LT (0x3FE)
  1258 +#define SPR_THRM3 (0x3FE)
  1259 +#define SPR_RCPU_FPECR (0x3FE)
  1260 +#define SPR_403_PBL2 (0x3FE)
  1261 +#define SPR_PIR (0x3FF)
  1262 +#define SPR_403_PBU2 (0x3FF)
  1263 +#define SPR_601_HID15 (0x3FF)
  1264 +#define SPR_604_HID15 (0x3FF)
  1265 +#define SPR_E500_SVR (0x3FF)
1213 1266  
1214 1267 /*****************************************************************************/
1215 1268 /* Memory access type :
... ...
target-ppc/translate_init.c
  View file @80d11f4
Changes suppressed. Click to show.
... ... @@ -28,11 +28,15 @@
28 28  
29 29 //#define PPC_DUMP_CPU
30 30 //#define PPC_DEBUG_SPR
31   -//#define PPC_DEBUG_IRQ
  31 +//#define PPC_DUMP_SPR_ACCESSES
  32 +#if defined(CONFIG_USER_ONLY)
  33 +#define TODO_USER_ONLY 1
  34 +#endif
32 35  
33 36 struct ppc_def_t {
34 37 const unsigned char *name;
35 38 uint32_t pvr;
  39 + uint32_t svr;
36 40 uint64_t insns_flags;
37 41 uint64_t msr_mask;
38 42 powerpc_mmu_t mmu_model;
... ... @@ -983,13 +987,6 @@ static void gen_spr_G2 (CPUPPCState *env)
983 987 SPR_NOACCESS, SPR_NOACCESS,
984 988 &spr_read_generic, &spr_write_generic,
985 989 0x00000000);
986   - /* System version register */
987   - /* SVR */
988   - /* XXX : TODO: initialize it to an appropriate value */
989   - spr_register(env, SPR_SVR, "SVR",
990   - SPR_NOACCESS, SPR_NOACCESS,
991   - &spr_read_generic, SPR_NOACCESS,
992   - 0x00000000);
993 990 /* Exception processing */
994 991 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
995 992 SPR_NOACCESS, SPR_NOACCESS,
... ... @@ -1277,14 +1274,68 @@ static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1277 1274 #endif
1278 1275 }
1279 1276  
1280   -/* PowerPC BookE SPR */
1281   -static void gen_spr_BookE (CPUPPCState *env)
  1277 +static void gen_spr_usprgh (CPUPPCState *env)
1282 1278 {
1283   - /* Processor identification */
1284   - spr_register(env, SPR_BOOKE_PIR, "PIR",
1285   - SPR_NOACCESS, SPR_NOACCESS,
1286   - &spr_read_generic, &spr_write_pir,
  1279 + spr_register(env, SPR_USPRG4, "USPRG4",
  1280 + &spr_read_ureg, SPR_NOACCESS,
  1281 + &spr_read_ureg, SPR_NOACCESS,
  1282 + 0x00000000);
  1283 + spr_register(env, SPR_USPRG5, "USPRG5",
  1284 + &spr_read_ureg, SPR_NOACCESS,
  1285 + &spr_read_ureg, SPR_NOACCESS,
  1286 + 0x00000000);
  1287 + spr_register(env, SPR_USPRG6, "USPRG6",
  1288 + &spr_read_ureg, SPR_NOACCESS,
  1289 + &spr_read_ureg, SPR_NOACCESS,
  1290 + 0x00000000);
  1291 + spr_register(env, SPR_USPRG7, "USPRG7",
  1292 + &spr_read_ureg, SPR_NOACCESS,
  1293 + &spr_read_ureg, SPR_NOACCESS,
1287 1294 0x00000000);
  1295 +}
  1296 +
  1297 +/* PowerPC BookE SPR */
  1298 +static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
  1299 +{
  1300 + const unsigned char *ivor_names[64] = {
  1301 + "IVOR0", "IVOR1", "IVOR2", "IVOR3",
  1302 + "IVOR4", "IVOR5", "IVOR6", "IVOR7",
  1303 + "IVOR8", "IVOR9", "IVOR10", "IVOR11",
  1304 + "IVOR12", "IVOR13", "IVOR14", "IVOR15",
  1305 + "IVOR16", "IVOR17", "IVOR18", "IVOR19",
  1306 + "IVOR20", "IVOR21", "IVOR22", "IVOR23",
  1307 + "IVOR24", "IVOR25", "IVOR26", "IVOR27",
  1308 + "IVOR28", "IVOR29", "IVOR30", "IVOR31",
  1309 + "IVOR32", "IVOR33", "IVOR34", "IVOR35",
  1310 + "IVOR36", "IVOR37", "IVOR38", "IVOR39",
  1311 + "IVOR40", "IVOR41", "IVOR42", "IVOR43",
  1312 + "IVOR44", "IVOR45", "IVOR46", "IVOR47",
  1313 + "IVOR48", "IVOR49", "IVOR50", "IVOR51",
  1314 + "IVOR52", "IVOR53", "IVOR54", "IVOR55",
  1315 + "IVOR56", "IVOR57", "IVOR58", "IVOR59",
  1316 + "IVOR60", "IVOR61", "IVOR62", "IVOR63",
  1317 + };
  1318 +#define SPR_BOOKE_IVORxx (-1)
  1319 + int ivor_sprn[64] = {
  1320 + SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
  1321 + SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
  1322 + SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
  1323 + SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
  1324 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1325 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1326 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1327 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1328 + SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
  1329 + SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1330 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1331 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1332 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1333 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1334 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1335 + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
  1336 + };
  1337 + int i;
  1338 +
1288 1339 /* Interrupt processing */
1289 1340 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1290 1341 SPR_NOACCESS, SPR_NOACCESS,
... ... @@ -1294,16 +1345,6 @@ static void gen_spr_BookE (CPUPPCState *env)
1294 1345 SPR_NOACCESS, SPR_NOACCESS,
1295 1346 &spr_read_generic, &spr_write_generic,
1296 1347 0x00000000);
1297   -#if 0
1298   - spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1299   - SPR_NOACCESS, SPR_NOACCESS,
1300   - &spr_read_generic, &spr_write_generic,
1301   - 0x00000000);
1302   - spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1303   - SPR_NOACCESS, SPR_NOACCESS,
1304   - &spr_read_generic, &spr_write_generic,
1305   - 0x00000000);
1306   -#endif
1307 1348 /* Debug */
1308 1349 /* XXX : not implemented */
1309 1350 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
... ... @@ -1316,16 +1357,6 @@ static void gen_spr_BookE (CPUPPCState *env)
1316 1357 &spr_read_generic, &spr_write_generic,
1317 1358 0x00000000);
1318 1359 /* XXX : not implemented */
1319   - spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1320   - SPR_NOACCESS, SPR_NOACCESS,
1321   - &spr_read_generic, &spr_write_generic,
1322   - 0x00000000);
1323   - /* XXX : not implemented */
1324   - spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1325   - SPR_NOACCESS, SPR_NOACCESS,
1326   - &spr_read_generic, &spr_write_generic,
1327   - 0x00000000);
1328   - /* XXX : not implemented */
1329 1360 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1330 1361 SPR_NOACCESS, SPR_NOACCESS,
1331 1362 &spr_read_generic, &spr_write_generic,
... ... @@ -1336,16 +1367,6 @@ static void gen_spr_BookE (CPUPPCState *env)
1336 1367 &spr_read_generic, &spr_write_generic,
1337 1368 0x00000000);
1338 1369 /* XXX : not implemented */
1339   - spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1340   - SPR_NOACCESS, SPR_NOACCESS,
1341   - &spr_read_generic, &spr_write_generic,
1342   - 0x00000000);
1343   - /* XXX : not implemented */
1344   - spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1345   - SPR_NOACCESS, SPR_NOACCESS,
1346   - &spr_read_generic, &spr_write_generic,
1347   - 0x00000000);
1348   - /* XXX : not implemented */
1349 1370 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1350 1371 SPR_NOACCESS, SPR_NOACCESS,
1351 1372 &spr_read_generic, &spr_write_generic,
... ... @@ -1378,96 +1399,18 @@ static void gen_spr_BookE (CPUPPCState *env)
1378 1399 &spr_read_generic, &spr_write_excp_prefix,
1379 1400 0x00000000);
1380 1401 /* Exception vectors */
1381   - spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1382   - SPR_NOACCESS, SPR_NOACCESS,
1383   - &spr_read_generic, &spr_write_excp_vector,
1384   - 0x00000000);
1385   - spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1386   - SPR_NOACCESS, SPR_NOACCESS,
1387   - &spr_read_generic, &spr_write_excp_vector,
1388   - 0x00000000);
1389   - spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1390   - SPR_NOACCESS, SPR_NOACCESS,
1391   - &spr_read_generic, &spr_write_excp_vector,
1392   - 0x00000000);
1393   - spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1394   - SPR_NOACCESS, SPR_NOACCESS,
1395   - &spr_read_generic, &spr_write_excp_vector,
1396   - 0x00000000);
1397   - spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1398   - SPR_NOACCESS, SPR_NOACCESS,
1399   - &spr_read_generic, &spr_write_excp_vector,
1400   - 0x00000000);
1401   - spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1402   - SPR_NOACCESS, SPR_NOACCESS,
1403   - &spr_read_generic, &spr_write_excp_vector,
1404   - 0x00000000);
1405   - spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1406   - SPR_NOACCESS, SPR_NOACCESS,
1407   - &spr_read_generic, &spr_write_excp_vector,
1408   - 0x00000000);
1409   - spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1410   - SPR_NOACCESS, SPR_NOACCESS,
1411   - &spr_read_generic, &spr_write_excp_vector,
1412   - 0x00000000);
1413   - spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1414   - SPR_NOACCESS, SPR_NOACCESS,
1415   - &spr_read_generic, &spr_write_excp_vector,
1416   - 0x00000000);
1417   - spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1418   - SPR_NOACCESS, SPR_NOACCESS,
1419   - &spr_read_generic, &spr_write_excp_vector,
1420   - 0x00000000);
1421   - spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1422   - SPR_NOACCESS, SPR_NOACCESS,
1423   - &spr_read_generic, &spr_write_excp_vector,
1424   - 0x00000000);
1425   - spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1426   - SPR_NOACCESS, SPR_NOACCESS,
1427   - &spr_read_generic, &spr_write_excp_vector,
1428   - 0x00000000);
1429   - spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1430   - SPR_NOACCESS, SPR_NOACCESS,
1431   - &spr_read_generic, &spr_write_excp_vector,
1432   - 0x00000000);
1433   - spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1434   - SPR_NOACCESS, SPR_NOACCESS,
1435   - &spr_read_generic, &spr_write_excp_vector,
1436   - 0x00000000);
1437   - spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1438   - SPR_NOACCESS, SPR_NOACCESS,
1439   - &spr_read_generic, &spr_write_excp_vector,
1440   - 0x00000000);
1441   - spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1442   - SPR_NOACCESS, SPR_NOACCESS,
1443   - &spr_read_generic, &spr_write_excp_vector,
1444   - 0x00000000);
1445   -#if 0
1446   - spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1447   - SPR_NOACCESS, SPR_NOACCESS,
1448   - &spr_read_generic, &spr_write_excp_vector,
1449   - 0x00000000);
1450   - spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1451   - SPR_NOACCESS, SPR_NOACCESS,
1452   - &spr_read_generic, &spr_write_excp_vector,
1453   - 0x00000000);
1454   - spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1455   - SPR_NOACCESS, SPR_NOACCESS,
1456   - &spr_read_generic, &spr_write_excp_vector,
1457   - 0x00000000);
1458   - spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1459   - SPR_NOACCESS, SPR_NOACCESS,
1460   - &spr_read_generic, &spr_write_excp_vector,
1461   - 0x00000000);
1462   - spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1463   - SPR_NOACCESS, SPR_NOACCESS,
1464   - &spr_read_generic, &spr_write_excp_vector,
1465   - 0x00000000);
1466   - spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1467   - SPR_NOACCESS, SPR_NOACCESS,
1468   - &spr_read_generic, &spr_write_excp_vector,
1469   - 0x00000000);
1470   -#endif
  1402 + for (i = 0; i < 64; i++) {
  1403 + if (ivor_mask & (1ULL << i)) {
  1404 + if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
  1405 + fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
  1406 + exit(1);
  1407 + }
  1408 + spr_register(env, ivor_sprn[i], ivor_names[i],
  1409 + SPR_NOACCESS, SPR_NOACCESS,
  1410 + &spr_read_generic, &spr_write_excp_vector,
  1411 + 0x00000000);
  1412 + }
  1413 + }
1471 1414 spr_register(env, SPR_BOOKE_PID, "PID",
1472 1415 SPR_NOACCESS, SPR_NOACCESS,
1473 1416 &spr_read_generic, &spr_write_generic,
... ... @@ -1498,76 +1441,43 @@ static void gen_spr_BookE (CPUPPCState *env)
1498 1441 SPR_NOACCESS, SPR_NOACCESS,
1499 1442 &spr_read_generic, &spr_write_generic,
1500 1443 0x00000000);
1501   - spr_register(env, SPR_USPRG4, "USPRG4",
1502   - &spr_read_ureg, SPR_NOACCESS,
1503   - &spr_read_ureg, SPR_NOACCESS,
1504   - 0x00000000);
1505 1444 spr_register(env, SPR_SPRG5, "SPRG5",
1506 1445 SPR_NOACCESS, SPR_NOACCESS,
1507 1446 &spr_read_generic, &spr_write_generic,
1508 1447 0x00000000);
1509   - spr_register(env, SPR_USPRG5, "USPRG5",
1510   - &spr_read_ureg, SPR_NOACCESS,
1511   - &spr_read_ureg, SPR_NOACCESS,
1512   - 0x00000000);
1513 1448 spr_register(env, SPR_SPRG6, "SPRG6",
1514 1449 SPR_NOACCESS, SPR_NOACCESS,
1515 1450 &spr_read_generic, &spr_write_generic,
1516 1451 0x00000000);
1517   - spr_register(env, SPR_USPRG6, "USPRG6",
1518   - &spr_read_ureg, SPR_NOACCESS,
1519   - &spr_read_ureg, SPR_NOACCESS,
1520   - 0x00000000);
1521 1452 spr_register(env, SPR_SPRG7, "SPRG7",
1522 1453 SPR_NOACCESS, SPR_NOACCESS,
1523 1454 &spr_read_generic, &spr_write_generic,
1524 1455 0x00000000);
1525   - spr_register(env, SPR_USPRG7, "USPRG7",
1526   - &spr_read_ureg, SPR_NOACCESS,
1527   - &spr_read_ureg, SPR_NOACCESS,
1528   - 0x00000000);
1529 1456 }
1530 1457  
1531 1458 /* FSL storage control registers */
1532   -static void gen_spr_BookE_FSL (CPUPPCState *env)
  1459 +static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1533 1460 {
1534 1461 #if !defined(CONFIG_USER_ONLY)
  1462 + const unsigned char *mas_names[8] = {
  1463 + "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
  1464 + };
  1465 + int mas_sprn[8] = {
  1466 + SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
  1467 + SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
  1468 + };
  1469 + int i;
  1470 +
1535 1471 /* TLB assist registers */
1536 1472 /* XXX : not implemented */
1537   - spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1538   - SPR_NOACCESS, SPR_NOACCESS,
1539   - &spr_read_generic, &spr_write_generic,
1540   - 0x00000000);
1541   - /* XXX : not implemented */
1542   - spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1543   - SPR_NOACCESS, SPR_NOACCESS,
1544   - &spr_read_generic, &spr_write_generic,
1545   - 0x00000000);
1546   - /* XXX : not implemented */
1547   - spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1548   - SPR_NOACCESS, SPR_NOACCESS,
1549   - &spr_read_generic, &spr_write_generic,
1550   - 0x00000000);
1551   - /* XXX : not implemented */
1552   - spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1553   - SPR_NOACCESS, SPR_NOACCESS,
1554   - &spr_read_generic, &spr_write_generic,
1555   - 0x00000000);
1556   - /* XXX : not implemented */
1557   - spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1558   - SPR_NOACCESS, SPR_NOACCESS,
1559   - &spr_read_generic, &spr_write_generic,
1560   - 0x00000000);
1561   - /* XXX : not implemented */
1562   - spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1563   - SPR_NOACCESS, SPR_NOACCESS,
1564   - &spr_read_generic, &spr_write_generic,
1565   - 0x00000000);
1566   - /* XXX : not implemented */
1567   - spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1568   - SPR_NOACCESS, SPR_NOACCESS,
1569   - &spr_read_generic, &spr_write_generic,
1570   - 0x00000000);
  1473 + for (i = 0; i < 8; i++) {
  1474 + if (mas_mask & (1 << i)) {
  1475 + spr_register(env, mas_sprn[i], mas_names[i],
  1476 + SPR_NOACCESS, SPR_NOACCESS,
  1477 + &spr_read_generic, &spr_write_generic,
  1478 + 0x00000000);
  1479 + }
  1480 + }
1571 1481 if (env->nb_pids > 1) {
1572 1482 /* XXX : not implemented */
1573 1483 spr_register(env, SPR_BOOKE_PID1, "PID1",
... ... @@ -1915,34 +1825,19 @@ static void gen_spr_405 (CPUPPCState *env)
1915 1825 SPR_NOACCESS, SPR_NOACCESS,
1916 1826 &spr_read_generic, &spr_write_generic,
1917 1827 0x00000000);
1918   - spr_register(env, SPR_USPRG4, "USPRG4",
1919   - &spr_read_ureg, SPR_NOACCESS,
1920   - &spr_read_ureg, SPR_NOACCESS,
1921   - 0x00000000);
1922 1828 spr_register(env, SPR_SPRG5, "SPRG5",
1923 1829 SPR_NOACCESS, SPR_NOACCESS,
1924 1830 spr_read_generic, &spr_write_generic,
1925 1831 0x00000000);
1926   - spr_register(env, SPR_USPRG5, "USPRG5",
1927   - &spr_read_ureg, SPR_NOACCESS,
1928   - &spr_read_ureg, SPR_NOACCESS,
1929   - 0x00000000);
1930 1832 spr_register(env, SPR_SPRG6, "SPRG6",
1931 1833 SPR_NOACCESS, SPR_NOACCESS,
1932 1834 spr_read_generic, &spr_write_generic,
1933 1835 0x00000000);
1934   - spr_register(env, SPR_USPRG6, "USPRG6",
1935   - &spr_read_ureg, SPR_NOACCESS,
1936   - &spr_read_ureg, SPR_NOACCESS,
1937   - 0x00000000);
1938 1836 spr_register(env, SPR_SPRG7, "SPRG7",
1939 1837 SPR_NOACCESS, SPR_NOACCESS,
1940 1838 spr_read_generic, &spr_write_generic,
1941 1839 0x00000000);
1942   - spr_register(env, SPR_USPRG7, "USPRG7",
1943   - &spr_read_ureg, SPR_NOACCESS,
1944   - &spr_read_ureg, SPR_NOACCESS,
1945   - 0x00000000);
  1840 + gen_spr_usprgh(env);
1946 1841 }
1947 1842  
1948 1843 /* SPR shared between PowerPC 401 & 403 implementations */
... ... @@ -2206,91 +2101,562 @@ static void gen_spr_620 (CPUPPCState *env)
2206 2101 }
2207 2102 #endif /* defined (TARGET_PPC64) */
2208 2103  
2209   -// XXX: TODO
2210   -/*
2211   - * AMR => SPR 29 (Power 2.04)
2212   - * CTRL => SPR 136 (Power 2.04)
2213   - * CTRL => SPR 152 (Power 2.04)
2214   - * SCOMC => SPR 276 (64 bits ?)
2215   - * SCOMD => SPR 277 (64 bits ?)
2216   - * TBU40 => SPR 286 (Power 2.04 hypv)
2217   - * HSPRG0 => SPR 304 (Power 2.04 hypv)
2218   - * HSPRG1 => SPR 305 (Power 2.04 hypv)
2219   - * HDSISR => SPR 306 (Power 2.04 hypv)
2220   - * HDAR => SPR 307 (Power 2.04 hypv)
2221   - * PURR => SPR 309 (Power 2.04 hypv)
2222   - * HDEC => SPR 310 (Power 2.04 hypv)
2223   - * HIOR => SPR 311 (hypv)
2224   - * RMOR => SPR 312 (970)
2225   - * HRMOR => SPR 313 (Power 2.04 hypv)
2226   - * HSRR0 => SPR 314 (Power 2.04 hypv)
2227   - * HSRR1 => SPR 315 (Power 2.04 hypv)
2228   - * LPCR => SPR 316 (970)
2229   - * LPIDR => SPR 317 (970)
2230   - * SPEFSCR => SPR 512 (Power 2.04 emb)
2231   - * EPR => SPR 702 (Power 2.04 emb)
2232   - * perf => 768-783 (Power 2.04)
2233   - * perf => 784-799 (Power 2.04)
2234   - * PPR => SPR 896 (Power 2.04)
2235   - * EPLC => SPR 947 (Power 2.04 emb)
2236   - * EPSC => SPR 948 (Power 2.04 emb)
2237   - * DABRX => 1015 (Power 2.04 hypv)
2238   - * FPECR => SPR 1022 (?)
2239   - * ... and more (thermal management, performance counters, ...)
2240   - */
2241   -
2242   -/*****************************************************************************/
2243   -/* Exception vectors models */
2244   -static void init_excp_4xx_real (CPUPPCState *env)
2245   -{
2246   -#if !defined(CONFIG_USER_ONLY)
2247   - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2248   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2249   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2250   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2251   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2252   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2253   - env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2254   - env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2255   - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2256   - env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2257   - env->excp_prefix = 0x00000000UL;
2258   - env->ivor_mask = 0x0000FFF0UL;
2259   - env->ivpr_mask = 0xFFFF0000UL;
2260   - /* Hardware reset vector */
2261   - env->hreset_vector = 0xFFFFFFFCUL;
2262   -#endif
2263   -}
2264   -
2265   -static void init_excp_4xx_softmmu (CPUPPCState *env)
2266   -{
2267   -#if !defined(CONFIG_USER_ONLY)
2268   - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2269   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2270   - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2271   - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2272   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2273   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2274   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2275   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2276   - env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2277   - env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2278   - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2279   - env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2280   - env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2281   - env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2282   - env->excp_prefix = 0x00000000UL;
2283   - env->ivor_mask = 0x0000FFF0UL;
2284   - env->ivpr_mask = 0xFFFF0000UL;
2285   - /* Hardware reset vector */
2286   - env->hreset_vector = 0xFFFFFFFCUL;
2287   -#endif
2288   -}
2289   -
2290   -static void init_excp_BookE (CPUPPCState *env)
  2104 +static void gen_spr_5xx_8xx (CPUPPCState *env)
2291 2105 {
2292   -#if !defined(CONFIG_USER_ONLY)
2293   - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
  2106 + /* Exception processing */
  2107 + spr_register(env, SPR_DSISR, "DSISR",
  2108 + SPR_NOACCESS, SPR_NOACCESS,
  2109 + &spr_read_generic, &spr_write_generic,
  2110 + 0x00000000);
  2111 + spr_register(env, SPR_DAR, "DAR",
  2112 + SPR_NOACCESS, SPR_NOACCESS,
  2113 + &spr_read_generic, &spr_write_generic,
  2114 + 0x00000000);
  2115 + /* Timer */
  2116 + spr_register(env, SPR_DECR, "DECR",
  2117 + SPR_NOACCESS, SPR_NOACCESS,
  2118 + &spr_read_decr, &spr_write_decr,
  2119 + 0x00000000);
  2120 + /* XXX : not implemented */
  2121 + spr_register(env, SPR_MPC_EIE, "EIE",
  2122 + SPR_NOACCESS, SPR_NOACCESS,
  2123 + &spr_read_generic, &spr_write_generic,
  2124 + 0x00000000);
  2125 + /* XXX : not implemented */
  2126 + spr_register(env, SPR_MPC_EID, "EID",
  2127 + SPR_NOACCESS, SPR_NOACCESS,
  2128 + &spr_read_generic, &spr_write_generic,
  2129 + 0x00000000);
  2130 + /* XXX : not implemented */
  2131 + spr_register(env, SPR_MPC_NRI, "NRI",
  2132 + SPR_NOACCESS, SPR_NOACCESS,
  2133 + &spr_read_generic, &spr_write_generic,
  2134 + 0x00000000);
  2135 + /* XXX : not implemented */
  2136 + spr_register(env, SPR_MPC_CMPA, "CMPA",
  2137 + SPR_NOACCESS, SPR_NOACCESS,
  2138 + &spr_read_generic, &spr_write_generic,
  2139 + 0x00000000);
  2140 + /* XXX : not implemented */
  2141 + spr_register(env, SPR_MPC_CMPB, "CMPB",
  2142 + SPR_NOACCESS, SPR_NOACCESS,
  2143 + &spr_read_generic, &spr_write_generic,
  2144 + 0x00000000);
  2145 + /* XXX : not implemented */
  2146 + spr_register(env, SPR_MPC_CMPC, "CMPC",
  2147 + SPR_NOACCESS, SPR_NOACCESS,
  2148 + &spr_read_generic, &spr_write_generic,
  2149 + 0x00000000);
  2150 + /* XXX : not implemented */
  2151 + spr_register(env, SPR_MPC_CMPD, "CMPD",
  2152 + SPR_NOACCESS, SPR_NOACCESS,
  2153 + &spr_read_generic, &spr_write_generic,
  2154 + 0x00000000);
  2155 + /* XXX : not implemented */
  2156 + spr_register(env, SPR_MPC_ECR, "ECR",
  2157 + SPR_NOACCESS, SPR_NOACCESS,
  2158 + &spr_read_generic, &spr_write_generic,
  2159 + 0x00000000);
  2160 + /* XXX : not implemented */
  2161 + spr_register(env, SPR_MPC_DER, "DER",
  2162 + SPR_NOACCESS, SPR_NOACCESS,
  2163 + &spr_read_generic, &spr_write_generic,
  2164 + 0x00000000);
  2165 + /* XXX : not implemented */
  2166 + spr_register(env, SPR_MPC_COUNTA, "COUNTA",
  2167 + SPR_NOACCESS, SPR_NOACCESS,
  2168 + &spr_read_generic, &spr_write_generic,
  2169 + 0x00000000);
  2170 + /* XXX : not implemented */
  2171 + spr_register(env, SPR_MPC_COUNTB, "COUNTB",
  2172 + SPR_NOACCESS, SPR_NOACCESS,
  2173 + &spr_read_generic, &spr_write_generic,
  2174 + 0x00000000);
  2175 + /* XXX : not implemented */
  2176 + spr_register(env, SPR_MPC_CMPE, "CMPE",
  2177 + SPR_NOACCESS, SPR_NOACCESS,
  2178 + &spr_read_generic, &spr_write_generic,
  2179 + 0x00000000);
  2180 + /* XXX : not implemented */
  2181 + spr_register(env, SPR_MPC_CMPF, "CMPF",
  2182 + SPR_NOACCESS, SPR_NOACCESS,
  2183 + &spr_read_generic, &spr_write_generic,
  2184 + 0x00000000);
  2185 + /* XXX : not implemented */
  2186 + spr_register(env, SPR_MPC_CMPG, "CMPG",
  2187 + SPR_NOACCESS, SPR_NOACCESS,
  2188 + &spr_read_generic, &spr_write_generic,
  2189 + 0x00000000);
  2190 + /* XXX : not implemented */
  2191 + spr_register(env, SPR_MPC_CMPH, "CMPH",
  2192 + SPR_NOACCESS, SPR_NOACCESS,
  2193 + &spr_read_generic, &spr_write_generic,
  2194 + 0x00000000);
  2195 + /* XXX : not implemented */
  2196 + spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
  2197 + SPR_NOACCESS, SPR_NOACCESS,
  2198 + &spr_read_generic, &spr_write_generic,
  2199 + 0x00000000);
  2200 + /* XXX : not implemented */
  2201 + spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
  2202 + SPR_NOACCESS, SPR_NOACCESS,
  2203 + &spr_read_generic, &spr_write_generic,
  2204 + 0x00000000);
  2205 + /* XXX : not implemented */
  2206 + spr_register(env, SPR_MPC_BAR, "BAR",
  2207 + SPR_NOACCESS, SPR_NOACCESS,
  2208 + &spr_read_generic, &spr_write_generic,
  2209 + 0x00000000);
  2210 + /* XXX : not implemented */
  2211 + spr_register(env, SPR_MPC_DPDR, "DPDR",
  2212 + SPR_NOACCESS, SPR_NOACCESS,
  2213 + &spr_read_generic, &spr_write_generic,
  2214 + 0x00000000);
  2215 + /* XXX : not implemented */
  2216 + spr_register(env, SPR_MPC_IMMR, "IMMR",
  2217 + SPR_NOACCESS, SPR_NOACCESS,
  2218 + &spr_read_generic, &spr_write_generic,
  2219 + 0x00000000);
  2220 +}
  2221 +
  2222 +static void gen_spr_5xx (CPUPPCState *env)
  2223 +{
  2224 + /* XXX : not implemented */
  2225 + spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
  2226 + SPR_NOACCESS, SPR_NOACCESS,
  2227 + &spr_read_generic, &spr_write_generic,
  2228 + 0x00000000);
  2229 + /* XXX : not implemented */
  2230 + spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
  2231 + SPR_NOACCESS, SPR_NOACCESS,
  2232 + &spr_read_generic, &spr_write_generic,
  2233 + 0x00000000);
  2234 + /* XXX : not implemented */
  2235 + spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
  2236 + SPR_NOACCESS, SPR_NOACCESS,
  2237 + &spr_read_generic, &spr_write_generic,
  2238 + 0x00000000);
  2239 + /* XXX : not implemented */
  2240 + spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
  2241 + SPR_NOACCESS, SPR_NOACCESS,
  2242 + &spr_read_generic, &spr_write_generic,
  2243 + 0x00000000);
  2244 + /* XXX : not implemented */
  2245 + spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
  2246 + SPR_NOACCESS, SPR_NOACCESS,
  2247 + &spr_read_generic, &spr_write_generic,
  2248 + 0x00000000);
  2249 + /* XXX : not implemented */
  2250 + spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
  2251 + SPR_NOACCESS, SPR_NOACCESS,
  2252 + &spr_read_generic, &spr_write_generic,
  2253 + 0x00000000);
  2254 + /* XXX : not implemented */
  2255 + spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
  2256 + SPR_NOACCESS, SPR_NOACCESS,
  2257 + &spr_read_generic, &spr_write_generic,
  2258 + 0x00000000);
  2259 + /* XXX : not implemented */
  2260 + spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
  2261 + SPR_NOACCESS, SPR_NOACCESS,
  2262 + &spr_read_generic, &spr_write_generic,
  2263 + 0x00000000);
  2264 + /* XXX : not implemented */
  2265 + spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
  2266 + SPR_NOACCESS, SPR_NOACCESS,
  2267 + &spr_read_generic, &spr_write_generic,
  2268 + 0x00000000);
  2269 + /* XXX : not implemented */
  2270 + spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
  2271 + SPR_NOACCESS, SPR_NOACCESS,
  2272 + &spr_read_generic, &spr_write_generic,
  2273 + 0x00000000);
  2274 + /* XXX : not implemented */
  2275 + spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
  2276 + SPR_NOACCESS, SPR_NOACCESS,
  2277 + &spr_read_generic, &spr_write_generic,
  2278 + 0x00000000);
  2279 + /* XXX : not implemented */
  2280 + spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
  2281 + SPR_NOACCESS, SPR_NOACCESS,
  2282 + &spr_read_generic, &spr_write_generic,
  2283 + 0x00000000);
  2284 + /* XXX : not implemented */
  2285 + spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
  2286 + SPR_NOACCESS, SPR_NOACCESS,
  2287 + &spr_read_generic, &spr_write_generic,
  2288 + 0x00000000);
  2289 + /* XXX : not implemented */
  2290 + spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
  2291 + SPR_NOACCESS, SPR_NOACCESS,
  2292 + &spr_read_generic, &spr_write_generic,
  2293 + 0x00000000);
  2294 + /* XXX : not implemented */
  2295 + spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
  2296 + SPR_NOACCESS, SPR_NOACCESS,
  2297 + &spr_read_generic, &spr_write_generic,
  2298 + 0x00000000);
  2299 + /* XXX : not implemented */
  2300 + spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
  2301 + SPR_NOACCESS, SPR_NOACCESS,
  2302 + &spr_read_generic, &spr_write_generic,
  2303 + 0x00000000);
  2304 + /* XXX : not implemented */
  2305 + spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
  2306 + SPR_NOACCESS, SPR_NOACCESS,
  2307 + &spr_read_generic, &spr_write_generic,
  2308 + 0x00000000);
  2309 + /* XXX : not implemented */
  2310 + spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
  2311 + SPR_NOACCESS, SPR_NOACCESS,
  2312 + &spr_read_generic, &spr_write_generic,
  2313 + 0x00000000);
  2314 + /* XXX : not implemented */
  2315 + spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
  2316 + SPR_NOACCESS, SPR_NOACCESS,
  2317 + &spr_read_generic, &spr_write_generic,
  2318 + 0x00000000);
  2319 + /* XXX : not implemented */
  2320 + spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
  2321 + SPR_NOACCESS, SPR_NOACCESS,
  2322 + &spr_read_generic, &spr_write_generic,
  2323 + 0x00000000);
  2324 + /* XXX : not implemented */
  2325 + spr_register(env, SPR_RCPU_FPECR, "FPECR",
  2326 + SPR_NOACCESS, SPR_NOACCESS,
  2327 + &spr_read_generic, &spr_write_generic,
  2328 + 0x00000000);
  2329 +}
  2330 +
  2331 +static void gen_spr_8xx (CPUPPCState *env)
  2332 +{
  2333 + /* XXX : not implemented */
  2334 + spr_register(env, SPR_MPC_IC_CST, "IC_CST",
  2335 + SPR_NOACCESS, SPR_NOACCESS,
  2336 + &spr_read_generic, &spr_write_generic,
  2337 + 0x00000000);
  2338 + /* XXX : not implemented */
  2339 + spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
  2340 + SPR_NOACCESS, SPR_NOACCESS,
  2341 + &spr_read_generic, &spr_write_generic,
  2342 + 0x00000000);
  2343 + /* XXX : not implemented */
  2344 + spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
  2345 + SPR_NOACCESS, SPR_NOACCESS,
  2346 + &spr_read_generic, &spr_write_generic,
  2347 + 0x00000000);
  2348 + /* XXX : not implemented */
  2349 + spr_register(env, SPR_MPC_DC_CST, "DC_CST",
  2350 + SPR_NOACCESS, SPR_NOACCESS,
  2351 + &spr_read_generic, &spr_write_generic,
  2352 + 0x00000000);
  2353 + /* XXX : not implemented */
  2354 + spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
  2355 + SPR_NOACCESS, SPR_NOACCESS,
  2356 + &spr_read_generic, &spr_write_generic,
  2357 + 0x00000000);
  2358 + /* XXX : not implemented */
  2359 + spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
  2360 + SPR_NOACCESS, SPR_NOACCESS,
  2361 + &spr_read_generic, &spr_write_generic,
  2362 + 0x00000000);
  2363 + /* XXX : not implemented */
  2364 + spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
  2365 + SPR_NOACCESS, SPR_NOACCESS,
  2366 + &spr_read_generic, &spr_write_generic,
  2367 + 0x00000000);
  2368 + /* XXX : not implemented */
  2369 + spr_register(env, SPR_MPC_MI_AP, "MI_AP",
  2370 + SPR_NOACCESS, SPR_NOACCESS,
  2371 + &spr_read_generic, &spr_write_generic,
  2372 + 0x00000000);
  2373 + /* XXX : not implemented */
  2374 + spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
  2375 + SPR_NOACCESS, SPR_NOACCESS,
  2376 + &spr_read_generic, &spr_write_generic,
  2377 + 0x00000000);
  2378 + /* XXX : not implemented */
  2379 + spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
  2380 + SPR_NOACCESS, SPR_NOACCESS,
  2381 + &spr_read_generic, &spr_write_generic,
  2382 + 0x00000000);
  2383 + /* XXX : not implemented */
  2384 + spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
  2385 + SPR_NOACCESS, SPR_NOACCESS,
  2386 + &spr_read_generic, &spr_write_generic,
  2387 + 0x00000000);
  2388 + /* XXX : not implemented */
  2389 + spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
  2390 + SPR_NOACCESS, SPR_NOACCESS,
  2391 + &spr_read_generic, &spr_write_generic,
  2392 + 0x00000000);
  2393 + /* XXX : not implemented */
  2394 + spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
  2395 + SPR_NOACCESS, SPR_NOACCESS,
  2396 + &spr_read_generic, &spr_write_generic,
  2397 + 0x00000000);
  2398 + /* XXX : not implemented */
  2399 + spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
  2400 + SPR_NOACCESS, SPR_NOACCESS,
  2401 + &spr_read_generic, &spr_write_generic,
  2402 + 0x00000000);
  2403 + /* XXX : not implemented */
  2404 + spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
  2405 + SPR_NOACCESS, SPR_NOACCESS,
  2406 + &spr_read_generic, &spr_write_generic,
  2407 + 0x00000000);
  2408 + /* XXX : not implemented */
  2409 + spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
  2410 + SPR_NOACCESS, SPR_NOACCESS,
  2411 + &spr_read_generic, &spr_write_generic,
  2412 + 0x00000000);
  2413 + /* XXX : not implemented */
  2414 + spr_register(env, SPR_MPC_MD_AP, "MD_AP",
  2415 + SPR_NOACCESS, SPR_NOACCESS,
  2416 + &spr_read_generic, &spr_write_generic,
  2417 + 0x00000000);
  2418 + /* XXX : not implemented */
  2419 + spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
  2420 + SPR_NOACCESS, SPR_NOACCESS,
  2421 + &spr_read_generic, &spr_write_generic,
  2422 + 0x00000000);
  2423 + /* XXX : not implemented */
  2424 + spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
  2425 + SPR_NOACCESS, SPR_NOACCESS,
  2426 + &spr_read_generic, &spr_write_generic,
  2427 + 0x00000000);
  2428 + /* XXX : not implemented */
  2429 + spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
  2430 + SPR_NOACCESS, SPR_NOACCESS,
  2431 + &spr_read_generic, &spr_write_generic,
  2432 + 0x00000000);
  2433 + /* XXX : not implemented */
  2434 + spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
  2435 + SPR_NOACCESS, SPR_NOACCESS,
  2436 + &spr_read_generic, &spr_write_generic,
  2437 + 0x00000000);
  2438 + /* XXX : not implemented */
  2439 + spr_register(env, SPR_MPC_MD_TW, "MD_TW",
  2440 + SPR_NOACCESS, SPR_NOACCESS,
  2441 + &spr_read_generic, &spr_write_generic,
  2442 + 0x00000000);
  2443 + /* XXX : not implemented */
  2444 + spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
  2445 + SPR_NOACCESS, SPR_NOACCESS,
  2446 + &spr_read_generic, &spr_write_generic,
  2447 + 0x00000000);
  2448 + /* XXX : not implemented */
  2449 + spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
  2450 + SPR_NOACCESS, SPR_NOACCESS,
  2451 + &spr_read_generic, &spr_write_generic,
  2452 + 0x00000000);
  2453 + /* XXX : not implemented */
  2454 + spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
  2455 + SPR_NOACCESS, SPR_NOACCESS,
  2456 + &spr_read_generic, &spr_write_generic,
  2457 + 0x00000000);
  2458 +}
  2459 +
  2460 +// XXX: TODO
  2461 +/*
  2462 + * AMR => SPR 29 (Power 2.04)
  2463 + * CTRL => SPR 136 (Power 2.04)
  2464 + * CTRL => SPR 152 (Power 2.04)
  2465 + * SCOMC => SPR 276 (64 bits ?)
  2466 + * SCOMD => SPR 277 (64 bits ?)
  2467 + * TBU40 => SPR 286 (Power 2.04 hypv)
  2468 + * HSPRG0 => SPR 304 (Power 2.04 hypv)
  2469 + * HSPRG1 => SPR 305 (Power 2.04 hypv)
  2470 + * HDSISR => SPR 306 (Power 2.04 hypv)
  2471 + * HDAR => SPR 307 (Power 2.04 hypv)
  2472 + * PURR => SPR 309 (Power 2.04 hypv)
  2473 + * HDEC => SPR 310 (Power 2.04 hypv)
  2474 + * HIOR => SPR 311 (hypv)
  2475 + * RMOR => SPR 312 (970)
  2476 + * HRMOR => SPR 313 (Power 2.04 hypv)
  2477 + * HSRR0 => SPR 314 (Power 2.04 hypv)
  2478 + * HSRR1 => SPR 315 (Power 2.04 hypv)
  2479 + * LPCR => SPR 316 (970)
  2480 + * LPIDR => SPR 317 (970)
  2481 + * SPEFSCR => SPR 512 (Power 2.04 emb)
  2482 + * EPR => SPR 702 (Power 2.04 emb)
  2483 + * perf => 768-783 (Power 2.04)
  2484 + * perf => 784-799 (Power 2.04)
  2485 + * PPR => SPR 896 (Power 2.04)
  2486 + * EPLC => SPR 947 (Power 2.04 emb)
  2487 + * EPSC => SPR 948 (Power 2.04 emb)
  2488 + * DABRX => 1015 (Power 2.04 hypv)
  2489 + * FPECR => SPR 1022 (?)
  2490 + * ... and more (thermal management, performance counters, ...)
  2491 + */
  2492 +
  2493 +/*****************************************************************************/
  2494 +/* Exception vectors models */
  2495 +static void init_excp_4xx_real (CPUPPCState *env)
  2496 +{
  2497 +#if !defined(CONFIG_USER_ONLY)
  2498 + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
  2499 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2500 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2501 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2502 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2503 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2504 + env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
  2505 + env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
  2506 + env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
  2507 + env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
  2508 + env->excp_prefix = 0x00000000UL;
  2509 + env->ivor_mask = 0x0000FFF0UL;
  2510 + env->ivpr_mask = 0xFFFF0000UL;
  2511 + /* Hardware reset vector */
  2512 + env->hreset_vector = 0xFFFFFFFCUL;
  2513 +#endif
  2514 +}
  2515 +
  2516 +static void init_excp_4xx_softmmu (CPUPPCState *env)
  2517 +{
  2518 +#if !defined(CONFIG_USER_ONLY)
  2519 + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
  2520 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2521 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2522 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2523 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2524 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2525 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2526 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2527 + env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
  2528 + env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
  2529 + env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
  2530 + env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
  2531 + env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
  2532 + env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
  2533 + env->excp_prefix = 0x00000000UL;
  2534 + env->ivor_mask = 0x0000FFF0UL;
  2535 + env->ivpr_mask = 0xFFFF0000UL;
  2536 + /* Hardware reset vector */
  2537 + env->hreset_vector = 0xFFFFFFFCUL;
  2538 +#endif
  2539 +}
  2540 +
  2541 +static void init_excp_MPC5xx (CPUPPCState *env)
  2542 +{
  2543 +#if !defined(CONFIG_USER_ONLY)
  2544 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2545 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2546 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2547 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2548 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2549 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
  2550 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2551 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2552 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2553 + env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
  2554 + env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
  2555 + env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
  2556 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
  2557 + env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
  2558 + env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
  2559 + env->excp_prefix = 0x00000000UL;
  2560 + env->ivor_mask = 0x0000FFF0UL;
  2561 + env->ivpr_mask = 0xFFFF0000UL;
  2562 + /* Hardware reset vector */
  2563 + env->hreset_vector = 0xFFFFFFFCUL;
  2564 +#endif
  2565 +}
  2566 +
  2567 +static void init_excp_MPC8xx (CPUPPCState *env)
  2568 +{
  2569 +#if !defined(CONFIG_USER_ONLY)
  2570 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2571 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2572 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2573 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2574 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2575 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2576 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2577 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
  2578 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2579 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2580 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2581 + env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
  2582 + env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
  2583 + env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
  2584 + env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
  2585 + env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
  2586 + env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
  2587 + env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
  2588 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
  2589 + env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
  2590 + env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
  2591 + env->excp_prefix = 0x00000000UL;
  2592 + env->ivor_mask = 0x0000FFF0UL;
  2593 + env->ivpr_mask = 0xFFFF0000UL;
  2594 + /* Hardware reset vector */
  2595 + env->hreset_vector = 0xFFFFFFFCUL;
  2596 +#endif
  2597 +}
  2598 +
  2599 +static void init_excp_G2 (CPUPPCState *env)
  2600 +{
  2601 +#if !defined(CONFIG_USER_ONLY)
  2602 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2603 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2604 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2605 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2606 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2607 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2608 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2609 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
  2610 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2611 + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
  2612 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2613 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2614 + env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
  2615 + env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
  2616 + env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
  2617 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
  2618 + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
  2619 + env->excp_prefix = 0x00000000UL;
  2620 + /* Hardware reset vector */
  2621 + env->hreset_vector = 0xFFFFFFFCUL;
  2622 +#endif
  2623 +}
  2624 +
  2625 +static void init_excp_e200 (CPUPPCState *env)
  2626 +{
  2627 +#if !defined(CONFIG_USER_ONLY)
  2628 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
  2629 + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
  2630 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
  2631 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
  2632 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
  2633 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
  2634 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
  2635 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
  2636 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
  2637 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
  2638 + env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
  2639 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
  2640 + env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
  2641 + env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
  2642 + env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
  2643 + env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
  2644 + env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
  2645 + env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
  2646 + env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
  2647 + env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
  2648 + env->excp_prefix = 0x00000000UL;
  2649 + env->ivor_mask = 0x0000FFF7UL;
  2650 + env->ivpr_mask = 0xFFFF0000UL;
  2651 + /* Hardware reset vector */
  2652 + env->hreset_vector = 0xFFFFFFFCUL;
  2653 +#endif
  2654 +}
  2655 +
  2656 +static void init_excp_BookE (CPUPPCState *env)
  2657 +{
  2658 +#if !defined(CONFIG_USER_ONLY)
  2659 + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2294 2660 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2295 2661 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2296 2662 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
... ... @@ -2388,7 +2754,158 @@ static void init_excp_603 (CPUPPCState *env)
2388 2754 #endif
2389 2755 }
2390 2756  
2391   -static void init_excp_G2 (CPUPPCState *env)
  2757 +static void init_excp_604 (CPUPPCState *env)
  2758 +{
  2759 +#if !defined(CONFIG_USER_ONLY)
  2760 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2761 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2762 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2763 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2764 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2765 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2766 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2767 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
  2768 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2769 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2770 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2771 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
  2772 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
  2773 + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
  2774 + env->excp_prefix = 0x00000000UL;
  2775 + /* Hardware reset vector */
  2776 + env->hreset_vector = 0xFFFFFFFCUL;
  2777 +#endif
  2778 +}
  2779 +
  2780 +#if defined(TARGET_PPC64)
  2781 +static void init_excp_620 (CPUPPCState *env)
  2782 +{
  2783 +#if !defined(CONFIG_USER_ONLY)
  2784 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2785 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2786 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2787 + env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
  2788 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2789 + env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
  2790 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2791 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2792 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2793 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
  2794 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2795 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2796 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2797 + env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
  2798 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
  2799 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
  2800 + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
  2801 + env->excp_prefix = 0xFFF00000UL;
  2802 + /* Hardware reset vector */
  2803 + env->hreset_vector = 0x0000000000000100ULL;
  2804 +#endif
  2805 +}
  2806 +#endif /* defined(TARGET_PPC64) */
  2807 +
  2808 +static void init_excp_7x0 (CPUPPCState *env)
  2809 +{
  2810 +#if !defined(CONFIG_USER_ONLY)
  2811 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2812 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2813 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2814 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2815 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2816 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2817 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2818 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
  2819 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2820 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2821 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2822 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
  2823 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
  2824 + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
  2825 + env->excp_prefix = 0x00000000UL;
  2826 + /* Hardware reset vector */
  2827 + env->hreset_vector = 0xFFFFFFFCUL;
  2828 +#endif
  2829 +}
  2830 +
  2831 +static void init_excp_750FX (CPUPPCState *env)
  2832 +{
  2833 +#if !defined(CONFIG_USER_ONLY)
  2834 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2835 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2836 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2837 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2838 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2839 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2840 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2841 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
  2842 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2843 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2844 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2845 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
  2846 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
  2847 + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
  2848 + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
  2849 + env->excp_prefix = 0x00000000UL;
  2850 + /* Hardware reset vector */
  2851 + env->hreset_vector = 0xFFFFFFFCUL;
  2852 +#endif
  2853 +}
  2854 +
  2855 +/* XXX: Check if this is correct */
  2856 +static void init_excp_7x5 (CPUPPCState *env)
  2857 +{
  2858 +#if !defined(CONFIG_USER_ONLY)
  2859 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2860 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2861 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2862 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2863 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2864 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2865 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2866 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
  2867 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2868 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2869 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2870 + env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
  2871 + env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
  2872 + env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
  2873 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
  2874 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
  2875 + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
  2876 + env->excp_prefix = 0x00000000UL;
  2877 + /* Hardware reset vector */
  2878 + env->hreset_vector = 0xFFFFFFFCUL;
  2879 +#endif
  2880 +}
  2881 +
  2882 +static void init_excp_7400 (CPUPPCState *env)
  2883 +{
  2884 +#if !defined(CONFIG_USER_ONLY)
  2885 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2886 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2887 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2888 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2889 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2890 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2891 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2892 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
  2893 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2894 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2895 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2896 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
  2897 + env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
  2898 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
  2899 + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
  2900 + env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
  2901 + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
  2902 + env->excp_prefix = 0x00000000UL;
  2903 + /* Hardware reset vector */
  2904 + env->hreset_vector = 0xFFFFFFFCUL;
  2905 +#endif
  2906 +}
  2907 +
  2908 +static void init_excp_7450 (CPUPPCState *env)
2392 2909 {
2393 2910 #if !defined(CONFIG_USER_ONLY)
2394 2911 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
... ... @@ -2400,839 +2917,1188 @@ static void init_excp_G2 (CPUPPCState *env)
2400 2917 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2401 2918 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2402 2919 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2403   - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2404 2920 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2405 2921 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2922 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
  2923 + env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2406 2924 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2407 2925 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2408 2926 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2409 2927 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2410 2928 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
  2929 + env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2411 2930 env->excp_prefix = 0x00000000UL;
2412 2931 /* Hardware reset vector */
2413 2932 env->hreset_vector = 0xFFFFFFFCUL;
2414 2933 #endif
2415 2934 }
2416 2935  
2417   -static void init_excp_604 (CPUPPCState *env)
  2936 +#if defined (TARGET_PPC64)
  2937 +static void init_excp_970 (CPUPPCState *env)
  2938 +{
  2939 +#if !defined(CONFIG_USER_ONLY)
  2940 + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
  2941 + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
  2942 + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
  2943 + env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
  2944 + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
  2945 + env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
  2946 + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
  2947 + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
  2948 + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
  2949 + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
  2950 + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
  2951 + env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
  2952 + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
  2953 + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
  2954 + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
  2955 + env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
  2956 + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
  2957 + env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
  2958 + env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
  2959 + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
  2960 + env->excp_prefix = 0x00000000FFF00000ULL;
  2961 + /* Hardware reset vector */
  2962 + env->hreset_vector = 0x0000000000000100ULL;
  2963 +#endif
  2964 +}
  2965 +#endif
  2966 +
  2967 +/*****************************************************************************/
  2968 +/* Power management enable checks */
  2969 +static int check_pow_none (CPUPPCState *env)
  2970 +{
  2971 + return 0;
  2972 +}
  2973 +
  2974 +static int check_pow_nocheck (CPUPPCState *env)
  2975 +{
  2976 + return 1;
  2977 +}
  2978 +
  2979 +static int check_pow_hid0 (CPUPPCState *env)
  2980 +{
  2981 + if (env->spr[SPR_HID0] & 0x00E00000)
  2982 + return 1;
  2983 +
  2984 + return 0;
  2985 +}
  2986 +
  2987 +/*****************************************************************************/
  2988 +/* PowerPC implementations definitions */
  2989 +
  2990 +/* PowerPC 40x instruction set */
  2991 +#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_WRTEE | \
  2992 + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)
  2993 +
  2994 +/* PowerPC 401 */
  2995 +#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  2996 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  2997 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  2998 +#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
  2999 +#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
  3000 +#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
  3001 +#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
  3002 +#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
  3003 +#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
  3004 +#define check_pow_401 check_pow_nocheck
  3005 +
  3006 +static void init_proc_401 (CPUPPCState *env)
  3007 +{
  3008 + gen_spr_40x(env);
  3009 + gen_spr_401_403(env);
  3010 + gen_spr_401(env);
  3011 + init_excp_4xx_real(env);
  3012 + env->dcache_line_size = 32;
  3013 + env->icache_line_size = 32;
  3014 + /* Allocate hardware IRQ controller */
  3015 + ppc40x_irq_init(env);
  3016 +}
  3017 +
  3018 +/* PowerPC 401x2 */
  3019 +#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  3020 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  3021 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  3022 + PPC_CACHE_DCBA | PPC_MFTB | \
  3023 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  3024 +#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
  3025 +#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
  3026 +#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
  3027 +#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
  3028 +#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
  3029 +#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
  3030 +#define check_pow_401x2 check_pow_nocheck
  3031 +
  3032 +static void init_proc_401x2 (CPUPPCState *env)
2418 3033 {
  3034 + gen_spr_40x(env);
  3035 + gen_spr_401_403(env);
  3036 + gen_spr_401x2(env);
  3037 + gen_spr_compress(env);
  3038 + /* Memory management */
2419 3039 #if !defined(CONFIG_USER_ONLY)
2420   - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2421   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2422   - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2423   - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2424   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2425   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2426   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2427   - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2428   - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2429   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2430   - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2431   - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2432   - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2433   - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2434   - env->excp_prefix = 0x00000000UL;
2435   - /* Hardware reset vector */
2436   - env->hreset_vector = 0xFFFFFFFCUL;
  3040 + env->nb_tlb = 64;
  3041 + env->nb_ways = 1;
  3042 + env->id_tlbs = 0;
2437 3043 #endif
  3044 + init_excp_4xx_softmmu(env);
  3045 + env->dcache_line_size = 32;
  3046 + env->icache_line_size = 32;
  3047 + /* Allocate hardware IRQ controller */
  3048 + ppc40x_irq_init(env);
2438 3049 }
2439 3050  
2440   -#if defined(TARGET_PPC64)
2441   -static void init_excp_620 (CPUPPCState *env)
  3051 +/* PowerPC 401x3 */
  3052 +#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  3053 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  3054 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  3055 + PPC_CACHE_DCBA | PPC_MFTB | \
  3056 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  3057 +#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
  3058 +#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
  3059 +#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
  3060 +#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
  3061 +#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
  3062 +#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
  3063 +#define check_pow_401x3 check_pow_nocheck
  3064 +
  3065 +__attribute__ (( unused ))
  3066 +static void init_proc_401x3 (CPUPPCState *env)
  3067 +{
  3068 + gen_spr_40x(env);
  3069 + gen_spr_401_403(env);
  3070 + gen_spr_401(env);
  3071 + gen_spr_401x2(env);
  3072 + gen_spr_compress(env);
  3073 + init_excp_4xx_softmmu(env);
  3074 + env->dcache_line_size = 32;
  3075 + env->icache_line_size = 32;
  3076 + /* Allocate hardware IRQ controller */
  3077 + ppc40x_irq_init(env);
  3078 +}
  3079 +
  3080 +/* IOP480 */
  3081 +#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  3082 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  3083 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  3084 + PPC_CACHE_DCBA | \
  3085 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  3086 +#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
  3087 +#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
  3088 +#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
  3089 +#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
  3090 +#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
  3091 +#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
  3092 +#define check_pow_IOP480 check_pow_nocheck
  3093 +
  3094 +static void init_proc_IOP480 (CPUPPCState *env)
2442 3095 {
  3096 + gen_spr_40x(env);
  3097 + gen_spr_401_403(env);
  3098 + gen_spr_401x2(env);
  3099 + gen_spr_compress(env);
  3100 + /* Memory management */
2443 3101 #if !defined(CONFIG_USER_ONLY)
2444   - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2445   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2446   - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2447   - env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2448   - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2449   - env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2450   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2451   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2452   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2453   - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2454   - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2455   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2456   - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2457   - env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2458   - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2459   - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2460   - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2461   - env->excp_prefix = 0xFFF00000UL;
2462   - /* Hardware reset vector */
2463   - env->hreset_vector = 0x0000000000000100ULL;
  3102 + env->nb_tlb = 64;
  3103 + env->nb_ways = 1;
  3104 + env->id_tlbs = 0;
2464 3105 #endif
  3106 + init_excp_4xx_softmmu(env);
  3107 + env->dcache_line_size = 32;
  3108 + env->icache_line_size = 32;
  3109 + /* Allocate hardware IRQ controller */
  3110 + ppc40x_irq_init(env);
2465 3111 }
2466   -#endif /* defined(TARGET_PPC64) */
2467 3112  
2468   -static void init_excp_7x0 (CPUPPCState *env)
  3113 +/* PowerPC 403 */
  3114 +#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  3115 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  3116 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  3117 +#define POWERPC_MSRM_403 (0x000000000007D00DULL)
  3118 +#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
  3119 +#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
  3120 +#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
  3121 +#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
  3122 +#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
  3123 +#define check_pow_403 check_pow_nocheck
  3124 +
  3125 +static void init_proc_403 (CPUPPCState *env)
2469 3126 {
  3127 + gen_spr_40x(env);
  3128 + gen_spr_401_403(env);
  3129 + gen_spr_403(env);
  3130 + gen_spr_403_real(env);
  3131 + init_excp_4xx_real(env);
  3132 + env->dcache_line_size = 32;
  3133 + env->icache_line_size = 32;
  3134 + /* Allocate hardware IRQ controller */
  3135 + ppc40x_irq_init(env);
2470 3136 #if !defined(CONFIG_USER_ONLY)
2471   - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2472   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2473   - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2474   - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2475   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2476   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2477   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2478   - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2479   - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2480   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2481   - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2482   - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2483   - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2484   - env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2485   - env->excp_prefix = 0x00000000UL;
2486 3137 /* Hardware reset vector */
2487 3138 env->hreset_vector = 0xFFFFFFFCUL;
2488 3139 #endif
2489 3140 }
2490 3141  
2491   -static void init_excp_750FX (CPUPPCState *env)
  3142 +/* PowerPC 403 GCX */
  3143 +#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  3144 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  3145 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  3146 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
  3147 +#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
  3148 +#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
  3149 +#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
  3150 +#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
  3151 +#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
  3152 +#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
  3153 +#define check_pow_403GCX check_pow_nocheck
  3154 +
  3155 +static void init_proc_403GCX (CPUPPCState *env)
2492 3156 {
  3157 + gen_spr_40x(env);
  3158 + gen_spr_401_403(env);
  3159 + gen_spr_403(env);
  3160 + gen_spr_403_real(env);
  3161 + gen_spr_403_mmu(env);
  3162 + /* Bus access control */
  3163 + /* not emulated, as Qemu never does speculative access */
  3164 + spr_register(env, SPR_40x_SGR, "SGR",
  3165 + SPR_NOACCESS, SPR_NOACCESS,
  3166 + &spr_read_generic, &spr_write_generic,
  3167 + 0xFFFFFFFF);
  3168 + /* not emulated, as Qemu do not emulate caches */
  3169 + spr_register(env, SPR_40x_DCWR, "DCWR",
  3170 + SPR_NOACCESS, SPR_NOACCESS,
  3171 + &spr_read_generic, &spr_write_generic,
  3172 + 0x00000000);
  3173 + /* Memory management */
2493 3174 #if !defined(CONFIG_USER_ONLY)
2494   - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2495   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2496   - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2497   - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2498   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2499   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2500   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2501   - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2502   - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2503   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2504   - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2505   - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2506   - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2507   - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2508   - env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2509   - env->excp_prefix = 0x00000000UL;
2510   - /* Hardware reset vector */
2511   - env->hreset_vector = 0xFFFFFFFCUL;
  3175 + env->nb_tlb = 64;
  3176 + env->nb_ways = 1;
  3177 + env->id_tlbs = 0;
2512 3178 #endif
  3179 + init_excp_4xx_softmmu(env);
  3180 + env->dcache_line_size = 32;
  3181 + env->icache_line_size = 32;
  3182 + /* Allocate hardware IRQ controller */
  3183 + ppc40x_irq_init(env);
2513 3184 }
2514 3185  
2515   -/* XXX: Check if this is correct */
2516   -static void init_excp_7x5 (CPUPPCState *env)
  3186 +/* PowerPC 405 */
  3187 +#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  3188 + PPC_MFTB | \
  3189 + PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
  3190 + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
  3191 + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
  3192 + PPC_405_MAC)
  3193 +#define POWERPC_MSRM_405 (0x000000000006E630ULL)
  3194 +#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
  3195 +#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
  3196 +#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
  3197 +#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
  3198 +#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
  3199 + POWERPC_FLAG_DE)
  3200 +#define check_pow_405 check_pow_nocheck
  3201 +
  3202 +static void init_proc_405 (CPUPPCState *env)
2517 3203 {
2518   -#if !defined(CONFIG_USER_ONLY)
2519   - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2520   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2521   - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2522   - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2523   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2524   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2525   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2526   - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2527   - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2528   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2529   - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2530   - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2531   - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2532   - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2533   - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2534   - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2535   - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2536   - env->excp_prefix = 0x00000000UL;
2537   - /* Hardware reset vector */
2538   - env->hreset_vector = 0xFFFFFFFCUL;
  3204 + /* Time base */
  3205 + gen_tbl(env);
  3206 + gen_spr_40x(env);
  3207 + gen_spr_405(env);
  3208 + /* Bus access control */
  3209 + /* not emulated, as Qemu never does speculative access */
  3210 + spr_register(env, SPR_40x_SGR, "SGR",
  3211 + SPR_NOACCESS, SPR_NOACCESS,
  3212 + &spr_read_generic, &spr_write_generic,
  3213 + 0xFFFFFFFF);
  3214 + /* not emulated, as Qemu do not emulate caches */
  3215 + spr_register(env, SPR_40x_DCWR, "DCWR",
  3216 + SPR_NOACCESS, SPR_NOACCESS,
  3217 + &spr_read_generic, &spr_write_generic,
  3218 + 0x00000000);
  3219 + /* Memory management */
  3220 +#if !defined(CONFIG_USER_ONLY)
  3221 + env->nb_tlb = 64;
  3222 + env->nb_ways = 1;
  3223 + env->id_tlbs = 0;
2539 3224 #endif
  3225 + init_excp_4xx_softmmu(env);
  3226 + env->dcache_line_size = 32;
  3227 + env->icache_line_size = 32;
  3228 + /* Allocate hardware IRQ controller */
  3229 + ppc40x_irq_init(env);
2540 3230 }
2541 3231  
2542   -static void init_excp_7400 (CPUPPCState *env)
  3232 +/* PowerPC 440 EP */
  3233 +#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  3234 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  3235 + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
  3236 + PPC_440_SPEC | PPC_RFMCI)
  3237 +#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
  3238 +#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
  3239 +#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
  3240 +#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
  3241 +#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
  3242 +#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
  3243 + POWERPC_FLAG_DE)
  3244 +#define check_pow_440EP check_pow_nocheck
  3245 +
  3246 +__attribute__ (( unused ))
  3247 +static void init_proc_440EP (CPUPPCState *env)
2543 3248 {
  3249 + /* Time base */
  3250 + gen_tbl(env);
  3251 + gen_spr_BookE(env, 0x000000000000FFFFULL);
  3252 + gen_spr_440(env);
  3253 + gen_spr_usprgh(env);
  3254 + /* Processor identification */
  3255 + spr_register(env, SPR_BOOKE_PIR, "PIR",
  3256 + SPR_NOACCESS, SPR_NOACCESS,
  3257 + &spr_read_generic, &spr_write_pir,
  3258 + 0x00000000);
  3259 + /* XXX : not implemented */
  3260 + spr_register(env, SPR_BOOKE_IAC3, "IAC3",
  3261 + SPR_NOACCESS, SPR_NOACCESS,
  3262 + &spr_read_generic, &spr_write_generic,
  3263 + 0x00000000);
  3264 + /* XXX : not implemented */
  3265 + spr_register(env, SPR_BOOKE_IAC4, "IAC4",
  3266 + SPR_NOACCESS, SPR_NOACCESS,
  3267 + &spr_read_generic, &spr_write_generic,
  3268 + 0x00000000);
  3269 + /* XXX : not implemented */
  3270 + spr_register(env, SPR_BOOKE_DVC1, "DVC1",
  3271 + SPR_NOACCESS, SPR_NOACCESS,
  3272 + &spr_read_generic, &spr_write_generic,
  3273 + 0x00000000);
  3274 + /* XXX : not implemented */
  3275 + spr_register(env, SPR_BOOKE_DVC2, "DVC2",
  3276 + SPR_NOACCESS, SPR_NOACCESS,
  3277 + &spr_read_generic, &spr_write_generic,
  3278 + 0x00000000);
  3279 + /* XXX : not implemented */
  3280 + spr_register(env, SPR_BOOKE_MCSR, "MCSR",
  3281 + SPR_NOACCESS, SPR_NOACCESS,
  3282 + &spr_read_generic, &spr_write_generic,
  3283 + 0x00000000);
  3284 + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  3285 + SPR_NOACCESS, SPR_NOACCESS,
  3286 + &spr_read_generic, &spr_write_generic,
  3287 + 0x00000000);
  3288 + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  3289 + SPR_NOACCESS, SPR_NOACCESS,
  3290 + &spr_read_generic, &spr_write_generic,
  3291 + 0x00000000);
  3292 + /* XXX : not implemented */
  3293 + spr_register(env, SPR_440_CCR1, "CCR1",
  3294 + SPR_NOACCESS, SPR_NOACCESS,
  3295 + &spr_read_generic, &spr_write_generic,
  3296 + 0x00000000);
  3297 + /* Memory management */
2544 3298 #if !defined(CONFIG_USER_ONLY)
2545   - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2546   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2547   - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2548   - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2549   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2550   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2551   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2552   - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2553   - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2554   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2555   - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2556   - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2557   - env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2558   - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2559   - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2560   - env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2561   - env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2562   - env->excp_prefix = 0x00000000UL;
2563   - /* Hardware reset vector */
2564   - env->hreset_vector = 0xFFFFFFFCUL;
  3299 + env->nb_tlb = 64;
  3300 + env->nb_ways = 1;
  3301 + env->id_tlbs = 0;
2565 3302 #endif
  3303 + init_excp_BookE(env);
  3304 + env->dcache_line_size = 32;
  3305 + env->icache_line_size = 32;
  3306 + /* XXX: TODO: allocate internal IRQ controller */
2566 3307 }
2567 3308  
2568   -static void init_excp_7450 (CPUPPCState *env)
  3309 +/* PowerPC 440 GP */
  3310 +#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | PPC_STRING | \
  3311 + PPC_DCR | PPC_DCRX | \
  3312 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  3313 + PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
  3314 + PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
  3315 +#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
  3316 +#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
  3317 +#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
  3318 +#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
  3319 +#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
  3320 +#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
  3321 + POWERPC_FLAG_DE)
  3322 +#define check_pow_440GP check_pow_nocheck
  3323 +
  3324 +__attribute__ (( unused ))
  3325 +static void init_proc_440GP (CPUPPCState *env)
2569 3326 {
  3327 + /* Time base */
  3328 + gen_tbl(env);
  3329 + gen_spr_BookE(env, 0x000000000000FFFFULL);
  3330 + gen_spr_440(env);
  3331 + gen_spr_usprgh(env);
  3332 + /* Processor identification */
  3333 + spr_register(env, SPR_BOOKE_PIR, "PIR",
  3334 + SPR_NOACCESS, SPR_NOACCESS,
  3335 + &spr_read_generic, &spr_write_pir,
  3336 + 0x00000000);
  3337 + /* XXX : not implemented */
  3338 + spr_register(env, SPR_BOOKE_IAC3, "IAC3",
  3339 + SPR_NOACCESS, SPR_NOACCESS,
  3340 + &spr_read_generic, &spr_write_generic,
  3341 + 0x00000000);
  3342 + /* XXX : not implemented */
  3343 + spr_register(env, SPR_BOOKE_IAC4, "IAC4",
  3344 + SPR_NOACCESS, SPR_NOACCESS,
  3345 + &spr_read_generic, &spr_write_generic,
  3346 + 0x00000000);
  3347 + /* XXX : not implemented */
  3348 + spr_register(env, SPR_BOOKE_DVC1, "DVC1",
  3349 + SPR_NOACCESS, SPR_NOACCESS,
  3350 + &spr_read_generic, &spr_write_generic,
  3351 + 0x00000000);
  3352 + /* XXX : not implemented */
  3353 + spr_register(env, SPR_BOOKE_DVC2, "DVC2",
  3354 + SPR_NOACCESS, SPR_NOACCESS,
  3355 + &spr_read_generic, &spr_write_generic,
  3356 + 0x00000000);
  3357 + /* Memory management */
2570 3358 #if !defined(CONFIG_USER_ONLY)
2571   - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2572   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2573   - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2574   - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2575   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2576   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2577   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2578   - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2579   - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2580   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2581   - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2582   - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2583   - env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2584   - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2585   - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2586   - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2587   - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2588   - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2589   - env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2590   - env->excp_prefix = 0x00000000UL;
2591   - /* Hardware reset vector */
2592   - env->hreset_vector = 0xFFFFFFFCUL;
  3359 + env->nb_tlb = 64;
  3360 + env->nb_ways = 1;
  3361 + env->id_tlbs = 0;
2593 3362 #endif
  3363 + init_excp_BookE(env);
  3364 + env->dcache_line_size = 32;
  3365 + env->icache_line_size = 32;
  3366 + /* XXX: TODO: allocate internal IRQ controller */
2594 3367 }
2595 3368  
2596   -#if defined (TARGET_PPC64)
2597   -static void init_excp_970 (CPUPPCState *env)
  3369 +/* PowerPC 440x4 */
  3370 +#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  3371 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  3372 + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
  3373 + PPC_440_SPEC)
  3374 +#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
  3375 +#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
  3376 +#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
  3377 +#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
  3378 +#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
  3379 +#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
  3380 + POWERPC_FLAG_DE)
  3381 +#define check_pow_440x4 check_pow_nocheck
  3382 +
  3383 +__attribute__ (( unused ))
  3384 +static void init_proc_440x4 (CPUPPCState *env)
2598 3385 {
  3386 + /* Time base */
  3387 + gen_tbl(env);
  3388 + gen_spr_BookE(env, 0x000000000000FFFFULL);
  3389 + gen_spr_440(env);
  3390 + gen_spr_usprgh(env);
  3391 + /* Processor identification */
  3392 + spr_register(env, SPR_BOOKE_PIR, "PIR",
  3393 + SPR_NOACCESS, SPR_NOACCESS,
  3394 + &spr_read_generic, &spr_write_pir,
  3395 + 0x00000000);
  3396 + /* XXX : not implemented */
  3397 + spr_register(env, SPR_BOOKE_IAC3, "IAC3",
  3398 + SPR_NOACCESS, SPR_NOACCESS,
  3399 + &spr_read_generic, &spr_write_generic,
  3400 + 0x00000000);
  3401 + /* XXX : not implemented */
  3402 + spr_register(env, SPR_BOOKE_IAC4, "IAC4",
  3403 + SPR_NOACCESS, SPR_NOACCESS,
  3404 + &spr_read_generic, &spr_write_generic,
  3405 + 0x00000000);
  3406 + /* XXX : not implemented */
  3407 + spr_register(env, SPR_BOOKE_DVC1, "DVC1",
  3408 + SPR_NOACCESS, SPR_NOACCESS,
  3409 + &spr_read_generic, &spr_write_generic,
  3410 + 0x00000000);
  3411 + /* XXX : not implemented */
  3412 + spr_register(env, SPR_BOOKE_DVC2, "DVC2",
  3413 + SPR_NOACCESS, SPR_NOACCESS,
  3414 + &spr_read_generic, &spr_write_generic,
  3415 + 0x00000000);
  3416 + /* Memory management */
2599 3417 #if !defined(CONFIG_USER_ONLY)
2600   - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2601   - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2602   - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2603   - env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2604   - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2605   - env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2606   - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2607   - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2608   - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2609   - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2610   - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2611   - env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2612   - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2613   - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2614   - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2615   - env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2616   - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2617   - env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2618   - env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2619   - env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2620   - env->excp_prefix = 0x00000000FFF00000ULL;
2621   - /* Hardware reset vector */
2622   - env->hreset_vector = 0x0000000000000100ULL;
2623   -#endif
2624   -}
  3418 + env->nb_tlb = 64;
  3419 + env->nb_ways = 1;
  3420 + env->id_tlbs = 0;
2625 3421 #endif
2626   -
2627   -/*****************************************************************************/
2628   -/* Power management enable checks */
2629   -static int check_pow_none (CPUPPCState *env)
2630   -{
2631   - return 0;
  3422 + init_excp_BookE(env);
  3423 + env->dcache_line_size = 32;
  3424 + env->icache_line_size = 32;
  3425 + /* XXX: TODO: allocate internal IRQ controller */
2632 3426 }
2633 3427  
2634   -static int check_pow_nocheck (CPUPPCState *env)
2635   -{
2636   - return 1;
2637   -}
  3428 +/* PowerPC 440x5 */
  3429 +#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
  3430 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  3431 + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
  3432 + PPC_440_SPEC | PPC_RFMCI)
  3433 +#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
  3434 +#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
  3435 +#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
  3436 +#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
  3437 +#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
  3438 +#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
  3439 + POWERPC_FLAG_DE)
  3440 +#define check_pow_440x5 check_pow_nocheck
2638 3441  
2639   -static int check_pow_hid0 (CPUPPCState *env)
  3442 +__attribute__ (( unused ))
  3443 +static void init_proc_440x5 (CPUPPCState *env)
2640 3444 {
2641   - if (env->spr[SPR_HID0] & 0x00E00000)
2642   - return 1;
2643   -
2644   - return 0;
  3445 + /* Time base */
  3446 + gen_tbl(env);
  3447 + gen_spr_BookE(env, 0x000000000000FFFFULL);
  3448 + gen_spr_440(env);
  3449 + gen_spr_usprgh(env);
  3450 + /* Processor identification */
  3451 + spr_register(env, SPR_BOOKE_PIR, "PIR",
  3452 + SPR_NOACCESS, SPR_NOACCESS,
  3453 + &spr_read_generic, &spr_write_pir,
  3454 + 0x00000000);
  3455 + /* XXX : not implemented */
  3456 + spr_register(env, SPR_BOOKE_IAC3, "IAC3",
  3457 + SPR_NOACCESS, SPR_NOACCESS,
  3458 + &spr_read_generic, &spr_write_generic,
  3459 + 0x00000000);
  3460 + /* XXX : not implemented */
  3461 + spr_register(env, SPR_BOOKE_IAC4, "IAC4",
  3462 + SPR_NOACCESS, SPR_NOACCESS,
  3463 + &spr_read_generic, &spr_write_generic,
  3464 + 0x00000000);
  3465 + /* XXX : not implemented */
  3466 + spr_register(env, SPR_BOOKE_DVC1, "DVC1",
  3467 + SPR_NOACCESS, SPR_NOACCESS,
  3468 + &spr_read_generic, &spr_write_generic,
  3469 + 0x00000000);
  3470 + /* XXX : not implemented */
  3471 + spr_register(env, SPR_BOOKE_DVC2, "DVC2",
  3472 + SPR_NOACCESS, SPR_NOACCESS,
  3473 + &spr_read_generic, &spr_write_generic,
  3474 + 0x00000000);
  3475 + /* XXX : not implemented */
  3476 + spr_register(env, SPR_BOOKE_MCSR, "MCSR",
  3477 + SPR_NOACCESS, SPR_NOACCESS,
  3478 + &spr_read_generic, &spr_write_generic,
  3479 + 0x00000000);
  3480 + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  3481 + SPR_NOACCESS, SPR_NOACCESS,
  3482 + &spr_read_generic, &spr_write_generic,
  3483 + 0x00000000);
  3484 + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  3485 + SPR_NOACCESS, SPR_NOACCESS,
  3486 + &spr_read_generic, &spr_write_generic,
  3487 + 0x00000000);
  3488 + /* XXX : not implemented */
  3489 + spr_register(env, SPR_440_CCR1, "CCR1",
  3490 + SPR_NOACCESS, SPR_NOACCESS,
  3491 + &spr_read_generic, &spr_write_generic,
  3492 + 0x00000000);
  3493 + /* Memory management */
  3494 +#if !defined(CONFIG_USER_ONLY)
  3495 + env->nb_tlb = 64;
  3496 + env->nb_ways = 1;
  3497 + env->id_tlbs = 0;
  3498 +#endif
  3499 + init_excp_BookE(env);
  3500 + env->dcache_line_size = 32;
  3501 + env->icache_line_size = 32;
  3502 + /* XXX: TODO: allocate internal IRQ controller */
2645 3503 }
2646 3504  
2647   -/*****************************************************************************/
2648   -/* PowerPC implementations definitions */
2649   -
2650   -/* PowerPC 40x instruction set */
2651   -#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_WRTEE | \
2652   - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)
2653   -
2654   -/* PowerPC 401 */
2655   -#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2656   - PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2657   - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2658   -#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2659   -#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
2660   -#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2661   -#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2662   -#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2663   -#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2664   -#define check_pow_401 check_pow_nocheck
  3505 +/* PowerPC 460 (guessed) */
  3506 +#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | PPC_STRING | \
  3507 + PPC_DCR | PPC_DCRX | PPC_DCRUX | \
  3508 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  3509 + PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
  3510 + PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
  3511 +#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
  3512 +#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
  3513 +#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
  3514 +#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
  3515 +#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
  3516 +#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
  3517 + POWERPC_FLAG_DE)
  3518 +#define check_pow_460 check_pow_nocheck
2665 3519  
2666   -static void init_proc_401 (CPUPPCState *env)
  3520 +__attribute__ (( unused ))
  3521 +static void init_proc_460 (CPUPPCState *env)
2667 3522 {
2668   - gen_spr_40x(env);
2669   - gen_spr_401_403(env);
2670   - gen_spr_401(env);
2671   - init_excp_4xx_real(env);
  3523 + /* Time base */
  3524 + gen_tbl(env);
  3525 + gen_spr_BookE(env, 0x000000000000FFFFULL);
  3526 + gen_spr_440(env);
  3527 + gen_spr_usprgh(env);
  3528 + /* Processor identification */
  3529 + spr_register(env, SPR_BOOKE_PIR, "PIR",
  3530 + SPR_NOACCESS, SPR_NOACCESS,
  3531 + &spr_read_generic, &spr_write_pir,
  3532 + 0x00000000);
  3533 + /* XXX : not implemented */
  3534 + spr_register(env, SPR_BOOKE_IAC3, "IAC3",
  3535 + SPR_NOACCESS, SPR_NOACCESS,
  3536 + &spr_read_generic, &spr_write_generic,
  3537 + 0x00000000);
  3538 + /* XXX : not implemented */
  3539 + spr_register(env, SPR_BOOKE_IAC4, "IAC4",
  3540 + SPR_NOACCESS, SPR_NOACCESS,
  3541 + &spr_read_generic, &spr_write_generic,
  3542 + 0x00000000);
  3543 + /* XXX : not implemented */
  3544 + spr_register(env, SPR_BOOKE_DVC1, "DVC1",
  3545 + SPR_NOACCESS, SPR_NOACCESS,
  3546 + &spr_read_generic, &spr_write_generic,
  3547 + 0x00000000);
  3548 + /* XXX : not implemented */
  3549 + spr_register(env, SPR_BOOKE_DVC2, "DVC2",
  3550 + SPR_NOACCESS, SPR_NOACCESS,
  3551 + &spr_read_generic, &spr_write_generic,
  3552 + 0x00000000);
  3553 + /* XXX : not implemented */
  3554 + spr_register(env, SPR_BOOKE_MCSR, "MCSR",
  3555 + SPR_NOACCESS, SPR_NOACCESS,
  3556 + &spr_read_generic, &spr_write_generic,
  3557 + 0x00000000);
  3558 + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  3559 + SPR_NOACCESS, SPR_NOACCESS,
  3560 + &spr_read_generic, &spr_write_generic,
  3561 + 0x00000000);
  3562 + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  3563 + SPR_NOACCESS, SPR_NOACCESS,
  3564 + &spr_read_generic, &spr_write_generic,
  3565 + 0x00000000);
  3566 + /* XXX : not implemented */
  3567 + spr_register(env, SPR_440_CCR1, "CCR1",
  3568 + SPR_NOACCESS, SPR_NOACCESS,
  3569 + &spr_read_generic, &spr_write_generic,
  3570 + 0x00000000);
  3571 + /* XXX : not implemented */
  3572 + spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
  3573 + &spr_read_generic, &spr_write_generic,
  3574 + &spr_read_generic, &spr_write_generic,
  3575 + 0x00000000);
  3576 + /* Memory management */
  3577 +#if !defined(CONFIG_USER_ONLY)
  3578 + env->nb_tlb = 64;
  3579 + env->nb_ways = 1;
  3580 + env->id_tlbs = 0;
  3581 +#endif
  3582 + init_excp_BookE(env);
2672 3583 env->dcache_line_size = 32;
2673 3584 env->icache_line_size = 32;
2674   - /* Allocate hardware IRQ controller */
2675   - ppc40x_irq_init(env);
  3585 + /* XXX: TODO: allocate internal IRQ controller */
2676 3586 }
2677 3587  
2678   -/* PowerPC 401x2 */
2679   -#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2680   - PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2681   - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2682   - PPC_CACHE_DCBA | PPC_MFTB | \
2683   - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2684   -#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2685   -#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2686   -#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2687   -#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2688   -#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2689   -#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2690   -#define check_pow_401x2 check_pow_nocheck
  3588 +/* PowerPC 460F (guessed) */
  3589 +#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | PPC_STRING | \
  3590 + PPC_DCR | PPC_DCRX | PPC_DCRUX | \
  3591 + PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
  3592 + PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
  3593 + PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
  3594 + PPC_FLOAT_STFIWX | \
  3595 + PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
  3596 + PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
  3597 +#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
  3598 +#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
  3599 +#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
  3600 +#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
  3601 +#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
  3602 +#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
  3603 + POWERPC_FLAG_DE)
  3604 +#define check_pow_460F check_pow_nocheck
2691 3605  
2692   -static void init_proc_401x2 (CPUPPCState *env)
  3606 +__attribute__ (( unused ))
  3607 +static void init_proc_460F (CPUPPCState *env)
2693 3608 {
2694   - gen_spr_40x(env);
2695   - gen_spr_401_403(env);
2696   - gen_spr_401x2(env);
2697   - gen_spr_compress(env);
  3609 + /* Time base */
  3610 + gen_tbl(env);
  3611 + gen_spr_BookE(env, 0x000000000000FFFFULL);
  3612 + gen_spr_440(env);
  3613 + gen_spr_usprgh(env);
  3614 + /* Processor identification */
  3615 + spr_register(env, SPR_BOOKE_PIR, "PIR",
  3616 + SPR_NOACCESS, SPR_NOACCESS,
  3617 + &spr_read_generic, &spr_write_pir,
  3618 + 0x00000000);
  3619 + /* XXX : not implemented */
  3620 + spr_register(env, SPR_BOOKE_IAC3, "IAC3",
  3621 + SPR_NOACCESS, SPR_NOACCESS,
  3622 + &spr_read_generic, &spr_write_generic,
  3623 + 0x00000000);
  3624 + /* XXX : not implemented */
  3625 + spr_register(env, SPR_BOOKE_IAC4, "IAC4",
  3626 + SPR_NOACCESS, SPR_NOACCESS,
  3627 + &spr_read_generic, &spr_write_generic,
  3628 + 0x00000000);
  3629 + /* XXX : not implemented */
  3630 + spr_register(env, SPR_BOOKE_DVC1, "DVC1",
  3631 + SPR_NOACCESS, SPR_NOACCESS,
  3632 + &spr_read_generic, &spr_write_generic,
  3633 + 0x00000000);
  3634 + /* XXX : not implemented */
  3635 + spr_register(env, SPR_BOOKE_DVC2, "DVC2",
  3636 + SPR_NOACCESS, SPR_NOACCESS,
  3637 + &spr_read_generic, &spr_write_generic,
  3638 + 0x00000000);
  3639 + /* XXX : not implemented */
  3640 + spr_register(env, SPR_BOOKE_MCSR, "MCSR",
  3641 + SPR_NOACCESS, SPR_NOACCESS,
  3642 + &spr_read_generic, &spr_write_generic,
  3643 + 0x00000000);
  3644 + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  3645 + SPR_NOACCESS, SPR_NOACCESS,
  3646 + &spr_read_generic, &spr_write_generic,
  3647 + 0x00000000);
  3648 + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  3649 + SPR_NOACCESS, SPR_NOACCESS,
  3650 + &spr_read_generic, &spr_write_generic,
  3651 + 0x00000000);
  3652 + /* XXX : not implemented */
  3653 + spr_register(env, SPR_440_CCR1, "CCR1",
  3654 + SPR_NOACCESS, SPR_NOACCESS,
  3655 + &spr_read_generic, &spr_write_generic,
  3656 + 0x00000000);
  3657 + /* XXX : not implemented */
  3658 + spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
  3659 + &spr_read_generic, &spr_write_generic,
  3660 + &spr_read_generic, &spr_write_generic,
  3661 + 0x00000000);
2698 3662 /* Memory management */
2699 3663 #if !defined(CONFIG_USER_ONLY)
2700 3664 env->nb_tlb = 64;
2701 3665 env->nb_ways = 1;
2702 3666 env->id_tlbs = 0;
2703 3667 #endif
2704   - init_excp_4xx_softmmu(env);
  3668 + init_excp_BookE(env);
2705 3669 env->dcache_line_size = 32;
2706 3670 env->icache_line_size = 32;
2707   - /* Allocate hardware IRQ controller */
2708   - ppc40x_irq_init(env);
  3671 + /* XXX: TODO: allocate internal IRQ controller */
2709 3672 }
2710 3673  
2711   -/* PowerPC 401x3 */
2712   -#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2713   - PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2714   - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2715   - PPC_CACHE_DCBA | PPC_MFTB | \
2716   - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2717   -#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2718   -#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2719   -#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2720   -#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2721   -#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2722   -#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2723   -#define check_pow_401x3 check_pow_nocheck
  3674 +/* Freescale 5xx cores (aka RCPU) */
  3675 +#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
  3676 + PPC_MEM_EIEIO | PPC_MEM_SYNC | \
  3677 + PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
  3678 + PPC_MFTB)
  3679 +#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
  3680 +#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
  3681 +#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
  3682 +#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
  3683 +#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
  3684 +#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
  3685 +#define check_pow_MPC5xx check_pow_none
2724 3686  
2725 3687 __attribute__ (( unused ))
2726   -static void init_proc_401x3 (CPUPPCState *env)
  3688 +static void init_proc_MPC5xx (CPUPPCState *env)
2727 3689 {
2728   - gen_spr_40x(env);
2729   - gen_spr_401_403(env);
2730   - gen_spr_401(env);
2731   - gen_spr_401x2(env);
2732   - gen_spr_compress(env);
2733   - init_excp_4xx_softmmu(env);
  3690 + /* Time base */
  3691 + gen_tbl(env);
  3692 + gen_spr_5xx_8xx(env);
  3693 + gen_spr_5xx(env);
  3694 + init_excp_MPC5xx(env);
2734 3695 env->dcache_line_size = 32;
2735 3696 env->icache_line_size = 32;
2736   - /* Allocate hardware IRQ controller */
2737   - ppc40x_irq_init(env);
  3697 + /* XXX: TODO: allocate internal IRQ controller */
2738 3698 }
2739 3699  
2740   -/* IOP480 */
2741   -#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2742   - PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2743   - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2744   - PPC_CACHE_DCBA | \
2745   - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2746   -#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2747   -#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2748   -#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2749   -#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2750   -#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2751   -#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2752   -#define check_pow_IOP480 check_pow_nocheck
  3700 +/* Freescale 8xx cores (aka PowerQUICC) */
  3701 +#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
  3702 + PPC_MEM_EIEIO | PPC_MEM_SYNC | \
  3703 + PPC_CACHE_ICBI | PPC_MFTB)
  3704 +#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
  3705 +#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
  3706 +#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
  3707 +#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
  3708 +#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
  3709 +#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
  3710 +#define check_pow_MPC8xx check_pow_none
2753 3711  
2754   -static void init_proc_IOP480 (CPUPPCState *env)
  3712 +__attribute__ (( unused ))
  3713 +static void init_proc_MPC8xx (CPUPPCState *env)
2755 3714 {
2756   - gen_spr_40x(env);
2757   - gen_spr_401_403(env);
2758   - gen_spr_401x2(env);
2759   - gen_spr_compress(env);
2760   - /* Memory management */
2761   -#if !defined(CONFIG_USER_ONLY)
2762   - env->nb_tlb = 64;
2763   - env->nb_ways = 1;
2764   - env->id_tlbs = 0;
2765   -#endif
2766   - init_excp_4xx_softmmu(env);
  3715 + /* Time base */
  3716 + gen_tbl(env);
  3717 + gen_spr_5xx_8xx(env);
  3718 + gen_spr_8xx(env);
  3719 + init_excp_MPC8xx(env);
2767 3720 env->dcache_line_size = 32;
2768 3721 env->icache_line_size = 32;
2769   - /* Allocate hardware IRQ controller */
2770   - ppc40x_irq_init(env);
  3722 + /* XXX: TODO: allocate internal IRQ controller */
2771 3723 }
2772 3724  
2773   -/* PowerPC 403 */
2774   -#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2775   - PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2776   - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2777   -#define POWERPC_MSRM_403 (0x000000000007D00DULL)
2778   -#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
2779   -#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2780   -#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2781   -#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2782   -#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2783   -#define check_pow_403 check_pow_nocheck
  3725 +/* Freescale 82xx cores (aka PowerQUICC-II) */
  3726 +/* PowerPC G2 */
  3727 +#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
  3728 +#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
  3729 +#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
  3730 +//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
  3731 +#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
  3732 +#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
  3733 +#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
  3734 + POWERPC_FLAG_BE)
  3735 +#define check_pow_G2 check_pow_hid0
2784 3736  
2785   -static void init_proc_403 (CPUPPCState *env)
  3737 +static void init_proc_G2 (CPUPPCState *env)
2786 3738 {
2787   - gen_spr_40x(env);
2788   - gen_spr_401_403(env);
2789   - gen_spr_403(env);
2790   - gen_spr_403_real(env);
2791   - init_excp_4xx_real(env);
  3739 + gen_spr_ne_601(env);
  3740 + gen_spr_G2_755(env);
  3741 + gen_spr_G2(env);
  3742 + /* Time base */
  3743 + gen_tbl(env);
  3744 + /* Hardware implementation register */
  3745 + /* XXX : not implemented */
  3746 + spr_register(env, SPR_HID0, "HID0",
  3747 + SPR_NOACCESS, SPR_NOACCESS,
  3748 + &spr_read_generic, &spr_write_generic,
  3749 + 0x00000000);
  3750 + /* XXX : not implemented */
  3751 + spr_register(env, SPR_HID1, "HID1",
  3752 + SPR_NOACCESS, SPR_NOACCESS,
  3753 + &spr_read_generic, &spr_write_generic,
  3754 + 0x00000000);
  3755 + /* XXX : not implemented */
  3756 + spr_register(env, SPR_HID2, "HID2",
  3757 + SPR_NOACCESS, SPR_NOACCESS,
  3758 + &spr_read_generic, &spr_write_generic,
  3759 + 0x00000000);
  3760 + /* Memory management */
  3761 + gen_low_BATs(env);
  3762 + gen_high_BATs(env);
  3763 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  3764 + init_excp_G2(env);
2792 3765 env->dcache_line_size = 32;
2793 3766 env->icache_line_size = 32;
2794 3767 /* Allocate hardware IRQ controller */
2795   - ppc40x_irq_init(env);
2796   -#if !defined(CONFIG_USER_ONLY)
2797   - /* Hardware reset vector */
2798   - env->hreset_vector = 0xFFFFFFFCUL;
2799   -#endif
  3768 + ppc6xx_irq_init(env);
2800 3769 }
2801 3770  
2802   -/* PowerPC 403 GCX */
2803   -#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2804   - PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2805   - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2806   - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2807   -#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2808   -#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2809   -#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2810   -#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2811   -#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2812   -#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2813   -#define check_pow_403GCX check_pow_nocheck
  3771 +/* PowerPC G2LE */
  3772 +#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
  3773 +#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
  3774 +#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
  3775 +#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
  3776 +#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
  3777 +#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
  3778 +#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
  3779 + POWERPC_FLAG_BE)
  3780 +#define check_pow_G2LE check_pow_hid0
2814 3781  
2815   -static void init_proc_403GCX (CPUPPCState *env)
  3782 +static void init_proc_G2LE (CPUPPCState *env)
2816 3783 {
2817   - gen_spr_40x(env);
2818   - gen_spr_401_403(env);
2819   - gen_spr_403(env);
2820   - gen_spr_403_real(env);
2821   - gen_spr_403_mmu(env);
2822   - /* Bus access control */
2823   - /* not emulated, as Qemu never does speculative access */
2824   - spr_register(env, SPR_40x_SGR, "SGR",
  3784 + gen_spr_ne_601(env);
  3785 + gen_spr_G2_755(env);
  3786 + gen_spr_G2(env);
  3787 + /* Time base */
  3788 + gen_tbl(env);
  3789 + /* Hardware implementation register */
  3790 + /* XXX : not implemented */
  3791 + spr_register(env, SPR_HID0, "HID0",
2825 3792 SPR_NOACCESS, SPR_NOACCESS,
2826 3793 &spr_read_generic, &spr_write_generic,
2827   - 0xFFFFFFFF);
2828   - /* not emulated, as Qemu do not emulate caches */
2829   - spr_register(env, SPR_40x_DCWR, "DCWR",
  3794 + 0x00000000);
  3795 + /* XXX : not implemented */
  3796 + spr_register(env, SPR_HID1, "HID1",
  3797 + SPR_NOACCESS, SPR_NOACCESS,
  3798 + &spr_read_generic, &spr_write_generic,
  3799 + 0x00000000);
  3800 + /* XXX : not implemented */
  3801 + spr_register(env, SPR_HID2, "HID2",
2830 3802 SPR_NOACCESS, SPR_NOACCESS,
2831 3803 &spr_read_generic, &spr_write_generic,
2832 3804 0x00000000);
2833 3805 /* Memory management */
2834   -#if !defined(CONFIG_USER_ONLY)
2835   - env->nb_tlb = 64;
2836   - env->nb_ways = 1;
2837   - env->id_tlbs = 0;
2838   -#endif
2839   - init_excp_4xx_softmmu(env);
  3806 + gen_low_BATs(env);
  3807 + gen_high_BATs(env);
  3808 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  3809 + init_excp_G2(env);
2840 3810 env->dcache_line_size = 32;
2841 3811 env->icache_line_size = 32;
2842 3812 /* Allocate hardware IRQ controller */
2843   - ppc40x_irq_init(env);
  3813 + ppc6xx_irq_init(env);
2844 3814 }
2845 3815  
2846   -/* PowerPC 405 */
2847   -#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2848   - PPC_MFTB | \
2849   - PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2850   - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2851   - PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2852   - PPC_405_MAC)
2853   -#define POWERPC_MSRM_405 (0x000000000006E630ULL)
2854   -#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2855   -#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2856   -#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2857   -#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2858   -#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2859   - POWERPC_FLAG_DE)
2860   -#define check_pow_405 check_pow_nocheck
  3816 +/* e200 core */
  3817 +/* XXX: unimplemented instructions:
  3818 + * dcblc
  3819 + * dcbtlst
  3820 + * dcbtstls
  3821 + * icblc
  3822 + * icbtls
  3823 + * tlbivax
  3824 + * all SPE multiply-accumulate instructions
  3825 + */
  3826 +#define POWERPC_INSNS_e200 (POWERPC_INSNS_EMB | PPC_ISEL | \
  3827 + PPC_SPE | PPC_SPEFPU | \
  3828 + PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
  3829 + PPC_CACHE_DCBA | PPC_CACHE_LOCK | \
  3830 + PPC_BOOKE | PPC_RFDI)
  3831 +#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
  3832 +#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
  3833 +#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
  3834 +#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
  3835 +#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
  3836 +#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
  3837 + POWERPC_FLAG_UBLE | POWERPC_FLAG_DE)
  3838 +#define check_pow_e200 check_pow_hid0
2861 3839  
2862   -static void init_proc_405 (CPUPPCState *env)
  3840 +
  3841 +__attribute__ (( unused ))
  3842 +static void init_proc_e200 (CPUPPCState *env)
2863 3843 {
2864 3844 /* Time base */
2865 3845 gen_tbl(env);
2866   - gen_spr_40x(env);
2867   - gen_spr_405(env);
2868   - /* Bus access control */
2869   - /* not emulated, as Qemu never does speculative access */
2870   - spr_register(env, SPR_40x_SGR, "SGR",
  3846 + gen_spr_BookE(env, 0x000000070000FFFFULL);
  3847 + /* XXX : not implemented */
  3848 + spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
  3849 + SPR_NOACCESS, SPR_NOACCESS,
  3850 + &spr_read_generic, &spr_write_generic,
  3851 + 0x00000000);
  3852 + /* Memory management */
  3853 + gen_spr_BookE_FSL(env, 0x0000005D);
  3854 + /* XXX : not implemented */
  3855 + spr_register(env, SPR_HID0, "HID0",
  3856 + SPR_NOACCESS, SPR_NOACCESS,
  3857 + &spr_read_generic, &spr_write_generic,
  3858 + 0x00000000);
  3859 + /* XXX : not implemented */
  3860 + spr_register(env, SPR_HID1, "HID1",
  3861 + SPR_NOACCESS, SPR_NOACCESS,
  3862 + &spr_read_generic, &spr_write_generic,
  3863 + 0x00000000);
  3864 + /* XXX : not implemented */
  3865 + spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
  3866 + SPR_NOACCESS, SPR_NOACCESS,
  3867 + &spr_read_generic, &spr_write_generic,
  3868 + 0x00000000);
  3869 + /* XXX : not implemented */
  3870 + spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
  3871 + SPR_NOACCESS, SPR_NOACCESS,
  3872 + &spr_read_generic, &spr_write_generic,
  3873 + 0x00000000);
  3874 + /* XXX : not implemented */
  3875 + spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2871 3876 SPR_NOACCESS, SPR_NOACCESS,
2872 3877 &spr_read_generic, &spr_write_generic,
2873   - 0xFFFFFFFF);
2874   - /* not emulated, as Qemu do not emulate caches */
2875   - spr_register(env, SPR_40x_DCWR, "DCWR",
  3878 + 0x00000000);
  3879 + /* XXX : not implemented */
  3880 + spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2876 3881 SPR_NOACCESS, SPR_NOACCESS,
2877 3882 &spr_read_generic, &spr_write_generic,
2878 3883 0x00000000);
2879   - /* Memory management */
2880   -#if !defined(CONFIG_USER_ONLY)
2881   - env->nb_tlb = 64;
2882   - env->nb_ways = 1;
2883   - env->id_tlbs = 0;
2884   -#endif
2885   - init_excp_4xx_softmmu(env);
2886   - env->dcache_line_size = 32;
2887   - env->icache_line_size = 32;
2888   - /* Allocate hardware IRQ controller */
2889   - ppc40x_irq_init(env);
2890   -}
2891   -
2892   -/* PowerPC 440 EP */
2893   -#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2894   - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2895   - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2896   - PPC_440_SPEC | PPC_RFMCI)
2897   -#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2898   -#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2899   -#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2900   -#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2901   -#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2902   -#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2903   - POWERPC_FLAG_DE)
2904   -#define check_pow_440EP check_pow_nocheck
2905   -
2906   -static void init_proc_440EP (CPUPPCState *env)
2907   -{
2908   - /* Time base */
2909   - gen_tbl(env);
2910   - gen_spr_BookE(env);
2911   - gen_spr_440(env);
2912 3884 /* XXX : not implemented */
2913   - spr_register(env, SPR_BOOKE_MCSR, "MCSR",
  3885 + spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
2914 3886 SPR_NOACCESS, SPR_NOACCESS,
2915 3887 &spr_read_generic, &spr_write_generic,
2916 3888 0x00000000);
2917   - spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  3889 + /* XXX : not implemented */
  3890 + spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2918 3891 SPR_NOACCESS, SPR_NOACCESS,
2919 3892 &spr_read_generic, &spr_write_generic,
2920 3893 0x00000000);
2921   - spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  3894 + /* XXX : not implemented */
  3895 + spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2922 3896 SPR_NOACCESS, SPR_NOACCESS,
2923 3897 &spr_read_generic, &spr_write_generic,
2924 3898 0x00000000);
2925 3899 /* XXX : not implemented */
2926   - spr_register(env, SPR_440_CCR1, "CCR1",
  3900 + spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
  3901 + SPR_NOACCESS, SPR_NOACCESS,
  3902 + &spr_read_generic, &spr_write_generic,
  3903 + 0x00000000);
  3904 + /* XXX : not implemented */
  3905 + spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
  3906 + SPR_NOACCESS, SPR_NOACCESS,
  3907 + &spr_read_generic, &spr_write_generic,
  3908 + 0x00000000);
  3909 + /* XXX : not implemented */
  3910 + spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
  3911 + SPR_NOACCESS, SPR_NOACCESS,
  3912 + &spr_read_generic, &spr_write_generic,
  3913 + 0x00000000);
  3914 + /* XXX : not implemented */
  3915 + spr_register(env, SPR_BOOKE_IAC3, "IAC3",
  3916 + SPR_NOACCESS, SPR_NOACCESS,
  3917 + &spr_read_generic, &spr_write_generic,
  3918 + 0x00000000);
  3919 + /* XXX : not implemented */
  3920 + spr_register(env, SPR_BOOKE_IAC4, "IAC4",
  3921 + SPR_NOACCESS, SPR_NOACCESS,
  3922 + &spr_read_generic, &spr_write_generic,
  3923 + 0x00000000);
  3924 + spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
  3925 + SPR_NOACCESS, SPR_NOACCESS,
  3926 + &spr_read_generic, &spr_write_generic,
  3927 + 0x00000000);
  3928 + spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
2927 3929 SPR_NOACCESS, SPR_NOACCESS,
2928 3930 &spr_read_generic, &spr_write_generic,
2929 3931 0x00000000);
2930   - /* Memory management */
2931   -#if !defined(CONFIG_USER_ONLY)
2932   - env->nb_tlb = 64;
2933   - env->nb_ways = 1;
2934   - env->id_tlbs = 0;
2935   -#endif
2936   - init_excp_BookE(env);
2937   - env->dcache_line_size = 32;
2938   - env->icache_line_size = 32;
2939   - /* XXX: TODO: allocate internal IRQ controller */
2940   -}
2941   -
2942   -/* PowerPC 440 GP */
2943   -#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | PPC_STRING | \
2944   - PPC_DCR | PPC_DCRX | \
2945   - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2946   - PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
2947   - PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
2948   -#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2949   -#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2950   -#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2951   -#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2952   -#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2953   -#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2954   - POWERPC_FLAG_DE)
2955   -#define check_pow_440GP check_pow_nocheck
2956   -
2957   -static void init_proc_440GP (CPUPPCState *env)
2958   -{
2959   - /* Time base */
2960   - gen_tbl(env);
2961   - gen_spr_BookE(env);
2962   - gen_spr_440(env);
2963   - /* Memory management */
2964 3932 #if !defined(CONFIG_USER_ONLY)
2965 3933 env->nb_tlb = 64;
2966 3934 env->nb_ways = 1;
2967 3935 env->id_tlbs = 0;
2968 3936 #endif
2969   - init_excp_BookE(env);
  3937 + init_excp_e200(env);
2970 3938 env->dcache_line_size = 32;
2971 3939 env->icache_line_size = 32;
2972 3940 /* XXX: TODO: allocate internal IRQ controller */
2973 3941 }
2974 3942  
2975   -/* PowerPC 440x4 */
2976   -#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
2977   - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2978   - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2979   - PPC_440_SPEC)
2980   -#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2981   -#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2982   -#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2983   -#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2984   -#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2985   -#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2986   - POWERPC_FLAG_DE)
2987   -#define check_pow_440x4 check_pow_nocheck
  3943 +/* e300 core */
  3944 +#define POWERPC_INSNS_e300 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
  3945 +#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
  3946 +#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
  3947 +#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
  3948 +#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
  3949 +#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
  3950 +#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
  3951 + POWERPC_FLAG_BE)
  3952 +#define check_pow_e300 check_pow_hid0
2988 3953  
2989 3954 __attribute__ (( unused ))
2990   -static void init_proc_440x4 (CPUPPCState *env)
2991   -{
2992   - /* Time base */
2993   - gen_tbl(env);
2994   - gen_spr_BookE(env);
2995   - gen_spr_440(env);
2996   - /* Memory management */
2997   -#if !defined(CONFIG_USER_ONLY)
2998   - env->nb_tlb = 64;
2999   - env->nb_ways = 1;
3000   - env->id_tlbs = 0;
3001   -#endif
3002   - init_excp_BookE(env);
3003   - env->dcache_line_size = 32;
3004   - env->icache_line_size = 32;
3005   - /* XXX: TODO: allocate internal IRQ controller */
3006   -}
3007   -
3008   -/* PowerPC 440x5 */
3009   -#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
3010   - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3011   - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3012   - PPC_440_SPEC | PPC_RFMCI)
3013   -#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3014   -#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3015   -#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3016   -#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3017   -#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3018   -#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3019   - POWERPC_FLAG_DE)
3020   -#define check_pow_440x5 check_pow_nocheck
3021   -
3022   -static void init_proc_440x5 (CPUPPCState *env)
  3955 +static void init_proc_e300 (CPUPPCState *env)
3023 3956 {
  3957 + gen_spr_ne_601(env);
  3958 + gen_spr_603(env);
3024 3959 /* Time base */
3025 3960 gen_tbl(env);
3026   - gen_spr_BookE(env);
3027   - gen_spr_440(env);
  3961 + /* hardware implementation registers */
3028 3962 /* XXX : not implemented */
3029   - spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3030   - SPR_NOACCESS, SPR_NOACCESS,
3031   - &spr_read_generic, &spr_write_generic,
3032   - 0x00000000);
3033   - spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3034   - SPR_NOACCESS, SPR_NOACCESS,
3035   - &spr_read_generic, &spr_write_generic,
3036   - 0x00000000);
3037   - spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  3963 + spr_register(env, SPR_HID0, "HID0",
3038 3964 SPR_NOACCESS, SPR_NOACCESS,
3039 3965 &spr_read_generic, &spr_write_generic,
3040 3966 0x00000000);
3041 3967 /* XXX : not implemented */
3042   - spr_register(env, SPR_440_CCR1, "CCR1",
  3968 + spr_register(env, SPR_HID1, "HID1",
3043 3969 SPR_NOACCESS, SPR_NOACCESS,
3044 3970 &spr_read_generic, &spr_write_generic,
3045 3971 0x00000000);
3046 3972 /* Memory management */
3047   -#if !defined(CONFIG_USER_ONLY)
3048   - env->nb_tlb = 64;
3049   - env->nb_ways = 1;
3050   - env->id_tlbs = 0;
3051   -#endif
3052   - init_excp_BookE(env);
  3973 + gen_low_BATs(env);
  3974 + gen_6xx_7xx_soft_tlb(env, 64, 2);
  3975 + init_excp_603(env);
3053 3976 env->dcache_line_size = 32;
3054 3977 env->icache_line_size = 32;
3055   - /* XXX: TODO: allocate internal IRQ controller */
  3978 + /* Allocate hardware IRQ controller */
  3979 + ppc6xx_irq_init(env);
3056 3980 }
3057 3981  
3058   -/* PowerPC 460 (guessed) */
3059   -#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | PPC_STRING | \
3060   - PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3061   - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3062   - PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
3063   - PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
3064   -#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3065   -#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3066   -#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3067   -#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3068   -#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3069   -#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3070   - POWERPC_FLAG_DE)
3071   -#define check_pow_460 check_pow_nocheck
  3982 +/* e500 core */
  3983 +#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | PPC_ISEL | \
  3984 + PPC_SPE | PPC_SPEFPU | \
  3985 + PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
  3986 + PPC_CACHE_DCBA | PPC_CACHE_LOCK | \
  3987 + PPC_BOOKE | PPC_RFDI)
  3988 +#define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
  3989 +#define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
  3990 +#define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE)
  3991 +#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
  3992 +#define POWERPC_BFDM_e500 (bfd_mach_ppc_860)
  3993 +#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
  3994 + POWERPC_FLAG_UBLE | POWERPC_FLAG_DE)
  3995 +#define check_pow_e500 check_pow_hid0
3072 3996  
3073 3997 __attribute__ (( unused ))
3074   -static void init_proc_460 (CPUPPCState *env)
  3998 +static void init_proc_e500 (CPUPPCState *env)
3075 3999 {
3076 4000 /* Time base */
3077 4001 gen_tbl(env);
3078   - gen_spr_BookE(env);
3079   - gen_spr_440(env);
  4002 + gen_spr_BookE(env, 0x0000000F0000FD7FULL);
  4003 + /* Processor identification */
  4004 + spr_register(env, SPR_BOOKE_PIR, "PIR",
  4005 + SPR_NOACCESS, SPR_NOACCESS,
  4006 + &spr_read_generic, &spr_write_pir,
  4007 + 0x00000000);
3080 4008 /* XXX : not implemented */
3081   - spr_register(env, SPR_BOOKE_MCSR, "MCSR",
  4009 + spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3082 4010 SPR_NOACCESS, SPR_NOACCESS,
3083 4011 &spr_read_generic, &spr_write_generic,
3084 4012 0x00000000);
3085   - spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  4013 + /* Memory management */
  4014 +#if !defined(CONFIG_USER_ONLY)
  4015 + env->nb_pids = 3;
  4016 +#endif
  4017 + gen_spr_BookE_FSL(env, 0x0000005F);
  4018 + /* XXX : not implemented */
  4019 + spr_register(env, SPR_HID0, "HID0",
3086 4020 SPR_NOACCESS, SPR_NOACCESS,
3087 4021 &spr_read_generic, &spr_write_generic,
3088 4022 0x00000000);
3089   - spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  4023 + /* XXX : not implemented */
  4024 + spr_register(env, SPR_HID1, "HID1",
3090 4025 SPR_NOACCESS, SPR_NOACCESS,
3091 4026 &spr_read_generic, &spr_write_generic,
3092 4027 0x00000000);
3093 4028 /* XXX : not implemented */
3094   - spr_register(env, SPR_440_CCR1, "CCR1",
  4029 + spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
3095 4030 SPR_NOACCESS, SPR_NOACCESS,
3096 4031 &spr_read_generic, &spr_write_generic,
3097 4032 0x00000000);
3098 4033 /* XXX : not implemented */
3099   - spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3100   - &spr_read_generic, &spr_write_generic,
  4034 + spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
  4035 + SPR_NOACCESS, SPR_NOACCESS,
3101 4036 &spr_read_generic, &spr_write_generic,
3102   - 0x00000000);
3103   - /* Memory management */
3104   -#if !defined(CONFIG_USER_ONLY)
3105   - env->nb_tlb = 64;
3106   - env->nb_ways = 1;
3107   - env->id_tlbs = 0;
3108   -#endif
3109   - init_excp_BookE(env);
3110   - env->dcache_line_size = 32;
3111   - env->icache_line_size = 32;
3112   - /* XXX: TODO: allocate internal IRQ controller */
3113   -}
3114   -
3115   -/* PowerPC 460F (guessed) */
3116   -#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | PPC_STRING | \
3117   - PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3118   - PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3119   - PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3120   - PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3121   - PPC_FLOAT_STFIWX | \
3122   - PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
3123   - PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
3124   -#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3125   -#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3126   -#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3127   -#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3128   -#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3129   -#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3130   - POWERPC_FLAG_DE)
3131   -#define check_pow_460F check_pow_nocheck
3132   -
3133   -__attribute__ (( unused ))
3134   -static void init_proc_460F (CPUPPCState *env)
3135   -{
3136   - /* Time base */
3137   - gen_tbl(env);
3138   - gen_spr_BookE(env);
3139   - gen_spr_440(env);
  4037 + 0x00000000);
  4038 + /* XXX : not implemented */
  4039 + spr_register(env, SPR_Exxx_MCAR, "MCAR",
  4040 + SPR_NOACCESS, SPR_NOACCESS,
  4041 + &spr_read_generic, &spr_write_generic,
  4042 + 0x00000000);
3140 4043 /* XXX : not implemented */
3141 4044 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3142 4045 SPR_NOACCESS, SPR_NOACCESS,
3143 4046 &spr_read_generic, &spr_write_generic,
3144 4047 0x00000000);
3145   - spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  4048 + /* XXX : not implemented */
  4049 + spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
3146 4050 SPR_NOACCESS, SPR_NOACCESS,
3147 4051 &spr_read_generic, &spr_write_generic,
3148 4052 0x00000000);
3149   - spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  4053 + /* XXX : not implemented */
  4054 + spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3150 4055 SPR_NOACCESS, SPR_NOACCESS,
3151 4056 &spr_read_generic, &spr_write_generic,
3152 4057 0x00000000);
3153 4058 /* XXX : not implemented */
3154   - spr_register(env, SPR_440_CCR1, "CCR1",
  4059 + spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3155 4060 SPR_NOACCESS, SPR_NOACCESS,
3156 4061 &spr_read_generic, &spr_write_generic,
3157 4062 0x00000000);
3158 4063 /* XXX : not implemented */
3159   - spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
  4064 + spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
  4065 + SPR_NOACCESS, SPR_NOACCESS,
3160 4066 &spr_read_generic, &spr_write_generic,
  4067 + 0x00000000);
  4068 + /* XXX : not implemented */
  4069 + spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
  4070 + SPR_NOACCESS, SPR_NOACCESS,
  4071 + &spr_read_generic, &spr_write_generic,
  4072 + 0x00000000);
  4073 + /* XXX : not implemented */
  4074 + spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
  4075 + SPR_NOACCESS, SPR_NOACCESS,
  4076 + &spr_read_generic, &spr_write_generic,
  4077 + 0x00000000);
  4078 + /* XXX : not implemented */
  4079 + spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
  4080 + SPR_NOACCESS, SPR_NOACCESS,
  4081 + &spr_read_generic, &spr_write_generic,
  4082 + 0x00000000);
  4083 + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
  4084 + SPR_NOACCESS, SPR_NOACCESS,
  4085 + &spr_read_generic, &spr_write_generic,
  4086 + 0x00000000);
  4087 + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
  4088 + SPR_NOACCESS, SPR_NOACCESS,
3161 4089 &spr_read_generic, &spr_write_generic,
3162 4090 0x00000000);
3163   - /* Memory management */
3164   -#if !defined(CONFIG_USER_ONLY)
3165   - env->nb_tlb = 64;
3166   - env->nb_ways = 1;
3167   - env->id_tlbs = 0;
3168   -#endif
3169   - init_excp_BookE(env);
3170   - env->dcache_line_size = 32;
3171   - env->icache_line_size = 32;
3172   - /* XXX: TODO: allocate internal IRQ controller */
3173   -}
3174   -
3175   -/* Generic BookE PowerPC */
3176   -#define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3177   - PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3178   - PPC_CACHE_DCBA | \
3179   - PPC_FLOAT | PPC_FLOAT_FSQRT | \
3180   - PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3181   - PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3182   - PPC_BOOKE)
3183   -#define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3184   -#define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3185   -#define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3186   -#define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
3187   -#define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
3188   -#define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
3189   -#define check_pow_BookE check_pow_nocheck
3190   -
3191   -__attribute__ (( unused ))
3192   -static void init_proc_BookE (CPUPPCState *env)
3193   -{
3194   - init_excp_BookE(env);
3195   - env->dcache_line_size = 32;
3196   - env->icache_line_size = 32;
3197   -}
3198   -
3199   -/* e200 core */
3200   -
3201   -/* e300 core */
3202   -
3203   -/* e500 core */
3204   -#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3205   - PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3206   - PPC_CACHE_DCBA | \
3207   - PPC_BOOKE | PPC_E500_VECTOR)
3208   -#define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3209   -#define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3210   -#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3211   -#define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
3212   -#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
3213   -#define check_pow_e500 check_pow_hid0
3214   -
3215   -__attribute__ (( unused ))
3216   -static void init_proc_e500 (CPUPPCState *env)
3217   -{
3218   - /* Time base */
3219   - gen_tbl(env);
3220   - gen_spr_BookE(env);
3221   - /* Memory management */
3222   - gen_spr_BookE_FSL(env);
3223 4091 #if !defined(CONFIG_USER_ONLY)
3224 4092 env->nb_tlb = 64;
3225 4093 env->nb_ways = 1;
3226 4094 env->id_tlbs = 0;
3227 4095 #endif
3228   - init_excp_BookE(env);
  4096 + init_excp_e200(env);
3229 4097 env->dcache_line_size = 32;
3230 4098 env->icache_line_size = 32;
3231 4099 /* XXX: TODO: allocate internal IRQ controller */
3232 4100 }
3233 4101  
3234   -/* e600 core */
3235   -
3236 4102 /* Non-embedded PowerPC */
3237 4103 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3238 4104 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | \
... ... @@ -3429,96 +4295,6 @@ static void init_proc_603E (CPUPPCState *env)
3429 4295 ppc6xx_irq_init(env);
3430 4296 }
3431 4297  
3432   -/* PowerPC G2 */
3433   -#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3434   -#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3435   -#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3436   -//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3437   -#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3438   -#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3439   -#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3440   - POWERPC_FLAG_BE)
3441   -#define check_pow_G2 check_pow_hid0
3442   -
3443   -static void init_proc_G2 (CPUPPCState *env)
3444   -{
3445   - gen_spr_ne_601(env);
3446   - gen_spr_G2_755(env);
3447   - gen_spr_G2(env);
3448   - /* Time base */
3449   - gen_tbl(env);
3450   - /* Hardware implementation register */
3451   - /* XXX : not implemented */
3452   - spr_register(env, SPR_HID0, "HID0",
3453   - SPR_NOACCESS, SPR_NOACCESS,
3454   - &spr_read_generic, &spr_write_generic,
3455   - 0x00000000);
3456   - /* XXX : not implemented */
3457   - spr_register(env, SPR_HID1, "HID1",
3458   - SPR_NOACCESS, SPR_NOACCESS,
3459   - &spr_read_generic, &spr_write_generic,
3460   - 0x00000000);
3461   - /* XXX : not implemented */
3462   - spr_register(env, SPR_HID2, "HID2",
3463   - SPR_NOACCESS, SPR_NOACCESS,
3464   - &spr_read_generic, &spr_write_generic,
3465   - 0x00000000);
3466   - /* Memory management */
3467   - gen_low_BATs(env);
3468   - gen_high_BATs(env);
3469   - gen_6xx_7xx_soft_tlb(env, 64, 2);
3470   - init_excp_G2(env);
3471   - env->dcache_line_size = 32;
3472   - env->icache_line_size = 32;
3473   - /* Allocate hardware IRQ controller */
3474   - ppc6xx_irq_init(env);
3475   -}
3476   -
3477   -/* PowerPC G2LE */
3478   -#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3479   -#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3480   -#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3481   -#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3482   -#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3483   -#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3484   -#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3485   - POWERPC_FLAG_BE)
3486   -#define check_pow_G2LE check_pow_hid0
3487   -
3488   -static void init_proc_G2LE (CPUPPCState *env)
3489   -{
3490   - gen_spr_ne_601(env);
3491   - gen_spr_G2_755(env);
3492   - gen_spr_G2(env);
3493   - /* Time base */
3494   - gen_tbl(env);
3495   - /* Hardware implementation register */
3496   - /* XXX : not implemented */
3497   - spr_register(env, SPR_HID0, "HID0",
3498   - SPR_NOACCESS, SPR_NOACCESS,
3499   - &spr_read_generic, &spr_write_generic,
3500   - 0x00000000);
3501   - /* XXX : not implemented */
3502   - spr_register(env, SPR_HID1, "HID1",
3503   - SPR_NOACCESS, SPR_NOACCESS,
3504   - &spr_read_generic, &spr_write_generic,
3505   - 0x00000000);
3506   - /* XXX : not implemented */
3507   - spr_register(env, SPR_HID2, "HID2",
3508   - SPR_NOACCESS, SPR_NOACCESS,
3509   - &spr_read_generic, &spr_write_generic,
3510   - 0x00000000);
3511   - /* Memory management */
3512   - gen_low_BATs(env);
3513   - gen_high_BATs(env);
3514   - gen_6xx_7xx_soft_tlb(env, 64, 2);
3515   - init_excp_G2(env);
3516   - env->dcache_line_size = 32;
3517   - env->icache_line_size = 32;
3518   - /* Allocate hardware IRQ controller */
3519   - ppc6xx_irq_init(env);
3520   -}
3521   -
3522 4298 /* PowerPC 604 */
3523 4299 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3524 4300 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
... ... @@ -4528,735 +5304,849 @@ static void init_proc_620 (CPUPPCState *env)
4528 5304 enum {
4529 5305 /* PowerPC 401 family */
4530 5306 /* Generic PowerPC 401 */
4531   -#define CPU_POWERPC_401 CPU_POWERPC_401G2
  5307 +#define CPU_POWERPC_401 CPU_POWERPC_401G2
4532 5308 /* PowerPC 401 cores */
4533   - CPU_POWERPC_401A1 = 0x00210000,
4534   - CPU_POWERPC_401B2 = 0x00220000,
  5309 + CPU_POWERPC_401A1 = 0x00210000,
  5310 + CPU_POWERPC_401B2 = 0x00220000,
4535 5311 #if 0
4536   - CPU_POWERPC_401B3 = xxx,
  5312 + CPU_POWERPC_401B3 = xxx,
4537 5313 #endif
4538   - CPU_POWERPC_401C2 = 0x00230000,
4539   - CPU_POWERPC_401D2 = 0x00240000,
4540   - CPU_POWERPC_401E2 = 0x00250000,
4541   - CPU_POWERPC_401F2 = 0x00260000,
4542   - CPU_POWERPC_401G2 = 0x00270000,
  5314 + CPU_POWERPC_401C2 = 0x00230000,
  5315 + CPU_POWERPC_401D2 = 0x00240000,
  5316 + CPU_POWERPC_401E2 = 0x00250000,
  5317 + CPU_POWERPC_401F2 = 0x00260000,
  5318 + CPU_POWERPC_401G2 = 0x00270000,
4543 5319 /* PowerPC 401 microcontrolers */
4544 5320 #if 0
4545   - CPU_POWERPC_401GF = xxx,
  5321 + CPU_POWERPC_401GF = xxx,
4546 5322 #endif
4547   -#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
  5323 +#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4548 5324 /* IBM Processor for Network Resources */
4549   - CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
  5325 + CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4550 5326 #if 0
4551   - CPU_POWERPC_XIPCHIP = xxx,
  5327 + CPU_POWERPC_XIPCHIP = xxx,
4552 5328 #endif
4553 5329 /* PowerPC 403 family */
4554 5330 /* Generic PowerPC 403 */
4555   -#define CPU_POWERPC_403 CPU_POWERPC_403GC
  5331 +#define CPU_POWERPC_403 CPU_POWERPC_403GC
4556 5332 /* PowerPC 403 microcontrollers */
4557   - CPU_POWERPC_403GA = 0x00200011,
4558   - CPU_POWERPC_403GB = 0x00200100,
4559   - CPU_POWERPC_403GC = 0x00200200,
4560   - CPU_POWERPC_403GCX = 0x00201400,
  5333 + CPU_POWERPC_403GA = 0x00200011,
  5334 + CPU_POWERPC_403GB = 0x00200100,
  5335 + CPU_POWERPC_403GC = 0x00200200,
  5336 + CPU_POWERPC_403GCX = 0x00201400,
4561 5337 #if 0
4562   - CPU_POWERPC_403GP = xxx,
  5338 + CPU_POWERPC_403GP = xxx,
4563 5339 #endif
4564 5340 /* PowerPC 405 family */
4565 5341 /* Generic PowerPC 405 */
4566   -#define CPU_POWERPC_405 CPU_POWERPC_405D4
  5342 +#define CPU_POWERPC_405 CPU_POWERPC_405D4
4567 5343 /* PowerPC 405 cores */
4568 5344 #if 0
4569   - CPU_POWERPC_405A3 = xxx,
  5345 + CPU_POWERPC_405A3 = xxx,
4570 5346 #endif
4571 5347 #if 0
4572   - CPU_POWERPC_405A4 = xxx,
  5348 + CPU_POWERPC_405A4 = xxx,
4573 5349 #endif
4574 5350 #if 0
4575   - CPU_POWERPC_405B3 = xxx,
  5351 + CPU_POWERPC_405B3 = xxx,
4576 5352 #endif
4577 5353 #if 0
4578   - CPU_POWERPC_405B4 = xxx,
  5354 + CPU_POWERPC_405B4 = xxx,
4579 5355 #endif
4580 5356 #if 0
4581   - CPU_POWERPC_405C3 = xxx,
  5357 + CPU_POWERPC_405C3 = xxx,
4582 5358 #endif
4583 5359 #if 0
4584   - CPU_POWERPC_405C4 = xxx,
  5360 + CPU_POWERPC_405C4 = xxx,
4585 5361 #endif
4586   - CPU_POWERPC_405D2 = 0x20010000,
  5362 + CPU_POWERPC_405D2 = 0x20010000,
4587 5363 #if 0
4588   - CPU_POWERPC_405D3 = xxx,
  5364 + CPU_POWERPC_405D3 = xxx,
4589 5365 #endif
4590   - CPU_POWERPC_405D4 = 0x41810000,
  5366 + CPU_POWERPC_405D4 = 0x41810000,
4591 5367 #if 0
4592   - CPU_POWERPC_405D5 = xxx,
  5368 + CPU_POWERPC_405D5 = xxx,
4593 5369 #endif
4594 5370 #if 0
4595   - CPU_POWERPC_405E4 = xxx,
  5371 + CPU_POWERPC_405E4 = xxx,
4596 5372 #endif
4597 5373 #if 0
4598   - CPU_POWERPC_405F4 = xxx,
  5374 + CPU_POWERPC_405F4 = xxx,
4599 5375 #endif
4600 5376 #if 0
4601   - CPU_POWERPC_405F5 = xxx,
  5377 + CPU_POWERPC_405F5 = xxx,
4602 5378 #endif
4603 5379 #if 0
4604   - CPU_POWERPC_405F6 = xxx,
  5380 + CPU_POWERPC_405F6 = xxx,
4605 5381 #endif
4606 5382 /* PowerPC 405 microcontrolers */
4607 5383 /* XXX: missing 0x200108a0 */
4608   -#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4609   - CPU_POWERPC_405CRa = 0x40110041,
4610   - CPU_POWERPC_405CRb = 0x401100C5,
4611   - CPU_POWERPC_405CRc = 0x40110145,
4612   - CPU_POWERPC_405EP = 0x51210950,
  5384 +#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
  5385 + CPU_POWERPC_405CRa = 0x40110041,
  5386 + CPU_POWERPC_405CRb = 0x401100C5,
  5387 + CPU_POWERPC_405CRc = 0x40110145,
  5388 + CPU_POWERPC_405EP = 0x51210950,
4613 5389 #if 0
4614   - CPU_POWERPC_405EXr = xxx,
  5390 + CPU_POWERPC_405EXr = xxx,
4615 5391 #endif
4616   - CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
  5392 + CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4617 5393 #if 0
4618   - CPU_POWERPC_405FX = xxx,
4619   -#endif
4620   -#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4621   - CPU_POWERPC_405GPa = 0x40110000,
4622   - CPU_POWERPC_405GPb = 0x40110040,
4623   - CPU_POWERPC_405GPc = 0x40110082,
4624   - CPU_POWERPC_405GPd = 0x401100C4,
4625   -#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4626   - CPU_POWERPC_405GPR = 0x50910951,
  5394 + CPU_POWERPC_405FX = xxx,
  5395 +#endif
  5396 +#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
  5397 + CPU_POWERPC_405GPa = 0x40110000,
  5398 + CPU_POWERPC_405GPb = 0x40110040,
  5399 + CPU_POWERPC_405GPc = 0x40110082,
  5400 + CPU_POWERPC_405GPd = 0x401100C4,
  5401 +#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
  5402 + CPU_POWERPC_405GPR = 0x50910951,
4627 5403 #if 0
4628   - CPU_POWERPC_405H = xxx,
  5404 + CPU_POWERPC_405H = xxx,
4629 5405 #endif
4630 5406 #if 0
4631   - CPU_POWERPC_405L = xxx,
  5407 + CPU_POWERPC_405L = xxx,
4632 5408 #endif
4633   - CPU_POWERPC_405LP = 0x41F10000,
  5409 + CPU_POWERPC_405LP = 0x41F10000,
4634 5410 #if 0
4635   - CPU_POWERPC_405PM = xxx,
  5411 + CPU_POWERPC_405PM = xxx,
4636 5412 #endif
4637 5413 #if 0
4638   - CPU_POWERPC_405PS = xxx,
  5414 + CPU_POWERPC_405PS = xxx,
4639 5415 #endif
4640 5416 #if 0
4641   - CPU_POWERPC_405S = xxx,
  5417 + CPU_POWERPC_405S = xxx,
4642 5418 #endif
4643 5419 /* IBM network processors */
4644   - CPU_POWERPC_NPE405H = 0x414100C0,
4645   - CPU_POWERPC_NPE405H2 = 0x41410140,
4646   - CPU_POWERPC_NPE405L = 0x416100C0,
4647   - CPU_POWERPC_NPE4GS3 = 0x40B10000,
  5420 + CPU_POWERPC_NPE405H = 0x414100C0,
  5421 + CPU_POWERPC_NPE405H2 = 0x41410140,
  5422 + CPU_POWERPC_NPE405L = 0x416100C0,
  5423 + CPU_POWERPC_NPE4GS3 = 0x40B10000,
4648 5424 #if 0
4649   - CPU_POWERPC_NPCxx1 = xxx,
  5425 + CPU_POWERPC_NPCxx1 = xxx,
4650 5426 #endif
4651 5427 #if 0
4652   - CPU_POWERPC_NPR161 = xxx,
  5428 + CPU_POWERPC_NPR161 = xxx,
4653 5429 #endif
4654 5430 #if 0
4655   - CPU_POWERPC_LC77700 = xxx,
  5431 + CPU_POWERPC_LC77700 = xxx,
4656 5432 #endif
4657 5433 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4658 5434 #if 0
4659   - CPU_POWERPC_STB01000 = xxx,
  5435 + CPU_POWERPC_STB01000 = xxx,
4660 5436 #endif
4661 5437 #if 0
4662   - CPU_POWERPC_STB01010 = xxx,
  5438 + CPU_POWERPC_STB01010 = xxx,
4663 5439 #endif
4664 5440 #if 0
4665   - CPU_POWERPC_STB0210 = xxx, /* 401B3 */
  5441 + CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4666 5442 #endif
4667   - CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
  5443 + CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4668 5444 #if 0
4669   - CPU_POWERPC_STB043 = xxx,
  5445 + CPU_POWERPC_STB043 = xxx,
4670 5446 #endif
4671 5447 #if 0
4672   - CPU_POWERPC_STB045 = xxx,
  5448 + CPU_POWERPC_STB045 = xxx,
4673 5449 #endif
4674   - CPU_POWERPC_STB04 = 0x41810000,
4675   - CPU_POWERPC_STB25 = 0x51510950,
  5450 + CPU_POWERPC_STB04 = 0x41810000,
  5451 + CPU_POWERPC_STB25 = 0x51510950,
4676 5452 #if 0
4677   - CPU_POWERPC_STB130 = xxx,
  5453 + CPU_POWERPC_STB130 = xxx,
4678 5454 #endif
4679 5455 /* Xilinx cores */
4680   - CPU_POWERPC_X2VP4 = 0x20010820,
4681   -#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4682   - CPU_POWERPC_X2VP20 = 0x20010860,
4683   -#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
  5456 + CPU_POWERPC_X2VP4 = 0x20010820,
  5457 +#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
  5458 + CPU_POWERPC_X2VP20 = 0x20010860,
  5459 +#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4684 5460 #if 0
4685   - CPU_POWERPC_ZL10310 = xxx,
  5461 + CPU_POWERPC_ZL10310 = xxx,
4686 5462 #endif
4687 5463 #if 0
4688   - CPU_POWERPC_ZL10311 = xxx,
  5464 + CPU_POWERPC_ZL10311 = xxx,
4689 5465 #endif
4690 5466 #if 0
4691   - CPU_POWERPC_ZL10320 = xxx,
  5467 + CPU_POWERPC_ZL10320 = xxx,
4692 5468 #endif
4693 5469 #if 0
4694   - CPU_POWERPC_ZL10321 = xxx,
  5470 + CPU_POWERPC_ZL10321 = xxx,
4695 5471 #endif
4696 5472 /* PowerPC 440 family */
4697 5473 /* Generic PowerPC 440 */
4698   -#define CPU_POWERPC_440 CPU_POWERPC_440GXf
  5474 +#define CPU_POWERPC_440 CPU_POWERPC_440GXf
4699 5475 /* PowerPC 440 cores */
4700 5476 #if 0
4701   - CPU_POWERPC_440A4 = xxx,
  5477 + CPU_POWERPC_440A4 = xxx,
4702 5478 #endif
4703 5479 #if 0
4704   - CPU_POWERPC_440A5 = xxx,
  5480 + CPU_POWERPC_440A5 = xxx,
4705 5481 #endif
4706 5482 #if 0
4707   - CPU_POWERPC_440B4 = xxx,
  5483 + CPU_POWERPC_440B4 = xxx,
4708 5484 #endif
4709 5485 #if 0
4710   - CPU_POWERPC_440F5 = xxx,
  5486 + CPU_POWERPC_440F5 = xxx,
4711 5487 #endif
4712 5488 #if 0
4713   - CPU_POWERPC_440G5 = xxx,
  5489 + CPU_POWERPC_440G5 = xxx,
4714 5490 #endif
4715 5491 #if 0
4716   - CPU_POWERPC_440H4 = xxx,
  5492 + CPU_POWERPC_440H4 = xxx,
4717 5493 #endif
4718 5494 #if 0
4719   - CPU_POWERPC_440H6 = xxx,
  5495 + CPU_POWERPC_440H6 = xxx,
4720 5496 #endif
4721 5497 /* PowerPC 440 microcontrolers */
4722   -#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4723   - CPU_POWERPC_440EPa = 0x42221850,
4724   - CPU_POWERPC_440EPb = 0x422218D3,
4725   -#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4726   - CPU_POWERPC_440GPb = 0x40120440,
4727   - CPU_POWERPC_440GPc = 0x40120481,
4728   -#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4729   -#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4730   - CPU_POWERPC_440GRX = 0x200008D0,
4731   -#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4732   -#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4733   - CPU_POWERPC_440GXa = 0x51B21850,
4734   - CPU_POWERPC_440GXb = 0x51B21851,
4735   - CPU_POWERPC_440GXc = 0x51B21892,
4736   - CPU_POWERPC_440GXf = 0x51B21894,
  5498 +#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
  5499 + CPU_POWERPC_440EPa = 0x42221850,
  5500 + CPU_POWERPC_440EPb = 0x422218D3,
  5501 +#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
  5502 + CPU_POWERPC_440GPb = 0x40120440,
  5503 + CPU_POWERPC_440GPc = 0x40120481,
  5504 +#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
  5505 +#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
  5506 + CPU_POWERPC_440GRX = 0x200008D0,
  5507 +#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
  5508 +#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
  5509 + CPU_POWERPC_440GXa = 0x51B21850,
  5510 + CPU_POWERPC_440GXb = 0x51B21851,
  5511 + CPU_POWERPC_440GXc = 0x51B21892,
  5512 + CPU_POWERPC_440GXf = 0x51B21894,
4737 5513 #if 0
4738   - CPU_POWERPC_440S = xxx,
  5514 + CPU_POWERPC_440S = xxx,
4739 5515 #endif
4740   - CPU_POWERPC_440SP = 0x53221850,
4741   - CPU_POWERPC_440SP2 = 0x53221891,
4742   - CPU_POWERPC_440SPE = 0x53421890,
  5516 + CPU_POWERPC_440SP = 0x53221850,
  5517 + CPU_POWERPC_440SP2 = 0x53221891,
  5518 + CPU_POWERPC_440SPE = 0x53421890,
4743 5519 /* PowerPC 460 family */
4744 5520 #if 0
4745 5521 /* Generic PowerPC 464 */
4746   -#define CPU_POWERPC_464 CPU_POWERPC_464H90
  5522 +#define CPU_POWERPC_464 CPU_POWERPC_464H90
4747 5523 #endif
4748 5524 /* PowerPC 464 microcontrolers */
4749 5525 #if 0
4750   - CPU_POWERPC_464H90 = xxx,
  5526 + CPU_POWERPC_464H90 = xxx,
4751 5527 #endif
4752 5528 #if 0
4753   - CPU_POWERPC_464H90FP = xxx,
  5529 + CPU_POWERPC_464H90FP = xxx,
4754 5530 #endif
4755 5531 /* Freescale embedded PowerPC cores */
4756 5532 /* PowerPC MPC 5xx cores (aka RCPU) */
4757   - CPU_POWERPC_5xx = 0x00020020,
4758   -#define CPU_POWERPC_509 CPU_POWERPC_5xx
4759   -#define CPU_POWERPC_533 CPU_POWERPC_5xx
4760   -#define CPU_POWERPC_534 CPU_POWERPC_5xx
4761   -#define CPU_POWERPC_555 CPU_POWERPC_5xx
4762   -#define CPU_POWERPC_556 CPU_POWERPC_5xx
4763   -#define CPU_POWERPC_560 CPU_POWERPC_5xx
4764   -#define CPU_POWERPC_561 CPU_POWERPC_5xx
4765   -#define CPU_POWERPC_562 CPU_POWERPC_5xx
4766   -#define CPU_POWERPC_563 CPU_POWERPC_5xx
4767   -#define CPU_POWERPC_564 CPU_POWERPC_5xx
4768   -#define CPU_POWERPC_565 CPU_POWERPC_5xx
4769   -#define CPU_POWERPC_566 CPU_POWERPC_5xx
  5533 + CPU_POWERPC_MPC5xx = 0x00020020,
  5534 +#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
  5535 +#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
  5536 +#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
  5537 +#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
  5538 +#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
  5539 +#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
  5540 +#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
  5541 +#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
  5542 +#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
  5543 +#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
  5544 +#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
  5545 +#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
  5546 +#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
4770 5547 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4771   - CPU_POWERPC_8xx = 0x00500000,
4772   -#define CPU_POWERPC_821 CPU_POWERPC_8xx
4773   -#define CPU_POWERPC_823 CPU_POWERPC_8xx
4774   -#define CPU_POWERPC_850 CPU_POWERPC_8xx
4775   -#define CPU_POWERPC_852T CPU_POWERPC_8xx
4776   -#define CPU_POWERPC_855T CPU_POWERPC_8xx
4777   -#define CPU_POWERPC_859 CPU_POWERPC_8xx
4778   -#define CPU_POWERPC_860 CPU_POWERPC_8xx
4779   -#define CPU_POWERPC_862 CPU_POWERPC_8xx
4780   -#define CPU_POWERPC_866 CPU_POWERPC_8xx
4781   -#define CPU_POWERPC_857 CPU_POWERPC_8xx
4782   -#define CPU_POWERPC_870 CPU_POWERPC_8xx
4783   -#define CPU_POWERPC_875 CPU_POWERPC_8xx
4784   -#define CPU_POWERPC_880 CPU_POWERPC_8xx
4785   -#define CPU_POWERPC_885 CPU_POWERPC_8xx
  5548 + CPU_POWERPC_MPC8xx = 0x00500000,
  5549 +#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
  5550 +#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
  5551 +#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
  5552 +#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
  5553 +#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
  5554 +#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
  5555 +#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
  5556 +#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
  5557 +#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
  5558 +#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
  5559 +#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
  5560 +#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
  5561 +#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
  5562 +#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
  5563 +#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
4786 5564 /* G2 cores (aka PowerQUICC-II) */
4787   - CPU_POWERPC_G2 = 0x00810011,
4788   - CPU_POWERPC_G2H4 = 0x80811010,
4789   - CPU_POWERPC_G2gp = 0x80821010,
4790   - CPU_POWERPC_G2ls = 0x90810010,
4791   - CPU_POWERPC_MPC603 = 0x00810100,
4792   -#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
4793   - CPU_POWERPC_G2_HIP3 = 0x00810101,
4794   -#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
4795   -#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
4796   -#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
4797   -#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
4798   -#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
4799   -#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
4800   - CPU_POWERPC_G2_HIP4 = 0x80811014,
4801   -#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
4802   -#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
4803   -#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
4804   -#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
4805   -#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
4806   -#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
4807   -#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
4808   -#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
  5565 + CPU_POWERPC_G2 = 0x00810011,
  5566 + CPU_POWERPC_G2H4 = 0x80811010,
  5567 + CPU_POWERPC_G2gp = 0x80821010,
  5568 + CPU_POWERPC_G2ls = 0x90810010,
  5569 + CPU_POWERPC_MPC603 = 0x00810100,
  5570 + CPU_POWERPC_G2_HIP3 = 0x00810101,
  5571 + CPU_POWERPC_G2_HIP4 = 0x80811014,
4809 5572 /* G2_LE core (aka PowerQUICC-II) */
4810   - CPU_POWERPC_G2LE = 0x80820010,
4811   - CPU_POWERPC_G2LEgp = 0x80822010,
4812   - CPU_POWERPC_G2LEls = 0xA0822010,
4813   - CPU_POWERPC_G2LEgp1 = 0x80822011,
  5573 + CPU_POWERPC_G2LE = 0x80820010,
  5574 + CPU_POWERPC_G2LEgp = 0x80822010,
  5575 + CPU_POWERPC_G2LEls = 0xA0822010,
  5576 + CPU_POWERPC_G2LEgp1 = 0x80822011,
  5577 + CPU_POWERPC_G2LEgp3 = 0x80822013,
  5578 + /* MPC52xx microcontrollers */
4814 5579 /* XXX: MPC 5121 ? */
4815   -#define CPU_POWERPC_MPC5200 CPU_POWERPC_G2LEgp1
4816   - CPU_POWERPC_G2LEgp3 = 0x80822013,
4817   -#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
4818   -#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
4819   -#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
4820   -#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
4821   -#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
4822   -#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
4823   -#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
  5580 +#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
  5581 +#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
  5582 +#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
  5583 +#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
  5584 +#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
  5585 +#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
  5586 +#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
  5587 +#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
  5588 + /* MPC82xx microcontrollers */
  5589 +#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
  5590 +#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
  5591 +#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
  5592 +#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
  5593 +#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
  5594 +#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
  5595 +#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
  5596 +#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
  5597 +#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
  5598 +#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
  5599 +#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
  5600 +#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
  5601 +#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
  5602 +#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
  5603 +#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
  5604 +#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
  5605 +#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
  5606 +#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
  5607 +#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
  5608 +#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
  5609 +#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
  5610 +#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
  5611 +#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
  5612 +#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
  5613 +#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
  5614 +#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
  5615 +#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
  5616 +#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
  5617 +#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
4824 5618 /* e200 family */
4825   -#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
  5619 + /* e200 cores */
  5620 +#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4826 5621 #if 0
4827   - CPU_POWERPC_e200z0 = xxx,
4828   -#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
4829   -#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
4830   -#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
4831   -#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
  5622 + CPU_POWERPC_e200z0 = xxx,
4832 5623 #endif
4833 5624 #if 0
4834   - CPU_POWERPC_e200z1 = xxx,
4835   -#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
4836   -#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
4837   -#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
4838   -#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
4839   -#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
4840   -#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
  5625 + CPU_POWERPC_e200z1 = xxx,
4841 5626 #endif
4842 5627 #if 0 /* ? */
4843   - CPU_POWERPC_e200z3 = 0x81120000,
4844   -#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
4845   -#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
4846   -#endif
4847   - CPU_POWERPC_e200z5 = 0x81000000,
4848   - CPU_POWERPC_e200z6 = 0x81120000,
4849   -#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
4850   -#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
4851   -#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
4852   -#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
4853   -#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
4854   -#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
  5628 + CPU_POWERPC_e200z3 = 0x81120000,
  5629 +#endif
  5630 + CPU_POWERPC_e200z5 = 0x81000000,
  5631 + CPU_POWERPC_e200z6 = 0x81120000,
  5632 + /* MPC55xx microcontrollers */
  5633 +#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
  5634 +#if 0
  5635 +#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
  5636 +#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
  5637 +#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
  5638 +#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
  5639 +#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
  5640 +#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
  5641 +#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
  5642 +#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
  5643 +#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
  5644 +#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
  5645 +#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
  5646 +#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
  5647 +#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
  5648 +#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
  5649 +#endif
  5650 +#if 0
  5651 +#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
  5652 +#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
  5653 +#endif
  5654 +#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
  5655 +#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
  5656 +#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
  5657 +#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
  5658 +#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
  5659 +#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
4855 5660 /* e300 family */
4856   -#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4857   - CPU_POWERPC_e300c1 = 0x00830000,
4858   -#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
4859   -#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
4860   -#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
4861   -#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
4862   -#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
4863   -#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
4864   -#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
4865   -#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
4866   - CPU_POWERPC_e300c2 = 0x00840000,
4867   -#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
4868   -#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
4869   -#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
4870   -#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
4871   - CPU_POWERPC_e300c3 = 0x00850000,
4872   -#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
4873   -#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
4874   -#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
4875   -#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
4876   -#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
4877   -#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
4878   - CPU_POWERPC_e300c4 = 0x00860000,
4879   -#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
4880   -#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
4881   -#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
4882   -#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
4883   -#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
4884   -#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
  5661 + /* e300 cores */
  5662 +#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
  5663 + CPU_POWERPC_e300c1 = 0x00830010,
  5664 + CPU_POWERPC_e300c2 = 0x00840010,
  5665 + CPU_POWERPC_e300c3 = 0x00850010,
  5666 + CPU_POWERPC_e300c4 = 0x00860010,
  5667 + /* MPC83xx microcontrollers */
  5668 +#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
  5669 +#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
  5670 +#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
  5671 +#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
  5672 +#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
  5673 +#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
  5674 +#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
  5675 +#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
  5676 +#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
  5677 +#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
  5678 +#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
  5679 +#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
  5680 +#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
  5681 +#define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
  5682 +#define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
  5683 +#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
  5684 +#define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
  5685 +#define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
  5686 +#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
  5687 +#define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
  5688 +#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
  5689 +#define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
  5690 +#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
  5691 +#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
  5692 +#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
  5693 +#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
  5694 +#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
  5695 +#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
  5696 +#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
  5697 +#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
4885 5698 /* e500 family */
4886   -#define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4887   - CPU_POWERPC_e500_v10 = 0x80200010,
4888   -#define CPU_POWERPC_MPC8540_v1 CPU_POWERPC_e500_v10
4889   - CPU_POWERPC_e500_v20 = 0x80200020,
4890   -#define CPU_POWERPC_MPC8540_v2 CPU_POWERPC_e500_v20
4891   -#define CPU_POWERPC_MPC8541 CPU_POWERPC_e500_v20
4892   -#define CPU_POWERPC_MPC8541E CPU_POWERPC_e500_v20
4893   -#define CPU_POWERPC_MPC8555 CPU_POWERPC_e500_v20
4894   -#define CPU_POWERPC_MPC8555E CPU_POWERPC_e500_v20
4895   -#define CPU_POWERPC_MPC8560 CPU_POWERPC_e500_v20
4896   - CPU_POWERPC_e500v2_v10 = 0x80210010,
4897   -#define CPU_POWERPC_MPC8543 CPU_POWERPC_e500v2_v10
4898   -#define CPU_POWERPC_MPC8543E CPU_POWERPC_e500v2_v10
4899   -#define CPU_POWERPC_MPC8545 CPU_POWERPC_e500v2_v10
4900   -#define CPU_POWERPC_MPC8545E CPU_POWERPC_e500v2_v10
4901   -#define CPU_POWERPC_MPC8547E CPU_POWERPC_e500v2_v10
4902   -#define CPU_POWERPC_MPC8548 CPU_POWERPC_e500v2_v10
4903   -#define CPU_POWERPC_MPC8548E CPU_POWERPC_e500v2_v10
4904   - CPU_POWERPC_e500v2_v20 = 0x80210020,
4905   - CPU_POWERPC_e500v2_v21 = 0x80210021,
4906   -#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
4907   -#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
4908   -#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
4909   -#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
4910   - CPU_POWERPC_e500v2_v22 = 0x80210022,
4911   -#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
4912   -#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
4913   -#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
4914   -#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
4915   -#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
4916   -#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
4917   - CPU_POWERPC_e500v2_v30 = 0x80210030,
4918   -#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
  5699 + /* e500 cores */
  5700 +#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
  5701 +#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
  5702 + CPU_POWERPC_e500_v10 = 0x80200010,
  5703 + CPU_POWERPC_e500_v20 = 0x80200020,
  5704 + CPU_POWERPC_e500v2_v10 = 0x80210010,
  5705 + CPU_POWERPC_e500v2_v11 = 0x80210011,
  5706 + CPU_POWERPC_e500v2_v20 = 0x80210020,
  5707 + CPU_POWERPC_e500v2_v21 = 0x80210021,
  5708 + CPU_POWERPC_e500v2_v22 = 0x80210022,
  5709 + CPU_POWERPC_e500v2_v30 = 0x80210030,
  5710 + /* MPC85xx microcontrollers */
  5711 +#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
  5712 +#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
  5713 +#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
  5714 +#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
  5715 +#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
  5716 +#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
  5717 +#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
  5718 +#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500_v10
  5719 +#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500_v20
  5720 +#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500_v20
  5721 +#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
  5722 +#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500_v20
  5723 +#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500_v20
  5724 +#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
  5725 +#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500_v20
  5726 +#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500_v20
  5727 +#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
  5728 +#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
  5729 +#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
  5730 +#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
  5731 +#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
  5732 +#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
  5733 +#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
  5734 +#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
  5735 +#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
  5736 +#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
  5737 +#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
  5738 +#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
  5739 +#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
  5740 +#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
  5741 +#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
  5742 +#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
  5743 +#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
  5744 +#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
  5745 +#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
  5746 +#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
  5747 +#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
  5748 +#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
  5749 +#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
  5750 +#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
  5751 +#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
  5752 +#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
  5753 +#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
  5754 +#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
  5755 +#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
  5756 +#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
  5757 +#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
  5758 +#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
  5759 +#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
  5760 +#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
  5761 +#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
  5762 +#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
  5763 +#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
  5764 +#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
  5765 +#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
  5766 +#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
  5767 +#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
  5768 +#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
  5769 +#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
  5770 +#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
  5771 +#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
  5772 +#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
  5773 +#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
  5774 +#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
  5775 +#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
  5776 +#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
  5777 +#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
  5778 +#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
  5779 +#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
  5780 +#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
4919 5781 /* e600 family */
4920   - CPU_POWERPC_e600 = 0x80040010,
4921   -#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
4922   -#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
4923   -#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
  5782 + /* e600 cores */
  5783 + CPU_POWERPC_e600 = 0x80040010,
  5784 + /* MPC86xx microcontrollers */
  5785 +#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
  5786 +#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
  5787 +#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
4924 5788 /* PowerPC 6xx cores */
4925   -#define CPU_POWERPC_601 CPU_POWERPC_601_v2
4926   - CPU_POWERPC_601_v0 = 0x00010001,
4927   - CPU_POWERPC_601_v1 = 0x00010001,
4928   - CPU_POWERPC_601_v2 = 0x00010002,
4929   - CPU_POWERPC_602 = 0x00050100,
4930   - CPU_POWERPC_603 = 0x00030100,
4931   -#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4932   - CPU_POWERPC_603E_v11 = 0x00060101,
4933   - CPU_POWERPC_603E_v12 = 0x00060102,
4934   - CPU_POWERPC_603E_v13 = 0x00060103,
4935   - CPU_POWERPC_603E_v14 = 0x00060104,
4936   - CPU_POWERPC_603E_v22 = 0x00060202,
4937   - CPU_POWERPC_603E_v3 = 0x00060300,
4938   - CPU_POWERPC_603E_v4 = 0x00060400,
4939   - CPU_POWERPC_603E_v41 = 0x00060401,
4940   - CPU_POWERPC_603E7t = 0x00071201,
4941   - CPU_POWERPC_603E7v = 0x00070100,
4942   - CPU_POWERPC_603E7v1 = 0x00070101,
4943   - CPU_POWERPC_603E7v2 = 0x00070201,
4944   - CPU_POWERPC_603E7 = 0x00070200,
4945   - CPU_POWERPC_603P = 0x00070000,
4946   -#define CPU_POWERPC_603R CPU_POWERPC_603E7t
  5789 +#define CPU_POWERPC_601 CPU_POWERPC_601_v2
  5790 + CPU_POWERPC_601_v0 = 0x00010001,
  5791 + CPU_POWERPC_601_v1 = 0x00010001,
  5792 + CPU_POWERPC_601_v2 = 0x00010002,
  5793 + CPU_POWERPC_602 = 0x00050100,
  5794 + CPU_POWERPC_603 = 0x00030100,
  5795 +#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
  5796 + CPU_POWERPC_603E_v11 = 0x00060101,
  5797 + CPU_POWERPC_603E_v12 = 0x00060102,
  5798 + CPU_POWERPC_603E_v13 = 0x00060103,
  5799 + CPU_POWERPC_603E_v14 = 0x00060104,
  5800 + CPU_POWERPC_603E_v22 = 0x00060202,
  5801 + CPU_POWERPC_603E_v3 = 0x00060300,
  5802 + CPU_POWERPC_603E_v4 = 0x00060400,
  5803 + CPU_POWERPC_603E_v41 = 0x00060401,
  5804 + CPU_POWERPC_603E7t = 0x00071201,
  5805 + CPU_POWERPC_603E7v = 0x00070100,
  5806 + CPU_POWERPC_603E7v1 = 0x00070101,
  5807 + CPU_POWERPC_603E7v2 = 0x00070201,
  5808 + CPU_POWERPC_603E7 = 0x00070200,
  5809 + CPU_POWERPC_603P = 0x00070000,
  5810 +#define CPU_POWERPC_603R CPU_POWERPC_603E7t
4947 5811 /* XXX: missing 0x00040303 (604) */
4948   - CPU_POWERPC_604 = 0x00040103,
4949   -#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
  5812 + CPU_POWERPC_604 = 0x00040103,
  5813 +#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4950 5814 /* XXX: missing 0x00091203 */
4951 5815 /* XXX: missing 0x00092110 */
4952 5816 /* XXX: missing 0x00092120 */
4953   - CPU_POWERPC_604E_v10 = 0x00090100,
4954   - CPU_POWERPC_604E_v22 = 0x00090202,
4955   - CPU_POWERPC_604E_v24 = 0x00090204,
  5817 + CPU_POWERPC_604E_v10 = 0x00090100,
  5818 + CPU_POWERPC_604E_v22 = 0x00090202,
  5819 + CPU_POWERPC_604E_v24 = 0x00090204,
4956 5820 /* XXX: missing 0x000a0100 */
4957 5821 /* XXX: missing 0x00093102 */
4958   - CPU_POWERPC_604R = 0x000a0101,
  5822 + CPU_POWERPC_604R = 0x000a0101,
4959 5823 #if 0
4960   - CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
  5824 + CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
4961 5825 #endif
4962 5826 /* PowerPC 740/750 cores (aka G3) */
4963 5827 /* XXX: missing 0x00084202 */
4964   -#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4965   - CPU_POWERPC_7x0_v20 = 0x00080200,
4966   - CPU_POWERPC_7x0_v21 = 0x00080201,
4967   - CPU_POWERPC_7x0_v22 = 0x00080202,
4968   - CPU_POWERPC_7x0_v30 = 0x00080300,
4969   - CPU_POWERPC_7x0_v31 = 0x00080301,
4970   - CPU_POWERPC_740E = 0x00080100,
4971   - CPU_POWERPC_7x0P = 0x10080000,
  5828 +#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
  5829 + CPU_POWERPC_7x0_v20 = 0x00080200,
  5830 + CPU_POWERPC_7x0_v21 = 0x00080201,
  5831 + CPU_POWERPC_7x0_v22 = 0x00080202,
  5832 + CPU_POWERPC_7x0_v30 = 0x00080300,
  5833 + CPU_POWERPC_7x0_v31 = 0x00080301,
  5834 + CPU_POWERPC_740E = 0x00080100,
  5835 + CPU_POWERPC_7x0P = 0x10080000,
4972 5836 /* XXX: missing 0x00087010 (CL ?) */
4973   - CPU_POWERPC_750CL = 0x00087200,
4974   -#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4975   - CPU_POWERPC_750CX_v21 = 0x00082201,
4976   - CPU_POWERPC_750CX_v22 = 0x00082202,
4977   -#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4978   - CPU_POWERPC_750CXE_v21 = 0x00082211,
4979   - CPU_POWERPC_750CXE_v22 = 0x00082212,
4980   - CPU_POWERPC_750CXE_v23 = 0x00082213,
4981   - CPU_POWERPC_750CXE_v24 = 0x00082214,
4982   - CPU_POWERPC_750CXE_v24b = 0x00083214,
4983   - CPU_POWERPC_750CXE_v31 = 0x00083211,
4984   - CPU_POWERPC_750CXE_v31b = 0x00083311,
4985   - CPU_POWERPC_750CXR = 0x00083410,
4986   - CPU_POWERPC_750E = 0x00080200,
4987   - CPU_POWERPC_750FL = 0x700A0203,
4988   -#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4989   - CPU_POWERPC_750FX_v10 = 0x70000100,
4990   - CPU_POWERPC_750FX_v20 = 0x70000200,
4991   - CPU_POWERPC_750FX_v21 = 0x70000201,
4992   - CPU_POWERPC_750FX_v22 = 0x70000202,
4993   - CPU_POWERPC_750FX_v23 = 0x70000203,
4994   - CPU_POWERPC_750GL = 0x70020102,
4995   -#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4996   - CPU_POWERPC_750GX_v10 = 0x70020100,
4997   - CPU_POWERPC_750GX_v11 = 0x70020101,
4998   - CPU_POWERPC_750GX_v12 = 0x70020102,
4999   -#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
5000   - CPU_POWERPC_750L_v22 = 0x00088202,
5001   - CPU_POWERPC_750L_v30 = 0x00088300,
5002   - CPU_POWERPC_750L_v32 = 0x00088302,
  5837 + CPU_POWERPC_750CL = 0x00087200,
  5838 +#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
  5839 + CPU_POWERPC_750CX_v21 = 0x00082201,
  5840 + CPU_POWERPC_750CX_v22 = 0x00082202,
  5841 +#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
  5842 + CPU_POWERPC_750CXE_v21 = 0x00082211,
  5843 + CPU_POWERPC_750CXE_v22 = 0x00082212,
  5844 + CPU_POWERPC_750CXE_v23 = 0x00082213,
  5845 + CPU_POWERPC_750CXE_v24 = 0x00082214,
  5846 + CPU_POWERPC_750CXE_v24b = 0x00083214,
  5847 + CPU_POWERPC_750CXE_v31 = 0x00083211,
  5848 + CPU_POWERPC_750CXE_v31b = 0x00083311,
  5849 + CPU_POWERPC_750CXR = 0x00083410,
  5850 + CPU_POWERPC_750E = 0x00080200,
  5851 + CPU_POWERPC_750FL = 0x700A0203,
  5852 +#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
  5853 + CPU_POWERPC_750FX_v10 = 0x70000100,
  5854 + CPU_POWERPC_750FX_v20 = 0x70000200,
  5855 + CPU_POWERPC_750FX_v21 = 0x70000201,
  5856 + CPU_POWERPC_750FX_v22 = 0x70000202,
  5857 + CPU_POWERPC_750FX_v23 = 0x70000203,
  5858 + CPU_POWERPC_750GL = 0x70020102,
  5859 +#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
  5860 + CPU_POWERPC_750GX_v10 = 0x70020100,
  5861 + CPU_POWERPC_750GX_v11 = 0x70020101,
  5862 + CPU_POWERPC_750GX_v12 = 0x70020102,
  5863 +#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
  5864 + CPU_POWERPC_750L_v22 = 0x00088202,
  5865 + CPU_POWERPC_750L_v30 = 0x00088300,
  5866 + CPU_POWERPC_750L_v32 = 0x00088302,
5003 5867 /* PowerPC 745/755 cores */
5004   -#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
5005   - CPU_POWERPC_7x5_v10 = 0x00083100,
5006   - CPU_POWERPC_7x5_v11 = 0x00083101,
5007   - CPU_POWERPC_7x5_v20 = 0x00083200,
5008   - CPU_POWERPC_7x5_v21 = 0x00083201,
5009   - CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
5010   - CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
5011   - CPU_POWERPC_7x5_v24 = 0x00083204,
5012   - CPU_POWERPC_7x5_v25 = 0x00083205,
5013   - CPU_POWERPC_7x5_v26 = 0x00083206,
5014   - CPU_POWERPC_7x5_v27 = 0x00083207,
5015   - CPU_POWERPC_7x5_v28 = 0x00083208,
  5868 +#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
  5869 + CPU_POWERPC_7x5_v10 = 0x00083100,
  5870 + CPU_POWERPC_7x5_v11 = 0x00083101,
  5871 + CPU_POWERPC_7x5_v20 = 0x00083200,
  5872 + CPU_POWERPC_7x5_v21 = 0x00083201,
  5873 + CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
  5874 + CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
  5875 + CPU_POWERPC_7x5_v24 = 0x00083204,
  5876 + CPU_POWERPC_7x5_v25 = 0x00083205,
  5877 + CPU_POWERPC_7x5_v26 = 0x00083206,
  5878 + CPU_POWERPC_7x5_v27 = 0x00083207,
  5879 + CPU_POWERPC_7x5_v28 = 0x00083208,
5016 5880 #if 0
5017   - CPU_POWERPC_7x5P = xxx,
  5881 + CPU_POWERPC_7x5P = xxx,
5018 5882 #endif
5019 5883 /* PowerPC 74xx cores (aka G4) */
5020 5884 /* XXX: missing 0x000C1101 */
5021   -#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
5022   - CPU_POWERPC_7400_v10 = 0x000C0100,
5023   - CPU_POWERPC_7400_v11 = 0x000C0101,
5024   - CPU_POWERPC_7400_v20 = 0x000C0200,
5025   - CPU_POWERPC_7400_v22 = 0x000C0202,
5026   - CPU_POWERPC_7400_v26 = 0x000C0206,
5027   - CPU_POWERPC_7400_v27 = 0x000C0207,
5028   - CPU_POWERPC_7400_v28 = 0x000C0208,
5029   - CPU_POWERPC_7400_v29 = 0x000C0209,
5030   -#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
5031   - CPU_POWERPC_7410_v10 = 0x800C1100,
5032   - CPU_POWERPC_7410_v11 = 0x800C1101,
5033   - CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
5034   - CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
5035   - CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
5036   -#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
5037   - CPU_POWERPC_7448_v10 = 0x80040100,
5038   - CPU_POWERPC_7448_v11 = 0x80040101,
5039   - CPU_POWERPC_7448_v20 = 0x80040200,
5040   - CPU_POWERPC_7448_v21 = 0x80040201,
5041   -#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
5042   - CPU_POWERPC_7450_v10 = 0x80000100,
5043   - CPU_POWERPC_7450_v11 = 0x80000101,
5044   - CPU_POWERPC_7450_v12 = 0x80000102,
5045   - CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
5046   - CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
5047   - CPU_POWERPC_74x1 = 0x80000203,
5048   - CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
5049   -#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
5050   - CPU_POWERPC_74x5_v10 = 0x80010100,
  5885 +#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
  5886 + CPU_POWERPC_7400_v10 = 0x000C0100,
  5887 + CPU_POWERPC_7400_v11 = 0x000C0101,
  5888 + CPU_POWERPC_7400_v20 = 0x000C0200,
  5889 + CPU_POWERPC_7400_v22 = 0x000C0202,
  5890 + CPU_POWERPC_7400_v26 = 0x000C0206,
  5891 + CPU_POWERPC_7400_v27 = 0x000C0207,
  5892 + CPU_POWERPC_7400_v28 = 0x000C0208,
  5893 + CPU_POWERPC_7400_v29 = 0x000C0209,
  5894 +#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
  5895 + CPU_POWERPC_7410_v10 = 0x800C1100,
  5896 + CPU_POWERPC_7410_v11 = 0x800C1101,
  5897 + CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
  5898 + CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
  5899 + CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
  5900 +#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
  5901 + CPU_POWERPC_7448_v10 = 0x80040100,
  5902 + CPU_POWERPC_7448_v11 = 0x80040101,
  5903 + CPU_POWERPC_7448_v20 = 0x80040200,
  5904 + CPU_POWERPC_7448_v21 = 0x80040201,
  5905 +#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
  5906 + CPU_POWERPC_7450_v10 = 0x80000100,
  5907 + CPU_POWERPC_7450_v11 = 0x80000101,
  5908 + CPU_POWERPC_7450_v12 = 0x80000102,
  5909 + CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
  5910 + CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
  5911 + CPU_POWERPC_74x1 = 0x80000203,
  5912 + CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
  5913 +#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
  5914 + CPU_POWERPC_74x5_v10 = 0x80010100,
5051 5915 /* XXX: missing 0x80010200 */
5052   - CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
5053   - CPU_POWERPC_74x5_v32 = 0x80010302,
5054   - CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
5055   - CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
5056   -#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
  5916 + CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
  5917 + CPU_POWERPC_74x5_v32 = 0x80010302,
  5918 + CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
  5919 + CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
  5920 +#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
5057 5921 /* XXX: is 0x8002xxxx 7447 and 0x8003xxxx 7457 ? */
5058 5922 /* XXX: missing 0x80030102 */
5059 5923 /* XXX: missing 0x80020101 */
5060   - CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
5061   - CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
5062   - CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
  5924 + CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
  5925 + CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
  5926 + CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
5063 5927 /* 64 bits PowerPC */
5064 5928 #if defined(TARGET_PPC64)
5065   - CPU_POWERPC_620 = 0x00140000,
5066   - CPU_POWERPC_630 = 0x00400000,
5067   - CPU_POWERPC_631 = 0x00410104,
5068   - CPU_POWERPC_POWER4 = 0x00350000,
5069   - CPU_POWERPC_POWER4P = 0x00380000,
  5929 + CPU_POWERPC_620 = 0x00140000,
  5930 + CPU_POWERPC_630 = 0x00400000,
  5931 + CPU_POWERPC_631 = 0x00410104,
  5932 + CPU_POWERPC_POWER4 = 0x00350000,
  5933 + CPU_POWERPC_POWER4P = 0x00380000,
5070 5934 /* XXX: missing 0x003A0201 */
5071   - CPU_POWERPC_POWER5 = 0x003A0203,
5072   -#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
5073   - CPU_POWERPC_POWER5P = 0x003B0000,
5074   -#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
5075   - CPU_POWERPC_POWER6 = 0x003E0000,
5076   - CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
5077   - CPU_POWERPC_POWER6A = 0x0F000002,
5078   - CPU_POWERPC_970 = 0x00390202,
5079   -#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
5080   - CPU_POWERPC_970FX_v10 = 0x00391100,
5081   - CPU_POWERPC_970FX_v20 = 0x003C0200,
5082   - CPU_POWERPC_970FX_v21 = 0x003C0201,
5083   - CPU_POWERPC_970FX_v30 = 0x003C0300,
5084   - CPU_POWERPC_970FX_v31 = 0x003C0301,
5085   - CPU_POWERPC_970GX = 0x00450000,
5086   -#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
5087   - CPU_POWERPC_970MP_v10 = 0x00440100,
5088   - CPU_POWERPC_970MP_v11 = 0x00440101,
5089   -#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
5090   - CPU_POWERPC_CELL_v10 = 0x00700100,
5091   - CPU_POWERPC_CELL_v20 = 0x00700400,
5092   - CPU_POWERPC_CELL_v30 = 0x00700500,
5093   - CPU_POWERPC_CELL_v31 = 0x00700501,
5094   -#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
5095   - CPU_POWERPC_RS64 = 0x00330000,
5096   - CPU_POWERPC_RS64II = 0x00340000,
5097   - CPU_POWERPC_RS64III = 0x00360000,
5098   - CPU_POWERPC_RS64IV = 0x00370000,
  5935 + CPU_POWERPC_POWER5 = 0x003A0203,
  5936 +#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
  5937 + CPU_POWERPC_POWER5P = 0x003B0000,
  5938 +#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
  5939 + CPU_POWERPC_POWER6 = 0x003E0000,
  5940 + CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
  5941 + CPU_POWERPC_POWER6A = 0x0F000002,
  5942 + CPU_POWERPC_970 = 0x00390202,
  5943 +#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
  5944 + CPU_POWERPC_970FX_v10 = 0x00391100,
  5945 + CPU_POWERPC_970FX_v20 = 0x003C0200,
  5946 + CPU_POWERPC_970FX_v21 = 0x003C0201,
  5947 + CPU_POWERPC_970FX_v30 = 0x003C0300,
  5948 + CPU_POWERPC_970FX_v31 = 0x003C0301,
  5949 + CPU_POWERPC_970GX = 0x00450000,
  5950 +#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
  5951 + CPU_POWERPC_970MP_v10 = 0x00440100,
  5952 + CPU_POWERPC_970MP_v11 = 0x00440101,
  5953 +#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
  5954 + CPU_POWERPC_CELL_v10 = 0x00700100,
  5955 + CPU_POWERPC_CELL_v20 = 0x00700400,
  5956 + CPU_POWERPC_CELL_v30 = 0x00700500,
  5957 + CPU_POWERPC_CELL_v31 = 0x00700501,
  5958 +#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
  5959 + CPU_POWERPC_RS64 = 0x00330000,
  5960 + CPU_POWERPC_RS64II = 0x00340000,
  5961 + CPU_POWERPC_RS64III = 0x00360000,
  5962 + CPU_POWERPC_RS64IV = 0x00370000,
5099 5963 #endif /* defined(TARGET_PPC64) */
5100 5964 /* Original POWER */
5101 5965 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
5102 5966 * POWER2 (RIOS2) & RSC2 (P2SC) here
5103 5967 */
5104 5968 #if 0
5105   - CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
  5969 + CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
5106 5970 #endif
5107 5971 #if 0
5108   - CPU_POWER2 = xxx, /* 0x40000 ? */
  5972 + CPU_POWER2 = xxx, /* 0x40000 ? */
5109 5973 #endif
5110 5974 /* PA Semi core */
5111   - CPU_POWERPC_PA6T = 0x00900000,
  5975 + CPU_POWERPC_PA6T = 0x00900000,
5112 5976 };
5113 5977  
5114 5978 /* System version register (used on MPC 8xxx) */
5115 5979 enum {
5116   - PPC_SVR_5200_v10 = 0x80110010,
5117   - PPC_SVR_5200_v11 = 0x80110011,
5118   - PPC_SVR_5200_v12 = 0x80110012,
5119   - PPC_SVR_5200B_v20 = 0x80110020,
5120   - PPC_SVR_5200B_v21 = 0x80110021,
  5980 + POWERPC_SVR_NONE = 0x00000000,
  5981 +#define POWERPC_SVR_52xx POWERPC_SVR_5200
  5982 +#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
  5983 + POWERPC_SVR_5200_v10 = 0x80110010,
  5984 + POWERPC_SVR_5200_v11 = 0x80110011,
  5985 + POWERPC_SVR_5200_v12 = 0x80110012,
  5986 +#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
  5987 + POWERPC_SVR_5200B_v20 = 0x80110020,
  5988 + POWERPC_SVR_5200B_v21 = 0x80110021,
  5989 +#define POWERPC_SVR_55xx POWERPC_SVR_5567
5121 5990 #if 0
5122   - PPC_SVR_5533 = xxx,
  5991 + POWERPC_SVR_5533 = xxx,
5123 5992 #endif
5124 5993 #if 0
5125   - PPC_SVR_5534 = xxx,
  5994 + POWERPC_SVR_5534 = xxx,
5126 5995 #endif
5127 5996 #if 0
5128   - PPC_SVR_5553 = xxx,
  5997 + POWERPC_SVR_5553 = xxx,
5129 5998 #endif
5130 5999 #if 0
5131   - PPC_SVR_5554 = xxx,
  6000 + POWERPC_SVR_5554 = xxx,
5132 6001 #endif
5133 6002 #if 0
5134   - PPC_SVR_5561 = xxx,
  6003 + POWERPC_SVR_5561 = xxx,
5135 6004 #endif
5136 6005 #if 0
5137   - PPC_SVR_5565 = xxx,
  6006 + POWERPC_SVR_5565 = xxx,
5138 6007 #endif
5139 6008 #if 0
5140   - PPC_SVR_5566 = xxx,
  6009 + POWERPC_SVR_5566 = xxx,
5141 6010 #endif
5142 6011 #if 0
5143   - PPC_SVR_5567 = xxx,
  6012 + POWERPC_SVR_5567 = xxx,
5144 6013 #endif
5145 6014 #if 0
5146   - PPC_SVR_8313 = xxx,
  6015 + POWERPC_SVR_8313 = xxx,
5147 6016 #endif
5148 6017 #if 0
5149   - PPC_SVR_8313E = xxx,
  6018 + POWERPC_SVR_8313E = xxx,
5150 6019 #endif
5151 6020 #if 0
5152   - PPC_SVR_8314 = xxx,
  6021 + POWERPC_SVR_8314 = xxx,
5153 6022 #endif
5154 6023 #if 0
5155   - PPC_SVR_8314E = xxx,
  6024 + POWERPC_SVR_8314E = xxx,
5156 6025 #endif
5157 6026 #if 0
5158   - PPC_SVR_8315 = xxx,
  6027 + POWERPC_SVR_8315 = xxx,
5159 6028 #endif
5160 6029 #if 0
5161   - PPC_SVR_8315E = xxx,
  6030 + POWERPC_SVR_8315E = xxx,
5162 6031 #endif
5163 6032 #if 0
5164   - PPC_SVR_8321 = xxx,
  6033 + POWERPC_SVR_8321 = xxx,
5165 6034 #endif
5166 6035 #if 0
5167   - PPC_SVR_8321E = xxx,
  6036 + POWERPC_SVR_8321E = xxx,
5168 6037 #endif
5169 6038 #if 0
5170   - PPC_SVR_8323 = xxx,
  6039 + POWERPC_SVR_8323 = xxx,
5171 6040 #endif
5172 6041 #if 0
5173   - PPC_SVR_8323E = xxx,
5174   -#endif
5175   - PPC_SVR_8343A = 0x80570030,
5176   - PPC_SVR_8343EA = 0x80560030,
5177   - PPC_SVR_8347AP = 0x80550030, /* PBGA package */
5178   - PPC_SVR_8347AT = 0x80530030, /* TBGA package */
5179   - PPC_SVR_8347EAP = 0x80540030, /* PBGA package */
5180   - PPC_SVR_8347EAT = 0x80520030, /* TBGA package */
5181   - PPC_SVR_8349 = 0x80510010,
5182   - PPC_SVR_8349A = 0x80510030,
5183   - PPC_SVR_8349E = 0x80500010,
5184   - PPC_SVR_8349EA = 0x80500030,
  6042 + POWERPC_SVR_8323E = xxx,
  6043 +#endif
  6044 + POWERPC_SVR_8343A = 0x80570030,
  6045 + POWERPC_SVR_8343EA = 0x80560030,
  6046 +#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
  6047 + POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
  6048 + POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
  6049 +#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
  6050 + POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
  6051 + POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
  6052 + POWERPC_SVR_8349 = 0x80510010,
  6053 + POWERPC_SVR_8349A = 0x80510030,
  6054 + POWERPC_SVR_8349E = 0x80500010,
  6055 + POWERPC_SVR_8349EA = 0x80500030,
5185 6056 #if 0
5186   - PPC_SVR_8358E = xxx,
  6057 + POWERPC_SVR_8358E = xxx,
5187 6058 #endif
5188 6059 #if 0
5189   - PPC_SVR_8360E = xxx,
5190   -#endif
5191   - PPC_SVR_8377 = 0x80C70010,
5192   - PPC_SVR_8377E = 0x80C60010,
5193   - PPC_SVR_8378 = 0x80C50010,
5194   - PPC_SVR_8378E = 0x80C40010,
5195   - PPC_SVR_8379 = 0x80C30010,
5196   - PPC_SVR_8379E = 0x80C00010,
5197   - PPC_SVR_8533_v10 = 0x80340010,
5198   - PPC_SVR_8533_v11 = 0x80340011,
5199   - PPC_SVR_8533E_v10 = 0x803C0010,
5200   - PPC_SVR_8533E_v11 = 0x803C0011,
5201   - PPC_SVR_8540_v10 = 0x80300010,
5202   - PPC_SVR_8540_v20 = 0x80300020,
5203   - PPC_SVR_8540_v21 = 0x80300021,
5204   - PPC_SVR_8541_v10 = 0x80720010,
5205   - PPC_SVR_8541_v11 = 0x80720011,
5206   - PPC_SVR_8541E_v10 = 0x807A0010,
5207   - PPC_SVR_8541E_v11 = 0x807A0011,
5208   - PPC_SVR_8543_v10 = 0x80320010,
5209   - PPC_SVR_8543_v11 = 0x80320011,
5210   - PPC_SVR_8543_v20 = 0x80320020,
5211   - PPC_SVR_8543_v21 = 0x80320021,
5212   - PPC_SVR_8543E_v10 = 0x803A0010,
5213   - PPC_SVR_8543E_v11 = 0x803A0011,
5214   - PPC_SVR_8543E_v20 = 0x803A0020,
5215   - PPC_SVR_8543E_v21 = 0x803A0021,
5216   - PPC_SVR_8544_v10 = 0x80340110,
5217   - PPC_SVR_8544_v11 = 0x80340111,
5218   - PPC_SVR_8544E_v10 = 0x803C0110,
5219   - PPC_SVR_8544E_v11 = 0x803C0111,
5220   - PPC_SVR_8545_v20 = 0x80310220,
5221   - PPC_SVR_8545_v21 = 0x80310221,
5222   - PPC_SVR_8545E_v20 = 0x80390220,
5223   - PPC_SVR_8545E_v21 = 0x80390221,
5224   - PPC_SVR_8547E_v20 = 0x80390120,
5225   - PPC_SVR_8547E_v21 = 0x80390121,
5226   - PPC_SCR_8548_v10 = 0x80310010,
5227   - PPC_SCR_8548_v11 = 0x80310011,
5228   - PPC_SCR_8548_v20 = 0x80310020,
5229   - PPC_SCR_8548_v21 = 0x80310021,
5230   - PPC_SVR_8548E_v10 = 0x80390010,
5231   - PPC_SVR_8548E_v11 = 0x80390011,
5232   - PPC_SVR_8548E_v20 = 0x80390020,
5233   - PPC_SVR_8548E_v21 = 0x80390021,
5234   - PPC_SVR_8555_v10 = 0x80710010,
5235   - PPC_SVR_8555_v11 = 0x80710011,
5236   - PPC_SVR_8555E_v10 = 0x80790010,
5237   - PPC_SVR_8555E_v11 = 0x80790011,
5238   - PPC_SVR_8560_v10 = 0x80700010,
5239   - PPC_SVR_8560_v20 = 0x80700020,
5240   - PPC_SVR_8560_v21 = 0x80700021,
5241   - PPC_SVR_8567 = 0x80750111,
5242   - PPC_SVR_8567E = 0x807D0111,
5243   - PPC_SVR_8568 = 0x80750011,
5244   - PPC_SVR_8568E = 0x807D0011,
5245   - PPC_SVR_8572 = 0x80E00010,
5246   - PPC_SVR_8572E = 0x80E80010,
  6060 + POWERPC_SVR_8360E = xxx,
  6061 +#endif
  6062 +#define POWERPC_SVR_E500 0x40000000
  6063 + POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
  6064 + POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
  6065 + POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
  6066 + POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
  6067 + POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
  6068 + POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
  6069 +#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
  6070 + POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
  6071 + POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
  6072 +#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
  6073 + POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
  6074 + POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
  6075 +#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
  6076 + POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
  6077 + POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
  6078 + POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
  6079 +#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
  6080 + POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
  6081 + POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
  6082 +#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
  6083 + POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
  6084 + POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
  6085 +#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
  6086 + POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
  6087 + POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
  6088 + POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
  6089 + POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
  6090 +#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
  6091 + POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
  6092 + POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
  6093 + POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
  6094 + POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
  6095 +#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
  6096 + POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
  6097 + POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
  6098 +#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
  6099 + POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
  6100 + POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
  6101 +#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
  6102 + POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
  6103 + POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
  6104 +#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
  6105 + POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
  6106 + POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
  6107 +#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
  6108 + POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
  6109 + POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
  6110 +#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
  6111 + POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
  6112 + POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
  6113 + POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
  6114 + POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
  6115 +#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
  6116 + POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
  6117 + POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
  6118 + POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
  6119 + POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
  6120 +#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
  6121 + POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
  6122 + POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
  6123 +#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
  6124 + POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
  6125 + POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
  6126 +#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
  6127 + POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
  6128 + POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
  6129 + POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
  6130 + POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
  6131 + POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
  6132 + POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
  6133 + POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
  6134 + POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
  6135 + POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
5247 6136 #if 0
5248   - PPC_SVR_8610 = xxx,
  6137 + POWERPC_SVR_8610 = xxx,
5249 6138 #endif
5250   - PPC_SVR_8641 = 0x80900021,
5251   - PPC_SVR_8641D = 0x80900121,
  6139 + POWERPC_SVR_8641 = 0x80900021,
  6140 + POWERPC_SVR_8641D = 0x80900121,
5252 6141 };
5253 6142  
5254 6143 /*****************************************************************************/
5255 6144 /* PowerPC CPU definitions */
5256   -#define POWERPC_DEF(_name, _pvr, _type) \
  6145 +#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
5257 6146 { \
5258 6147 .name = _name, \
5259 6148 .pvr = _pvr, \
  6149 + .svr = _svr, \
5260 6150 .insns_flags = glue(POWERPC_INSNS_,_type), \
5261 6151 .msr_mask = glue(POWERPC_MSRM_,_type), \
5262 6152 .mmu_model = glue(POWERPC_MMU_,_type), \
... ... @@ -5267,862 +6157,1551 @@ enum {
5267 6157 .init_proc = &glue(init_proc_,_type), \
5268 6158 .check_pow = &glue(check_pow_,_type), \
5269 6159 }
  6160 +#define POWERPC_DEF(_name, _pvr, _type) \
  6161 +POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
5270 6162  
5271 6163 static const ppc_def_t ppc_defs[] = {
5272 6164 /* Embedded PowerPC */
5273 6165 /* PowerPC 401 family */
5274 6166 /* Generic PowerPC 401 */
5275   - POWERPC_DEF("401", CPU_POWERPC_401, 401),
  6167 + POWERPC_DEF("401", CPU_POWERPC_401, 401),
5276 6168 /* PowerPC 401 cores */
5277 6169 /* PowerPC 401A1 */
5278   - POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
  6170 + POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
5279 6171 /* PowerPC 401B2 */
5280   - POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
  6172 + POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
5281 6173 #if defined (TODO)
5282 6174 /* PowerPC 401B3 */
5283   - POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
  6175 + POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
5284 6176 #endif
5285 6177 /* PowerPC 401C2 */
5286   - POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
  6178 + POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
5287 6179 /* PowerPC 401D2 */
5288   - POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
  6180 + POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
5289 6181 /* PowerPC 401E2 */
5290   - POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
  6182 + POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
5291 6183 /* PowerPC 401F2 */
5292   - POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
  6184 + POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
5293 6185 /* PowerPC 401G2 */
5294 6186 /* XXX: to be checked */
5295   - POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
  6187 + POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
5296 6188 /* PowerPC 401 microcontrolers */
5297 6189 #if defined (TODO)
5298 6190 /* PowerPC 401GF */
5299   - POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
  6191 + POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
5300 6192 #endif
5301 6193 /* IOP480 (401 microcontroler) */
5302   - POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
  6194 + POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
5303 6195 /* IBM Processor for Network Resources */
5304   - POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
  6196 + POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
5305 6197 #if defined (TODO)
5306   - POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
  6198 + POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
5307 6199 #endif
5308 6200 /* PowerPC 403 family */
5309 6201 /* Generic PowerPC 403 */
5310   - POWERPC_DEF("403", CPU_POWERPC_403, 403),
  6202 + POWERPC_DEF("403", CPU_POWERPC_403, 403),
5311 6203 /* PowerPC 403 microcontrolers */
5312 6204 /* PowerPC 403 GA */
5313   - POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
  6205 + POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
5314 6206 /* PowerPC 403 GB */
5315   - POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
  6207 + POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
5316 6208 /* PowerPC 403 GC */
5317   - POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
  6209 + POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
5318 6210 /* PowerPC 403 GCX */
5319   - POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
  6211 + POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
5320 6212 #if defined (TODO)
5321 6213 /* PowerPC 403 GP */
5322   - POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
  6214 + POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
5323 6215 #endif
5324 6216 /* PowerPC 405 family */
5325 6217 /* Generic PowerPC 405 */
5326   - POWERPC_DEF("405", CPU_POWERPC_405, 405),
  6218 + POWERPC_DEF("405", CPU_POWERPC_405, 405),
5327 6219 /* PowerPC 405 cores */
5328 6220 #if defined (TODO)
5329 6221 /* PowerPC 405 A3 */
5330   - POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
  6222 + POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
5331 6223 #endif
5332 6224 #if defined (TODO)
5333 6225 /* PowerPC 405 A4 */
5334   - POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
  6226 + POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
5335 6227 #endif
5336 6228 #if defined (TODO)
5337 6229 /* PowerPC 405 B3 */
5338   - POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
  6230 + POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
5339 6231 #endif
5340 6232 #if defined (TODO)
5341 6233 /* PowerPC 405 B4 */
5342   - POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
  6234 + POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
5343 6235 #endif
5344 6236 #if defined (TODO)
5345 6237 /* PowerPC 405 C3 */
5346   - POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
  6238 + POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
5347 6239 #endif
5348 6240 #if defined (TODO)
5349 6241 /* PowerPC 405 C4 */
5350   - POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
  6242 + POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
5351 6243 #endif
5352 6244 /* PowerPC 405 D2 */
5353   - POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
  6245 + POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
5354 6246 #if defined (TODO)
5355 6247 /* PowerPC 405 D3 */
5356   - POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
  6248 + POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
5357 6249 #endif
5358 6250 /* PowerPC 405 D4 */
5359   - POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
  6251 + POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
5360 6252 #if defined (TODO)
5361 6253 /* PowerPC 405 D5 */
5362   - POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
  6254 + POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
5363 6255 #endif
5364 6256 #if defined (TODO)
5365 6257 /* PowerPC 405 E4 */
5366   - POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
  6258 + POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
5367 6259 #endif
5368 6260 #if defined (TODO)
5369 6261 /* PowerPC 405 F4 */
5370   - POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
  6262 + POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
5371 6263 #endif
5372 6264 #if defined (TODO)
5373 6265 /* PowerPC 405 F5 */
5374   - POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
  6266 + POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
5375 6267 #endif
5376 6268 #if defined (TODO)
5377 6269 /* PowerPC 405 F6 */
5378   - POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
  6270 + POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
5379 6271 #endif
5380 6272 /* PowerPC 405 microcontrolers */
5381 6273 /* PowerPC 405 CR */
5382   - POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
  6274 + POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
5383 6275 /* PowerPC 405 CRa */
5384   - POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
  6276 + POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
5385 6277 /* PowerPC 405 CRb */
5386   - POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
  6278 + POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
5387 6279 /* PowerPC 405 CRc */
5388   - POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
  6280 + POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
5389 6281 /* PowerPC 405 EP */
5390   - POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
  6282 + POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
5391 6283 #if defined(TODO)
5392 6284 /* PowerPC 405 EXr */
5393   - POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
  6285 + POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
5394 6286 #endif
5395 6287 /* PowerPC 405 EZ */
5396   - POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
  6288 + POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
5397 6289 #if defined(TODO)
5398 6290 /* PowerPC 405 FX */
5399   - POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
  6291 + POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
5400 6292 #endif
5401 6293 /* PowerPC 405 GP */
5402   - POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
  6294 + POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
5403 6295 /* PowerPC 405 GPa */
5404   - POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
  6296 + POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
5405 6297 /* PowerPC 405 GPb */
5406   - POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
  6298 + POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
5407 6299 /* PowerPC 405 GPc */
5408   - POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
  6300 + POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
5409 6301 /* PowerPC 405 GPd */
5410   - POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
  6302 + POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
5411 6303 /* PowerPC 405 GPe */
5412   - POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
  6304 + POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
5413 6305 /* PowerPC 405 GPR */
5414   - POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
  6306 + POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
5415 6307 #if defined(TODO)
5416 6308 /* PowerPC 405 H */
5417   - POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
  6309 + POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
5418 6310 #endif
5419 6311 #if defined(TODO)
5420 6312 /* PowerPC 405 L */
5421   - POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
  6313 + POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
5422 6314 #endif
5423 6315 /* PowerPC 405 LP */
5424   - POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
  6316 + POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
5425 6317 #if defined(TODO)
5426 6318 /* PowerPC 405 PM */
5427   - POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
  6319 + POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
5428 6320 #endif
5429 6321 #if defined(TODO)
5430 6322 /* PowerPC 405 PS */
5431   - POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
  6323 + POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
5432 6324 #endif
5433 6325 #if defined(TODO)
5434 6326 /* PowerPC 405 S */
5435   - POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
  6327 + POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
5436 6328 #endif
5437 6329 /* Npe405 H */
5438   - POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
  6330 + POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
5439 6331 /* Npe405 H2 */
5440   - POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
  6332 + POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
5441 6333 /* Npe405 L */
5442   - POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
  6334 + POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
5443 6335 /* Npe4GS3 */
5444   - POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
  6336 + POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
5445 6337 #if defined (TODO)
5446   - POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
  6338 + POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
5447 6339 #endif
5448 6340 #if defined (TODO)
5449   - POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
  6341 + POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
5450 6342 #endif
5451 6343 #if defined (TODO)
5452 6344 /* PowerPC LC77700 (Sanyo) */
5453   - POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
  6345 + POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
5454 6346 #endif
5455 6347 /* PowerPC 401/403/405 based set-top-box microcontrolers */
5456 6348 #if defined (TODO)
5457 6349 /* STB010000 */
5458   - POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
  6350 + POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
5459 6351 #endif
5460 6352 #if defined (TODO)
5461 6353 /* STB01010 */
5462   - POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
  6354 + POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
5463 6355 #endif
5464 6356 #if defined (TODO)
5465 6357 /* STB0210 */
5466   - POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
  6358 + POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
5467 6359 #endif
5468 6360 /* STB03xx */
5469   - POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
  6361 + POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
5470 6362 #if defined (TODO)
5471 6363 /* STB043x */
5472   - POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
  6364 + POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
5473 6365 #endif
5474 6366 #if defined (TODO)
5475 6367 /* STB045x */
5476   - POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
  6368 + POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
5477 6369 #endif
5478 6370 /* STB04xx */
5479   - POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
  6371 + POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
5480 6372 /* STB25xx */
5481   - POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
  6373 + POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
5482 6374 #if defined (TODO)
5483 6375 /* STB130 */
5484   - POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
  6376 + POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
5485 6377 #endif
5486 6378 /* Xilinx PowerPC 405 cores */
5487   - POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
5488   - POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
5489   - POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
5490   - POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
  6379 + POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
  6380 + POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
  6381 + POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
  6382 + POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
5491 6383 #if defined (TODO)
5492 6384 /* Zarlink ZL10310 */
5493   - POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
  6385 + POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
5494 6386 #endif
5495 6387 #if defined (TODO)
5496 6388 /* Zarlink ZL10311 */
5497   - POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
  6389 + POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
5498 6390 #endif
5499 6391 #if defined (TODO)
5500 6392 /* Zarlink ZL10320 */
5501   - POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
  6393 + POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
5502 6394 #endif
5503 6395 #if defined (TODO)
5504 6396 /* Zarlink ZL10321 */
5505   - POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
  6397 + POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
5506 6398 #endif
5507 6399 /* PowerPC 440 family */
  6400 +#if defined(TODO_USER_ONLY)
5508 6401 /* Generic PowerPC 440 */
5509   - POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
  6402 + POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
  6403 +#endif
5510 6404 /* PowerPC 440 cores */
5511 6405 #if defined (TODO)
5512 6406 /* PowerPC 440 A4 */
5513   - POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
  6407 + POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
5514 6408 #endif
5515 6409 #if defined (TODO)
5516 6410 /* PowerPC 440 A5 */
5517   - POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
  6411 + POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
5518 6412 #endif
5519 6413 #if defined (TODO)
5520 6414 /* PowerPC 440 B4 */
5521   - POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
  6415 + POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
5522 6416 #endif
5523 6417 #if defined (TODO)
5524 6418 /* PowerPC 440 G4 */
5525   - POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
  6419 + POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
5526 6420 #endif
5527 6421 #if defined (TODO)
5528 6422 /* PowerPC 440 F5 */
5529   - POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
  6423 + POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
5530 6424 #endif
5531 6425 #if defined (TODO)
5532 6426 /* PowerPC 440 G5 */
5533   - POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
  6427 + POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
5534 6428 #endif
5535 6429 #if defined (TODO)
5536 6430 /* PowerPC 440H4 */
5537   - POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
  6431 + POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
5538 6432 #endif
5539 6433 #if defined (TODO)
5540 6434 /* PowerPC 440H6 */
5541   - POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
  6435 + POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
5542 6436 #endif
5543 6437 /* PowerPC 440 microcontrolers */
  6438 +#if defined(TODO_USER_ONLY)
5544 6439 /* PowerPC 440 EP */
5545   - POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
  6440 + POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
  6441 +#endif
  6442 +#if defined(TODO_USER_ONLY)
5546 6443 /* PowerPC 440 EPa */
5547   - POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
  6444 + POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
  6445 +#endif
  6446 +#if defined(TODO_USER_ONLY)
5548 6447 /* PowerPC 440 EPb */
5549   - POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
  6448 + POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
  6449 +#endif
  6450 +#if defined(TODO_USER_ONLY)
5550 6451 /* PowerPC 440 EPX */
5551   - POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
  6452 + POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
  6453 +#endif
  6454 +#if defined(TODO_USER_ONLY)
5552 6455 /* PowerPC 440 GP */
5553   - POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
  6456 + POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
  6457 +#endif
  6458 +#if defined(TODO_USER_ONLY)
5554 6459 /* PowerPC 440 GPb */
5555   - POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
  6460 + POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
  6461 +#endif
  6462 +#if defined(TODO_USER_ONLY)
5556 6463 /* PowerPC 440 GPc */
5557   - POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
  6464 + POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
  6465 +#endif
  6466 +#if defined(TODO_USER_ONLY)
5558 6467 /* PowerPC 440 GR */
5559   - POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
  6468 + POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
  6469 +#endif
  6470 +#if defined(TODO_USER_ONLY)
5560 6471 /* PowerPC 440 GRa */
5561   - POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
  6472 + POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
  6473 +#endif
  6474 +#if defined(TODO_USER_ONLY)
5562 6475 /* PowerPC 440 GRX */
5563   - POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
  6476 + POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
  6477 +#endif
  6478 +#if defined(TODO_USER_ONLY)
5564 6479 /* PowerPC 440 GX */
5565   - POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
  6480 + POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
  6481 +#endif
  6482 +#if defined(TODO_USER_ONLY)
5566 6483 /* PowerPC 440 GXa */
5567   - POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
  6484 + POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
  6485 +#endif
  6486 +#if defined(TODO_USER_ONLY)
5568 6487 /* PowerPC 440 GXb */
5569   - POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
  6488 + POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
  6489 +#endif
  6490 +#if defined(TODO_USER_ONLY)
5570 6491 /* PowerPC 440 GXc */
5571   - POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
  6492 + POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
  6493 +#endif
  6494 +#if defined(TODO_USER_ONLY)
5572 6495 /* PowerPC 440 GXf */
5573   - POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
  6496 + POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
  6497 +#endif
5574 6498 #if defined(TODO)
5575 6499 /* PowerPC 440 S */
5576   - POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
  6500 + POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
5577 6501 #endif
  6502 +#if defined(TODO_USER_ONLY)
5578 6503 /* PowerPC 440 SP */
5579   - POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
  6504 + POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
  6505 +#endif
  6506 +#if defined(TODO_USER_ONLY)
5580 6507 /* PowerPC 440 SP2 */
5581   - POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
  6508 + POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
  6509 +#endif
  6510 +#if defined(TODO_USER_ONLY)
5582 6511 /* PowerPC 440 SPE */
5583   - POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
  6512 + POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
  6513 +#endif
5584 6514 /* PowerPC 460 family */
5585 6515 #if defined (TODO)
5586 6516 /* Generic PowerPC 464 */
5587   - POWERPC_DEF("464", CPU_POWERPC_464, 460),
  6517 + POWERPC_DEF("464", CPU_POWERPC_464, 460),
5588 6518 #endif
5589 6519 /* PowerPC 464 microcontrolers */
5590 6520 #if defined (TODO)
5591 6521 /* PowerPC 464H90 */
5592   - POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
  6522 + POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
5593 6523 #endif
5594 6524 #if defined (TODO)
5595 6525 /* PowerPC 464H90F */
5596   - POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
  6526 + POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
5597 6527 #endif
5598 6528 /* Freescale embedded PowerPC cores */
  6529 + /* MPC5xx family (aka RCPU) */
  6530 +#if defined(TODO_USER_ONLY)
  6531 + /* Generic MPC5xx core */
  6532 + POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
  6533 +#endif
  6534 +#if defined(TODO_USER_ONLY)
  6535 + /* Codename for MPC5xx core */
  6536 + POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
  6537 +#endif
  6538 + /* MPC5xx microcontrollers */
  6539 +#if defined(TODO_USER_ONLY)
  6540 + /* MGT560 */
  6541 + POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
  6542 +#endif
  6543 +#if defined(TODO_USER_ONLY)
  6544 + /* MPC509 */
  6545 + POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
  6546 +#endif
  6547 +#if defined(TODO_USER_ONLY)
  6548 + /* MPC533 */
  6549 + POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
  6550 +#endif
  6551 +#if defined(TODO_USER_ONLY)
  6552 + /* MPC534 */
  6553 + POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
  6554 +#endif
  6555 +#if defined(TODO_USER_ONLY)
  6556 + /* MPC555 */
  6557 + POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
  6558 +#endif
  6559 +#if defined(TODO_USER_ONLY)
  6560 + /* MPC556 */
  6561 + POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
  6562 +#endif
  6563 +#if defined(TODO_USER_ONLY)
  6564 + /* MPC560 */
  6565 + POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
  6566 +#endif
  6567 +#if defined(TODO_USER_ONLY)
  6568 + /* MPC561 */
  6569 + POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
  6570 +#endif
  6571 +#if defined(TODO_USER_ONLY)
  6572 + /* MPC562 */
  6573 + POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
  6574 +#endif
  6575 +#if defined(TODO_USER_ONLY)
  6576 + /* MPC563 */
  6577 + POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
  6578 +#endif
  6579 +#if defined(TODO_USER_ONLY)
  6580 + /* MPC564 */
  6581 + POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
  6582 +#endif
  6583 +#if defined(TODO_USER_ONLY)
  6584 + /* MPC565 */
  6585 + POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
  6586 +#endif
  6587 +#if defined(TODO_USER_ONLY)
  6588 + /* MPC566 */
  6589 + POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
  6590 +#endif
  6591 + /* MPC8xx family (aka PowerQUICC) */
  6592 +#if defined(TODO_USER_ONLY)
  6593 + /* Generic MPC8xx core */
  6594 + POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
  6595 +#endif
  6596 +#if defined(TODO_USER_ONLY)
  6597 + /* Codename for MPC8xx core */
  6598 + POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
  6599 +#endif
  6600 + /* MPC8xx microcontrollers */
  6601 +#if defined(TODO_USER_ONLY)
  6602 + /* MGT823 */
  6603 + POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
  6604 +#endif
  6605 +#if defined(TODO_USER_ONLY)
  6606 + /* MPC821 */
  6607 + POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
  6608 +#endif
  6609 +#if defined(TODO_USER_ONLY)
  6610 + /* MPC823 */
  6611 + POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
  6612 +#endif
  6613 +#if defined(TODO_USER_ONLY)
  6614 + /* MPC850 */
  6615 + POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
  6616 +#endif
  6617 +#if defined(TODO_USER_ONLY)
  6618 + /* MPC852T */
  6619 + POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
  6620 +#endif
  6621 +#if defined(TODO_USER_ONLY)
  6622 + /* MPC855T */
  6623 + POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
  6624 +#endif
  6625 +#if defined(TODO_USER_ONLY)
  6626 + /* MPC857 */
  6627 + POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
  6628 +#endif
  6629 +#if defined(TODO_USER_ONLY)
  6630 + /* MPC859 */
  6631 + POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
  6632 +#endif
  6633 +#if defined(TODO_USER_ONLY)
  6634 + /* MPC860 */
  6635 + POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
  6636 +#endif
  6637 +#if defined(TODO_USER_ONLY)
  6638 + /* MPC862 */
  6639 + POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
  6640 +#endif
  6641 +#if defined(TODO_USER_ONLY)
  6642 + /* MPC866 */
  6643 + POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
  6644 +#endif
  6645 +#if defined(TODO_USER_ONLY)
  6646 + /* MPC870 */
  6647 + POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
  6648 +#endif
  6649 +#if defined(TODO_USER_ONLY)
  6650 + /* MPC875 */
  6651 + POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
  6652 +#endif
  6653 +#if defined(TODO_USER_ONLY)
  6654 + /* MPC880 */
  6655 + POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
  6656 +#endif
  6657 +#if defined(TODO_USER_ONLY)
  6658 + /* MPC885 */
  6659 + POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
  6660 +#endif
  6661 + /* MPC82xx family (aka PowerQUICC-II) */
  6662 + /* Generic MPC52xx core */
  6663 + POWERPC_DEF_SVR("MPC52xx",
  6664 + CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
  6665 + /* Generic MPC82xx core */
  6666 + POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
  6667 + /* Codename for MPC82xx */
  6668 + POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
  6669 + /* PowerPC G2 core */
  6670 + POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
  6671 + /* PowerPC G2 H4 core */
  6672 + POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
  6673 + /* PowerPC G2 GP core */
  6674 + POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
  6675 + /* PowerPC G2 LS core */
  6676 + POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
  6677 + /* PowerPC G2 HiP3 core */
  6678 + POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
  6679 + /* PowerPC G2 HiP4 core */
  6680 + POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
  6681 + /* PowerPC MPC603 core */
  6682 + POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
  6683 + /* PowerPC G2le core (same as G2 plus little-endian mode support) */
  6684 + POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
  6685 + /* PowerPC G2LE GP core */
  6686 + POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
  6687 + /* PowerPC G2LE LS core */
  6688 + POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
  6689 + /* PowerPC G2LE GP1 core */
  6690 + POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
  6691 + /* PowerPC G2LE GP3 core */
  6692 + POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
  6693 + /* PowerPC MPC603 microcontrollers */
  6694 + /* MPC8240 */
  6695 + POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
  6696 + /* PowerPC G2 microcontrollers */
  6697 +#if 0
  6698 + /* MPC5121 */
  6699 + POWERPC_DEF_SVR("MPC5121",
  6700 + CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
  6701 +#endif
  6702 + /* MPC5200 */
  6703 + POWERPC_DEF_SVR("MPC5200",
  6704 + CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
  6705 + /* MPC5200 v1.0 */
  6706 + POWERPC_DEF_SVR("MPC5200_v10",
  6707 + CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
  6708 + /* MPC5200 v1.1 */
  6709 + POWERPC_DEF_SVR("MPC5200_v11",
  6710 + CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
  6711 + /* MPC5200 v1.2 */
  6712 + POWERPC_DEF_SVR("MPC5200_v12",
  6713 + CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
  6714 + /* MPC5200B */
  6715 + POWERPC_DEF_SVR("MPC5200B",
  6716 + CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
  6717 + /* MPC5200B v2.0 */
  6718 + POWERPC_DEF_SVR("MPC5200B_v20",
  6719 + CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
  6720 + /* MPC5200B v2.1 */
  6721 + POWERPC_DEF_SVR("MPC5200B_v21",
  6722 + CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
  6723 + /* MPC8241 */
  6724 + POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
  6725 + /* MPC8245 */
  6726 + POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
  6727 + /* MPC8247 */
  6728 + POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
  6729 + /* MPC8248 */
  6730 + POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
  6731 + /* MPC8250 */
  6732 + POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
  6733 + /* MPC8250 HiP3 */
  6734 + POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
  6735 + /* MPC8250 HiP4 */
  6736 + POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
  6737 + /* MPC8255 */
  6738 + POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
  6739 + /* MPC8255 HiP3 */
  6740 + POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
  6741 + /* MPC8255 HiP4 */
  6742 + POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
  6743 + /* MPC8260 */
  6744 + POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
  6745 + /* MPC8260 HiP3 */
  6746 + POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
  6747 + /* MPC8260 HiP4 */
  6748 + POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
  6749 + /* MPC8264 */
  6750 + POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
  6751 + /* MPC8264 HiP3 */
  6752 + POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
  6753 + /* MPC8264 HiP4 */
  6754 + POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
  6755 + /* MPC8265 */
  6756 + POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
  6757 + /* MPC8265 HiP3 */
  6758 + POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
  6759 + /* MPC8265 HiP4 */
  6760 + POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
  6761 + /* MPC8266 */
  6762 + POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
  6763 + /* MPC8266 HiP3 */
  6764 + POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
  6765 + /* MPC8266 HiP4 */
  6766 + POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
  6767 + /* MPC8270 */
  6768 + POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
  6769 + /* MPC8271 */
  6770 + POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
  6771 + /* MPC8272 */
  6772 + POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
  6773 + /* MPC8275 */
  6774 + POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
  6775 + /* MPC8280 */
  6776 + POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
5599 6777 /* e200 family */
5600   -#if defined (TODO)
5601 6778 /* Generic PowerPC e200 core */
5602   - POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
  6779 + POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
  6780 + /* Generic MPC55xx core */
  6781 +#if defined (TODO)
  6782 + POWERPC_DEF_SVR("MPC55xx",
  6783 + CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
5603 6784 #endif
5604 6785 #if defined (TODO)
5605   - /* PowerPC e200z5 core */
5606   - POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
  6786 + /* PowerPC e200z0 core */
  6787 + POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
  6788 +#endif
  6789 +#if defined (TODO)
  6790 + /* PowerPC e200z1 core */
  6791 + POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
5607 6792 #endif
5608 6793 #if defined (TODO)
  6794 + /* PowerPC e200z3 core */
  6795 + POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
  6796 +#endif
  6797 + /* PowerPC e200z5 core */
  6798 + POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
5609 6799 /* PowerPC e200z6 core */
5610   - POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
  6800 + POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
  6801 + /* PowerPC e200 microcontrollers */
  6802 +#if defined (TODO)
  6803 + /* MPC5514E */
  6804 + POWERPC_DEF_SVR("MPC5514E",
  6805 + CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
5611 6806 #endif
5612   - /* e300 family */
5613 6807 #if defined (TODO)
5614   - /* Generic PowerPC e300 core */
5615   - POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
  6808 + /* MPC5514E v0 */
  6809 + POWERPC_DEF_SVR("MPC5514E_v0",
  6810 + CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
5616 6811 #endif
5617 6812 #if defined (TODO)
5618   - /* PowerPC e300c1 core */
5619   - POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
  6813 + /* MPC5514E v1 */
  6814 + POWERPC_DEF_SVR("MPC5514E_v1",
  6815 + CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
5620 6816 #endif
5621 6817 #if defined (TODO)
5622   - /* PowerPC e300c2 core */
5623   - POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
  6818 + /* MPC5514G */
  6819 + POWERPC_DEF_SVR("MPC5514G",
  6820 + CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
5624 6821 #endif
5625 6822 #if defined (TODO)
5626   - /* PowerPC e300c3 core */
5627   - POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
  6823 + /* MPC5514G v0 */
  6824 + POWERPC_DEF_SVR("MPC5514G_v0",
  6825 + CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
5628 6826 #endif
5629   - /* e500 family */
5630 6827 #if defined (TODO)
5631   - /* PowerPC e500 core */
5632   - POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
  6828 + /* MPC5514G v1 */
  6829 + POWERPC_DEF_SVR("MPC5514G_v1",
  6830 + CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
5633 6831 #endif
5634 6832 #if defined (TODO)
5635   - /* PowerPC e500 v1.1 core */
5636   - POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, e500),
  6833 + /* MPC5515S */
  6834 + POWERPC_DEF_SVR("MPC5515S",
  6835 + CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
5637 6836 #endif
5638 6837 #if defined (TODO)
5639   - /* PowerPC e500 v1.2 core */
5640   - POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, e500),
  6838 + /* MPC5516E */
  6839 + POWERPC_DEF_SVR("MPC5516E",
  6840 + CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
5641 6841 #endif
5642 6842 #if defined (TODO)
5643   - /* PowerPC e500 v2.1 core */
5644   - POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, e500),
  6843 + /* MPC5516E v0 */
  6844 + POWERPC_DEF_SVR("MPC5516E_v0",
  6845 + CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
5645 6846 #endif
5646 6847 #if defined (TODO)
5647   - /* PowerPC e500 v2.2 core */
5648   - POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, e500),
  6848 + /* MPC5516E v1 */
  6849 + POWERPC_DEF_SVR("MPC5516E_v1",
  6850 + CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
5649 6851 #endif
5650   - /* e600 family */
5651 6852 #if defined (TODO)
5652   - /* PowerPC e600 core */
5653   - POWERPC_DEF("e600", CPU_POWERPC_e600, e600),
  6853 + /* MPC5516G */
  6854 + POWERPC_DEF_SVR("MPC5516G",
  6855 + CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
5654 6856 #endif
5655   - /* PowerPC MPC 5xx cores */
5656 6857 #if defined (TODO)
5657   - /* PowerPC MPC 5xx */
5658   - POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 5xx),
  6858 + /* MPC5516G v0 */
  6859 + POWERPC_DEF_SVR("MPC5516G_v0",
  6860 + CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
5659 6861 #endif
5660   - /* PowerPC MPC 8xx cores */
5661 6862 #if defined (TODO)
5662   - /* PowerPC MPC 8xx */
5663   - POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 8xx),
  6863 + /* MPC5516G v1 */
  6864 + POWERPC_DEF_SVR("MPC5516G_v1",
  6865 + CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
5664 6866 #endif
5665   - /* PowerPC MPC 8xxx cores */
5666 6867 #if defined (TODO)
5667   - /* PowerPC MPC 82xx HIP3 */
5668   - POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 82xx),
  6868 + /* MPC5516S */
  6869 + POWERPC_DEF_SVR("MPC5516S",
  6870 + CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
5669 6871 #endif
5670 6872 #if defined (TODO)
5671   - /* PowerPC MPC 82xx HIP4 */
5672   - POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 82xx),
  6873 + /* MPC5533 */
  6874 + POWERPC_DEF_SVR("MPC5533",
  6875 + CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
5673 6876 #endif
5674 6877 #if defined (TODO)
5675   - /* PowerPC MPC 827x */
5676   - POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 827x),
  6878 + /* MPC5534 */
  6879 + POWERPC_DEF_SVR("MPC5534",
  6880 + CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
5677 6881 #endif
5678   -
  6882 +#if defined (TODO)
  6883 + /* MPC5553 */
  6884 + POWERPC_DEF_SVR("MPC5553",
  6885 + CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
  6886 +#endif
  6887 +#if defined (TODO)
  6888 + /* MPC5554 */
  6889 + POWERPC_DEF_SVR("MPC5554",
  6890 + CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
  6891 +#endif
  6892 +#if defined (TODO)
  6893 + /* MPC5561 */
  6894 + POWERPC_DEF_SVR("MPC5561",
  6895 + CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
  6896 +#endif
  6897 +#if defined (TODO)
  6898 + /* MPC5565 */
  6899 + POWERPC_DEF_SVR("MPC5565",
  6900 + CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
  6901 +#endif
  6902 +#if defined (TODO)
  6903 + /* MPC5566 */
  6904 + POWERPC_DEF_SVR("MPC5566",
  6905 + CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
  6906 +#endif
  6907 +#if defined (TODO)
  6908 + /* MPC5567 */
  6909 + POWERPC_DEF_SVR("MPC5567",
  6910 + CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
  6911 +#endif
  6912 + /* e300 family */
  6913 + /* Generic PowerPC e300 core */
  6914 + POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
  6915 + /* PowerPC e300c1 core */
  6916 + POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
  6917 + /* PowerPC e300c2 core */
  6918 + POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
  6919 + /* PowerPC e300c3 core */
  6920 + POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
  6921 + /* PowerPC e300c4 core */
  6922 + POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
  6923 + /* PowerPC e300 microcontrollers */
  6924 +#if defined (TODO)
  6925 + /* MPC8313 */
  6926 + POWERPC_DEF_SVR("MPC8313",
  6927 + CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
  6928 +#endif
  6929 +#if defined (TODO)
  6930 + /* MPC8313E */
  6931 + POWERPC_DEF_SVR("MPC8313E",
  6932 + CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
  6933 +#endif
  6934 +#if defined (TODO)
  6935 + /* MPC8314 */
  6936 + POWERPC_DEF_SVR("MPC8314",
  6937 + CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
  6938 +#endif
  6939 +#if defined (TODO)
  6940 + /* MPC8314E */
  6941 + POWERPC_DEF_SVR("MPC8314E",
  6942 + CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
  6943 +#endif
  6944 +#if defined (TODO)
  6945 + /* MPC8315 */
  6946 + POWERPC_DEF_SVR("MPC8315",
  6947 + CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
  6948 +#endif
  6949 +#if defined (TODO)
  6950 + /* MPC8315E */
  6951 + POWERPC_DEF_SVR("MPC8315E",
  6952 + CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
  6953 +#endif
  6954 +#if defined (TODO)
  6955 + /* MPC8321 */
  6956 + POWERPC_DEF_SVR("MPC8321",
  6957 + CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
  6958 +#endif
  6959 +#if defined (TODO)
  6960 + /* MPC8321E */
  6961 + POWERPC_DEF_SVR("MPC8321E",
  6962 + CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
  6963 +#endif
  6964 +#if defined (TODO)
  6965 + /* MPC8323 */
  6966 + POWERPC_DEF_SVR("MPC8323",
  6967 + CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
  6968 +#endif
  6969 +#if defined (TODO)
  6970 + /* MPC8323E */
  6971 + POWERPC_DEF_SVR("MPC8323E",
  6972 + CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
  6973 +#endif
  6974 + /* MPC8343A */
  6975 + POWERPC_DEF_SVR("MPC8343A",
  6976 + CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
  6977 + /* MPC8343EA */
  6978 + POWERPC_DEF_SVR("MPC8343EA",
  6979 + CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
  6980 + /* MPC8347A */
  6981 + POWERPC_DEF_SVR("MPC8347A",
  6982 + CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
  6983 + /* MPC8347AT */
  6984 + POWERPC_DEF_SVR("MPC8347AT",
  6985 + CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
  6986 + /* MPC8347AP */
  6987 + POWERPC_DEF_SVR("MPC8347AP",
  6988 + CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
  6989 + /* MPC8347EA */
  6990 + POWERPC_DEF_SVR("MPC8347EA",
  6991 + CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
  6992 + /* MPC8347EAT */
  6993 + POWERPC_DEF_SVR("MPC8347EAT",
  6994 + CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
  6995 + /* MPC8343EAP */
  6996 + POWERPC_DEF_SVR("MPC8347EAP",
  6997 + CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
  6998 + /* MPC8349 */
  6999 + POWERPC_DEF_SVR("MPC8349",
  7000 + CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
  7001 + /* MPC8349A */
  7002 + POWERPC_DEF_SVR("MPC8349A",
  7003 + CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
  7004 + /* MPC8349E */
  7005 + POWERPC_DEF_SVR("MPC8349E",
  7006 + CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
  7007 + /* MPC8349EA */
  7008 + POWERPC_DEF_SVR("MPC8349EA",
  7009 + CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
  7010 +#if defined (TODO)
  7011 + /* MPC8358E */
  7012 + POWERPC_DEF_SVR("MPC8358E",
  7013 + CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
  7014 +#endif
  7015 +#if defined (TODO)
  7016 + /* MPC8360E */
  7017 + POWERPC_DEF_SVR("MPC8360E",
  7018 + CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
  7019 +#endif
  7020 + /* MPC8377 */
  7021 + POWERPC_DEF_SVR("MPC8377",
  7022 + CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
  7023 + /* MPC8377E */
  7024 + POWERPC_DEF_SVR("MPC8377E",
  7025 + CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
  7026 + /* MPC8378 */
  7027 + POWERPC_DEF_SVR("MPC8378",
  7028 + CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
  7029 + /* MPC8378E */
  7030 + POWERPC_DEF_SVR("MPC8378E",
  7031 + CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
  7032 + /* MPC8379 */
  7033 + POWERPC_DEF_SVR("MPC8379",
  7034 + CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
  7035 + /* MPC8379E */
  7036 + POWERPC_DEF_SVR("MPC8379E",
  7037 + CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
  7038 + /* e500 family */
  7039 + /* PowerPC e500 core */
  7040 + POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
  7041 + /* PowerPC e500 v1.0 core */
  7042 + POWERPC_DEF("e500_v10", CPU_POWERPC_e500_v10, e500),
  7043 + /* PowerPC e500 v2.0 core */
  7044 + POWERPC_DEF("e500_v20", CPU_POWERPC_e500_v20, e500),
  7045 + /* PowerPC e500v2 core */
  7046 + POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500),
  7047 + /* PowerPC e500v2 v1.0 core */
  7048 + POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500),
  7049 + /* PowerPC e500v2 v2.0 core */
  7050 + POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500),
  7051 + /* PowerPC e500v2 v2.1 core */
  7052 + POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500),
  7053 + /* PowerPC e500v2 v2.2 core */
  7054 + POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500),
  7055 + /* PowerPC e500v2 v3.0 core */
  7056 + POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500),
  7057 + /* PowerPC e500 microcontrollers */
  7058 + /* MPC8533 */
  7059 + POWERPC_DEF_SVR("MPC8533",
  7060 + CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500),
  7061 + /* MPC8533 v1.0 */
  7062 + POWERPC_DEF_SVR("MPC8533_v10",
  7063 + CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500),
  7064 + /* MPC8533 v1.1 */
  7065 + POWERPC_DEF_SVR("MPC8533_v11",
  7066 + CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500),
  7067 + /* MPC8533E */
  7068 + POWERPC_DEF_SVR("MPC8533E",
  7069 + CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500),
  7070 + /* MPC8533E v1.0 */
  7071 + POWERPC_DEF_SVR("MPC8533E_v10",
  7072 + CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
  7073 + POWERPC_DEF_SVR("MPC8533E_v11",
  7074 + CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
  7075 + /* MPC8540 */
  7076 + POWERPC_DEF_SVR("MPC8540",
  7077 + CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500),
  7078 + /* MPC8540 v1.0 */
  7079 + POWERPC_DEF_SVR("MPC8540_v10",
  7080 + CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500),
  7081 + /* MPC8540 v2.0 */
  7082 + POWERPC_DEF_SVR("MPC8540_v20",
  7083 + CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500),
  7084 + /* MPC8540 v2.1 */
  7085 + POWERPC_DEF_SVR("MPC8540_v21",
  7086 + CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500),
  7087 + /* MPC8541 */
  7088 + POWERPC_DEF_SVR("MPC8541",
  7089 + CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500),
  7090 + /* MPC8541 v1.0 */
  7091 + POWERPC_DEF_SVR("MPC8541_v10",
  7092 + CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500),
  7093 + /* MPC8541 v1.1 */
  7094 + POWERPC_DEF_SVR("MPC8541_v11",
  7095 + CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500),
  7096 + /* MPC8541E */
  7097 + POWERPC_DEF_SVR("MPC8541E",
  7098 + CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500),
  7099 + /* MPC8541E v1.0 */
  7100 + POWERPC_DEF_SVR("MPC8541E_v10",
  7101 + CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
  7102 + /* MPC8541E v1.1 */
  7103 + POWERPC_DEF_SVR("MPC8541E_v11",
  7104 + CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
  7105 + /* MPC8543 */
  7106 + POWERPC_DEF_SVR("MPC8543",
  7107 + CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500),
  7108 + /* MPC8543 v1.0 */
  7109 + POWERPC_DEF_SVR("MPC8543_v10",
  7110 + CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500),
  7111 + /* MPC8543 v1.1 */
  7112 + POWERPC_DEF_SVR("MPC8543_v11",
  7113 + CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500),
  7114 + /* MPC8543 v2.0 */
  7115 + POWERPC_DEF_SVR("MPC8543_v20",
  7116 + CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500),
  7117 + /* MPC8543 v2.1 */
  7118 + POWERPC_DEF_SVR("MPC8543_v21",
  7119 + CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500),
  7120 + /* MPC8543E */
  7121 + POWERPC_DEF_SVR("MPC8543E",
  7122 + CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500),
  7123 + /* MPC8543E v1.0 */
  7124 + POWERPC_DEF_SVR("MPC8543E_v10",
  7125 + CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
  7126 + /* MPC8543E v1.1 */
  7127 + POWERPC_DEF_SVR("MPC8543E_v11",
  7128 + CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
  7129 + /* MPC8543E v2.0 */
  7130 + POWERPC_DEF_SVR("MPC8543E_v20",
  7131 + CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
  7132 + /* MPC8543E v2.1 */
  7133 + POWERPC_DEF_SVR("MPC8543E_v21",
  7134 + CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
  7135 + /* MPC8544 */
  7136 + POWERPC_DEF_SVR("MPC8544",
  7137 + CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500),
  7138 + /* MPC8544 v1.0 */
  7139 + POWERPC_DEF_SVR("MPC8544_v10",
  7140 + CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500),
  7141 + /* MPC8544 v1.1 */
  7142 + POWERPC_DEF_SVR("MPC8544_v11",
  7143 + CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500),
  7144 + /* MPC8544E */
  7145 + POWERPC_DEF_SVR("MPC8544E",
  7146 + CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500),
  7147 + /* MPC8544E v1.0 */
  7148 + POWERPC_DEF_SVR("MPC8544E_v10",
  7149 + CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
  7150 + /* MPC8544E v1.1 */
  7151 + POWERPC_DEF_SVR("MPC8544E_v11",
  7152 + CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
  7153 + /* MPC8545 */
  7154 + POWERPC_DEF_SVR("MPC8545",
  7155 + CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500),
  7156 + /* MPC8545 v2.0 */
  7157 + POWERPC_DEF_SVR("MPC8545_v20",
  7158 + CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500),
  7159 + /* MPC8545 v2.1 */
  7160 + POWERPC_DEF_SVR("MPC8545_v21",
  7161 + CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500),
  7162 + /* MPC8545E */
  7163 + POWERPC_DEF_SVR("MPC8545E",
  7164 + CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500),
  7165 + /* MPC8545E v2.0 */
  7166 + POWERPC_DEF_SVR("MPC8545E_v20",
  7167 + CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
  7168 + /* MPC8545E v2.1 */
  7169 + POWERPC_DEF_SVR("MPC8545E_v21",
  7170 + CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
  7171 + /* MPC8547E */
  7172 + POWERPC_DEF_SVR("MPC8547E",
  7173 + CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500),
  7174 + /* MPC8547E v2.0 */
  7175 + POWERPC_DEF_SVR("MPC8547E_v20",
  7176 + CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
  7177 + /* MPC8547E v2.1 */
  7178 + POWERPC_DEF_SVR("MPC8547E_v21",
  7179 + CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
  7180 + /* MPC8548 */
  7181 + POWERPC_DEF_SVR("MPC8548",
  7182 + CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500),
  7183 + /* MPC8548 v1.0 */
  7184 + POWERPC_DEF_SVR("MPC8548_v10",
  7185 + CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500),
  7186 + /* MPC8548 v1.1 */
  7187 + POWERPC_DEF_SVR("MPC8548_v11",
  7188 + CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500),
  7189 + /* MPC8548 v2.0 */
  7190 + POWERPC_DEF_SVR("MPC8548_v20",
  7191 + CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500),
  7192 + /* MPC8548 v2.1 */
  7193 + POWERPC_DEF_SVR("MPC8548_v21",
  7194 + CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500),
  7195 + /* MPC8548E */
  7196 + POWERPC_DEF_SVR("MPC8548E",
  7197 + CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500),
  7198 + /* MPC8548E v1.0 */
  7199 + POWERPC_DEF_SVR("MPC8548E_v10",
  7200 + CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
  7201 + /* MPC8548E v1.1 */
  7202 + POWERPC_DEF_SVR("MPC8548E_v11",
  7203 + CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
  7204 + /* MPC8548E v2.0 */
  7205 + POWERPC_DEF_SVR("MPC8548E_v20",
  7206 + CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
  7207 + /* MPC8548E v2.1 */
  7208 + POWERPC_DEF_SVR("MPC8548E_v21",
  7209 + CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
  7210 + /* MPC8555 */
  7211 + POWERPC_DEF_SVR("MPC8555",
  7212 + CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500),
  7213 + /* MPC8555 v1.0 */
  7214 + POWERPC_DEF_SVR("MPC8555_v10",
  7215 + CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500),
  7216 + /* MPC8555 v1.1 */
  7217 + POWERPC_DEF_SVR("MPC8555_v11",
  7218 + CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500),
  7219 + /* MPC8555E */
  7220 + POWERPC_DEF_SVR("MPC8555E",
  7221 + CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500),
  7222 + /* MPC8555E v1.0 */
  7223 + POWERPC_DEF_SVR("MPC8555E_v10",
  7224 + CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
  7225 + /* MPC8555E v1.1 */
  7226 + POWERPC_DEF_SVR("MPC8555E_v11",
  7227 + CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
  7228 + /* MPC8560 */
  7229 + POWERPC_DEF_SVR("MPC8560",
  7230 + CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500),
  7231 + /* MPC8560 v1.0 */
  7232 + POWERPC_DEF_SVR("MPC8560_v10",
  7233 + CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500),
  7234 + /* MPC8560 v2.0 */
  7235 + POWERPC_DEF_SVR("MPC8560_v20",
  7236 + CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500),
  7237 + /* MPC8560 v2.1 */
  7238 + POWERPC_DEF_SVR("MPC8560_v21",
  7239 + CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500),
  7240 + /* MPC8567 */
  7241 + POWERPC_DEF_SVR("MPC8567",
  7242 + CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500),
  7243 + /* MPC8567E */
  7244 + POWERPC_DEF_SVR("MPC8567E",
  7245 + CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500),
  7246 + /* MPC8568 */
  7247 + POWERPC_DEF_SVR("MPC8568",
  7248 + CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500),
  7249 + /* MPC8568E */
  7250 + POWERPC_DEF_SVR("MPC8568E",
  7251 + CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500),
  7252 + /* MPC8572 */
  7253 + POWERPC_DEF_SVR("MPC8572",
  7254 + CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500),
  7255 + /* MPC8572E */
  7256 + POWERPC_DEF_SVR("MPC8572E",
  7257 + CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500),
  7258 + /* e600 family */
  7259 + /* PowerPC e600 core */
  7260 + POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
  7261 + /* PowerPC e600 microcontrollers */
  7262 +#if defined (TODO)
  7263 + /* MPC8610 */
  7264 + POWERPC_DEF_SVR("MPC8610",
  7265 + CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
  7266 +#endif
  7267 + /* MPC8641 */
  7268 + POWERPC_DEF_SVR("MPC8641",
  7269 + CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
  7270 + /* MPC8641D */
  7271 + POWERPC_DEF_SVR("MPC8641D",
  7272 + CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
5679 7273 /* 32 bits "classic" PowerPC */
5680 7274 /* PowerPC 6xx family */
5681 7275 /* PowerPC 601 */
5682   - POWERPC_DEF("601", CPU_POWERPC_601, 601),
  7276 + POWERPC_DEF("601", CPU_POWERPC_601, 601),
5683 7277 /* PowerPC 601v0 */
5684   - POWERPC_DEF("601v0", CPU_POWERPC_601_v0, 601),
  7278 + POWERPC_DEF("601v0", CPU_POWERPC_601_v0, 601),
5685 7279 /* PowerPC 601v1 */
5686   - POWERPC_DEF("601v1", CPU_POWERPC_601_v1, 601),
  7280 + POWERPC_DEF("601v1", CPU_POWERPC_601_v1, 601),
5687 7281 /* PowerPC 601v2 */
5688   - POWERPC_DEF("601v2", CPU_POWERPC_601_v2, 601),
  7282 + POWERPC_DEF("601v2", CPU_POWERPC_601_v2, 601),
5689 7283 /* PowerPC 602 */
5690   - POWERPC_DEF("602", CPU_POWERPC_602, 602),
  7284 + POWERPC_DEF("602", CPU_POWERPC_602, 602),
5691 7285 /* PowerPC 603 */
5692   - POWERPC_DEF("603", CPU_POWERPC_603, 603),
  7286 + POWERPC_DEF("603", CPU_POWERPC_603, 603),
5693 7287 /* Code name for PowerPC 603 */
5694   - POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
  7288 + POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
5695 7289 /* PowerPC 603e */
5696   - POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
  7290 + POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
5697 7291 /* Code name for PowerPC 603e */
5698   - POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
  7292 + POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
5699 7293 /* PowerPC 603e v1.1 */
5700   - POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 603E),
  7294 + POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
5701 7295 /* PowerPC 603e v1.2 */
5702   - POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 603E),
  7296 + POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
5703 7297 /* PowerPC 603e v1.3 */
5704   - POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 603E),
  7298 + POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
5705 7299 /* PowerPC 603e v1.4 */
5706   - POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 603E),
  7300 + POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
5707 7301 /* PowerPC 603e v2.2 */
5708   - POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 603E),
  7302 + POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
5709 7303 /* PowerPC 603e v3 */
5710   - POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 603E),
  7304 + POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
5711 7305 /* PowerPC 603e v4 */
5712   - POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 603E),
  7306 + POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
5713 7307 /* PowerPC 603e v4.1 */
5714   - POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 603E),
  7308 + POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
5715 7309 /* PowerPC 603e */
5716   - POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
  7310 + POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
5717 7311 /* PowerPC 603e7t */
5718   - POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
  7312 + POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
5719 7313 /* PowerPC 603e7v */
5720   - POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
  7314 + POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
5721 7315 /* Code name for PowerPC 603ev */
5722   - POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
  7316 + POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
5723 7317 /* PowerPC 603e7v1 */
5724   - POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
  7318 + POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
5725 7319 /* PowerPC 603e7v2 */
5726   - POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
  7320 + POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
5727 7321 /* PowerPC 603p */
5728 7322 /* to be checked */
5729   - POWERPC_DEF("603p", CPU_POWERPC_603P, 603),
  7323 + POWERPC_DEF("603p", CPU_POWERPC_603P, 603),
5730 7324 /* PowerPC 603r */
5731   - POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
  7325 + POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
5732 7326 /* Code name for PowerPC 603r */
5733   - POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
5734   - /* PowerPC G2 core */
5735   - POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
5736   - /* PowerPC G2 H4 */
5737   - POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
5738   - /* PowerPC G2 GP */
5739   - POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
5740   - /* PowerPC G2 LS */
5741   - POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
5742   - /* PowerPC G2LE */
5743   - /* Same as G2, with little-endian mode support */
5744   - POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
5745   - /* PowerPC G2LE GP */
5746   - POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
5747   - /* PowerPC G2LE LS */
5748   - POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
  7327 + POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
5749 7328 /* PowerPC 604 */
5750   - POWERPC_DEF("604", CPU_POWERPC_604, 604),
  7329 + POWERPC_DEF("604", CPU_POWERPC_604, 604),
5751 7330 /* PowerPC 604e */
5752 7331 /* XXX: code names "Sirocco" "Mach 5" */
5753   - POWERPC_DEF("604e", CPU_POWERPC_604E, 604),
  7332 + POWERPC_DEF("604e", CPU_POWERPC_604E, 604),
5754 7333 /* PowerPC 604e v1.0 */
5755   - POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 604),
  7334 + POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604),
5756 7335 /* PowerPC 604e v2.2 */
5757   - POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 604),
  7336 + POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604),
5758 7337 /* PowerPC 604e v2.4 */
5759   - POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 604),
  7338 + POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604),
5760 7339 /* PowerPC 604r */
5761   - POWERPC_DEF("604r", CPU_POWERPC_604R, 604),
  7340 + POWERPC_DEF("604r", CPU_POWERPC_604R, 604),
5762 7341 #if defined(TODO)
5763 7342 /* PowerPC 604ev */
5764   - POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604),
  7343 + POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604),
5765 7344 #endif
5766 7345 /* PowerPC 7xx family */
5767 7346 /* Generic PowerPC 740 (G3) */
5768   - POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
  7347 + POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
5769 7348 /* Generic PowerPC 750 (G3) */
5770   - POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
  7349 + POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
5771 7350 /* Code name for generic PowerPC 740/750 (G3) */
5772   - POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
  7351 + POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
5773 7352 /* XXX: 750 codename "Typhoon" */
5774 7353 /* PowerPC 740/750 is also known as G3 */
5775   - POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
  7354 + POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
5776 7355 /* PowerPC 740 v2.0 (G3) */
5777   - POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 7x0),
  7356 + POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 7x0),
5778 7357 /* PowerPC 750 v2.0 (G3) */
5779   - POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 7x0),
  7358 + POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 7x0),
5780 7359 /* PowerPC 740 v2.1 (G3) */
5781   - POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 7x0),
  7360 + POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 7x0),
5782 7361 /* PowerPC 750 v2.1 (G3) */
5783   - POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 7x0),
  7362 + POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 7x0),
5784 7363 /* PowerPC 740 v2.2 (G3) */
5785   - POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 7x0),
  7364 + POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 7x0),
5786 7365 /* PowerPC 750 v2.2 (G3) */
5787   - POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 7x0),
  7366 + POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 7x0),
5788 7367 /* PowerPC 740 v3.0 (G3) */
5789   - POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 7x0),
  7368 + POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 7x0),
5790 7369 /* PowerPC 750 v3.0 (G3) */
5791   - POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 7x0),
  7370 + POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 7x0),
5792 7371 /* PowerPC 740 v3.1 (G3) */
5793   - POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 7x0),
  7372 + POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 7x0),
5794 7373 /* PowerPC 750 v3.1 (G3) */
5795   - POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 7x0),
  7374 + POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 7x0),
5796 7375 /* PowerPC 740E (G3) */
5797   - POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
  7376 + POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
5798 7377 /* PowerPC 740P (G3) */
5799   - POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
  7378 + POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
5800 7379 /* PowerPC 750P (G3) */
5801   - POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
  7380 + POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
5802 7381 /* Code name for PowerPC 740P/750P (G3) */
5803   - POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
  7382 + POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
5804 7383 /* PowerPC 750CL (G3 embedded) */
5805   - POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
  7384 + POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
5806 7385 /* PowerPC 750CX (G3 embedded) */
5807   - POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
  7386 + POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
5808 7387 /* PowerPC 750CX v2.1 (G3 embedded) */
5809   - POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 7x0),
  7388 + POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 7x0),
5810 7389 /* PowerPC 750CX v2.2 (G3 embedded) */
5811   - POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 7x0),
  7390 + POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 7x0),
5812 7391 /* PowerPC 750CXe (G3 embedded) */
5813   - POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
  7392 + POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
5814 7393 /* PowerPC 750CXe v2.1 (G3 embedded) */
5815   - POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 7x0),
  7394 + POWERPC_DEF("750cxe_v21", CPU_POWERPC_750CXE_v21, 7x0),
5816 7395 /* PowerPC 750CXe v2.2 (G3 embedded) */
5817   - POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 7x0),
  7396 + POWERPC_DEF("750cxe_v22", CPU_POWERPC_750CXE_v22, 7x0),
5818 7397 /* PowerPC 750CXe v2.3 (G3 embedded) */
5819   - POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 7x0),
  7398 + POWERPC_DEF("750cxe_v23", CPU_POWERPC_750CXE_v23, 7x0),
5820 7399 /* PowerPC 750CXe v2.4 (G3 embedded) */
5821   - POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 7x0),
  7400 + POWERPC_DEF("750cxe_v24", CPU_POWERPC_750CXE_v24, 7x0),
5822 7401 /* PowerPC 750CXe v2.4b (G3 embedded) */
5823   - POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 7x0),
  7402 + POWERPC_DEF("750cxe_v24b", CPU_POWERPC_750CXE_v24b, 7x0),
5824 7403 /* PowerPC 750CXe v3.1 (G3 embedded) */
5825   - POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 7x0),
  7404 + POWERPC_DEF("750cxe_v31", CPU_POWERPC_750CXE_v31, 7x0),
5826 7405 /* PowerPC 750CXe v3.1b (G3 embedded) */
5827   - POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
  7406 + POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
5828 7407 /* PowerPC 750CXr (G3 embedded) */
5829   - POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
  7408 + POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
5830 7409 /* PowerPC 750E (G3) */
5831   - POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
  7410 + POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
5832 7411 /* PowerPC 750FL (G3 embedded) */
5833   - POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
  7412 + POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
5834 7413 /* PowerPC 750FX (G3 embedded) */
5835   - POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
  7414 + POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
5836 7415 /* PowerPC 750FX v1.0 (G3 embedded) */
5837   - POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 750fx),
  7416 + POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
5838 7417 /* PowerPC 750FX v2.0 (G3 embedded) */
5839   - POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 750fx),
  7418 + POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
5840 7419 /* PowerPC 750FX v2.1 (G3 embedded) */
5841   - POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 750fx),
  7420 + POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
5842 7421 /* PowerPC 750FX v2.2 (G3 embedded) */
5843   - POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 750fx),
  7422 + POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
5844 7423 /* PowerPC 750FX v2.3 (G3 embedded) */
5845   - POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 750fx),
  7424 + POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
5846 7425 /* PowerPC 750GL (G3 embedded) */
5847   - POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
  7426 + POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
5848 7427 /* PowerPC 750GX (G3 embedded) */
5849   - POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
  7428 + POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
5850 7429 /* PowerPC 750GX v1.0 (G3 embedded) */
5851   - POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 750fx),
  7430 + POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750fx),
5852 7431 /* PowerPC 750GX v1.1 (G3 embedded) */
5853   - POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 750fx),
  7432 + POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750fx),
5854 7433 /* PowerPC 750GX v1.2 (G3 embedded) */
5855   - POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 750fx),
  7434 + POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750fx),
5856 7435 /* PowerPC 750L (G3 embedded) */
5857   - POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
  7436 + POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
5858 7437 /* Code name for PowerPC 750L (G3 embedded) */
5859   - POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
  7438 + POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
5860 7439 /* PowerPC 750L v2.2 (G3 embedded) */
5861   - POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 7x0),
  7440 + POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 7x0),
5862 7441 /* PowerPC 750L v3.0 (G3 embedded) */
5863   - POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 7x0),
  7442 + POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 7x0),
5864 7443 /* PowerPC 750L v3.2 (G3 embedded) */
5865   - POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 7x0),
  7444 + POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 7x0),
5866 7445 /* Generic PowerPC 745 */
5867   - POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
  7446 + POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
5868 7447 /* Generic PowerPC 755 */
5869   - POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
  7448 + POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
5870 7449 /* Code name for PowerPC 745/755 */
5871   - POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
  7450 + POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
5872 7451 /* PowerPC 745 v1.0 */
5873   - POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 7x5),
  7452 + POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 7x5),
5874 7453 /* PowerPC 755 v1.0 */
5875   - POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 7x5),
  7454 + POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 7x5),
5876 7455 /* PowerPC 745 v1.1 */
5877   - POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 7x5),
  7456 + POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 7x5),
5878 7457 /* PowerPC 755 v1.1 */
5879   - POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 7x5),
  7458 + POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 7x5),
5880 7459 /* PowerPC 745 v2.0 */
5881   - POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 7x5),
  7460 + POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 7x5),
5882 7461 /* PowerPC 755 v2.0 */
5883   - POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 7x5),
  7462 + POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 7x5),
5884 7463 /* PowerPC 745 v2.1 */
5885   - POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 7x5),
  7464 + POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 7x5),
5886 7465 /* PowerPC 755 v2.1 */
5887   - POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 7x5),
  7466 + POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 7x5),
5888 7467 /* PowerPC 745 v2.2 */
5889   - POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 7x5),
  7468 + POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 7x5),
5890 7469 /* PowerPC 755 v2.2 */
5891   - POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 7x5),
  7470 + POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 7x5),
5892 7471 /* PowerPC 745 v2.3 */
5893   - POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 7x5),
  7472 + POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 7x5),
5894 7473 /* PowerPC 755 v2.3 */
5895   - POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 7x5),
  7474 + POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 7x5),
5896 7475 /* PowerPC 745 v2.4 */
5897   - POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 7x5),
  7476 + POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 7x5),
5898 7477 /* PowerPC 755 v2.4 */
5899   - POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 7x5),
  7478 + POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 7x5),
5900 7479 /* PowerPC 745 v2.5 */
5901   - POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 7x5),
  7480 + POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 7x5),
5902 7481 /* PowerPC 755 v2.5 */
5903   - POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 7x5),
  7482 + POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 7x5),
5904 7483 /* PowerPC 745 v2.6 */
5905   - POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 7x5),
  7484 + POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 7x5),
5906 7485 /* PowerPC 755 v2.6 */
5907   - POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 7x5),
  7486 + POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 7x5),
5908 7487 /* PowerPC 745 v2.7 */
5909   - POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 7x5),
  7488 + POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 7x5),
5910 7489 /* PowerPC 755 v2.7 */
5911   - POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 7x5),
  7490 + POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 7x5),
5912 7491 /* PowerPC 745 v2.8 */
5913   - POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 7x5),
  7492 + POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 7x5),
5914 7493 /* PowerPC 755 v2.8 */
5915   - POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 7x5),
  7494 + POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 7x5),
5916 7495 #if defined (TODO)
5917 7496 /* PowerPC 745P (G3) */
5918   - POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
  7497 + POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
5919 7498 /* PowerPC 755P (G3) */
5920   - POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
  7499 + POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
5921 7500 #endif
5922 7501 /* PowerPC 74xx family */
5923 7502 /* PowerPC 7400 (G4) */
5924   - POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
  7503 + POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
5925 7504 /* Code name for PowerPC 7400 */
5926   - POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
  7505 + POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
5927 7506 /* PowerPC 74xx is also well known as G4 */
5928   - POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
  7507 + POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
5929 7508 /* PowerPC 7400 v1.0 (G4) */
5930   - POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 7400),
  7509 + POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
5931 7510 /* PowerPC 7400 v1.1 (G4) */
5932   - POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 7400),
  7511 + POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
5933 7512 /* PowerPC 7400 v2.0 (G4) */
5934   - POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 7400),
  7513 + POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
5935 7514 /* PowerPC 7400 v2.2 (G4) */
5936   - POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 7400),
  7515 + POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
5937 7516 /* PowerPC 7400 v2.6 (G4) */
5938   - POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 7400),
  7517 + POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
5939 7518 /* PowerPC 7400 v2.7 (G4) */
5940   - POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 7400),
  7519 + POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
5941 7520 /* PowerPC 7400 v2.8 (G4) */
5942   - POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 7400),
  7521 + POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
5943 7522 /* PowerPC 7400 v2.9 (G4) */
5944   - POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 7400),
  7523 + POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
5945 7524 /* PowerPC 7410 (G4) */
5946   - POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
  7525 + POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
5947 7526 /* Code name for PowerPC 7410 */
5948   - POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
  7527 + POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
5949 7528 /* PowerPC 7410 v1.0 (G4) */
5950   - POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 7410),
  7529 + POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
5951 7530 /* PowerPC 7410 v1.1 (G4) */
5952   - POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 7410),
  7531 + POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
5953 7532 /* PowerPC 7410 v1.2 (G4) */
5954   - POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 7410),
  7533 + POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
5955 7534 /* PowerPC 7410 v1.3 (G4) */
5956   - POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 7410),
  7535 + POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
5957 7536 /* PowerPC 7410 v1.4 (G4) */
5958   - POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 7410),
  7537 + POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
5959 7538 /* PowerPC 7448 (G4) */
5960   - POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
  7539 + POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
5961 7540 /* PowerPC 7448 v1.0 (G4) */
5962   - POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 7400),
  7541 + POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
5963 7542 /* PowerPC 7448 v1.1 (G4) */
5964   - POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 7400),
  7543 + POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
5965 7544 /* PowerPC 7448 v2.0 (G4) */
5966   - POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 7400),
  7545 + POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
5967 7546 /* PowerPC 7448 v2.1 (G4) */
5968   - POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 7400),
  7547 + POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
5969 7548 /* PowerPC 7450 (G4) */
5970   - POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
  7549 + POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
5971 7550 /* Code name for PowerPC 7450 */
5972   - POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
  7551 + POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
5973 7552 /* PowerPC 7450 v1.0 (G4) */
5974   - POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 7450),
  7553 + POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
5975 7554 /* PowerPC 7450 v1.1 (G4) */
5976   - POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 7450),
  7555 + POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
5977 7556 /* PowerPC 7450 v1.2 (G4) */
5978   - POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 7450),
  7557 + POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
5979 7558 /* PowerPC 7450 v2.0 (G4) */
5980   - POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 7450),
  7559 + POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
5981 7560 /* PowerPC 7450 v2.1 (G4) */
5982   - POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 7450),
  7561 + POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
5983 7562 /* PowerPC 7441 (G4) */
5984   - POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
  7563 + POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
5985 7564 /* PowerPC 7451 (G4) */
5986   - POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
  7565 + POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
5987 7566 /* PowerPC 7441g (G4) */
5988   - POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
  7567 + POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
5989 7568 /* PowerPC 7451g (G4) */
5990   - POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
  7569 + POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
5991 7570 /* PowerPC 7445 (G4) */
5992   - POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
  7571 + POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
5993 7572 /* PowerPC 7455 (G4) */
5994   - POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
  7573 + POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
5995 7574 /* Code name for PowerPC 7445/7455 */
5996   - POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
  7575 + POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
5997 7576 /* PowerPC 7445 v1.0 (G4) */
5998   - POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 7445),
  7577 + POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
5999 7578 /* PowerPC 7455 v1.0 (G4) */
6000   - POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 7455),
  7579 + POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
6001 7580 /* PowerPC 7445 v2.1 (G4) */
6002   - POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 7445),
  7581 + POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
6003 7582 /* PowerPC 7455 v2.1 (G4) */
6004   - POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 7455),
  7583 + POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
6005 7584 /* PowerPC 7445 v3.2 (G4) */
6006   - POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 7445),
  7585 + POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
6007 7586 /* PowerPC 7455 v3.2 (G4) */
6008   - POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 7455),
  7587 + POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
6009 7588 /* PowerPC 7445 v3.3 (G4) */
6010   - POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 7445),
  7589 + POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
6011 7590 /* PowerPC 7455 v3.3 (G4) */
6012   - POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 7455),
  7591 + POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
6013 7592 /* PowerPC 7445 v3.4 (G4) */
6014   - POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 7445),
  7593 + POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
6015 7594 /* PowerPC 7455 v3.4 (G4) */
6016   - POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 7455),
  7595 + POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
6017 7596 /* PowerPC 7447 (G4) */
6018   - POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
  7597 + POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
6019 7598 /* PowerPC 7457 (G4) */
6020   - POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
  7599 + POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
6021 7600 /* Code name for PowerPC 7447/7457 */
6022   - POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
  7601 + POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
6023 7602 /* PowerPC 7447 v1.0 (G4) */
6024   - POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 7445),
  7603 + POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
6025 7604 /* PowerPC 7457 v1.0 (G4) */
6026   - POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 7455),
  7605 + POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
6027 7606 /* Code name for PowerPC 7447A/7457A */
6028   - POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 7455),
  7607 + POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 7455),
6029 7608 /* PowerPC 7447 v1.1 (G4) */
6030   - POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 7445),
  7609 + POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
6031 7610 /* PowerPC 7457 v1.1 (G4) */
6032   - POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 7455),
  7611 + POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
6033 7612 /* PowerPC 7447 v1.2 (G4) */
6034   - POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 7445),
  7613 + POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445),
6035 7614 /* PowerPC 7457 v1.2 (G4) */
6036   - POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 7455),
  7615 + POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
6037 7616 /* 64 bits PowerPC */
6038 7617 #if defined (TARGET_PPC64)
6039 7618 /* PowerPC 620 */
6040 7619 /* XXX: code name "Trident" */
6041   - POWERPC_DEF("620", CPU_POWERPC_620, 620),
  7620 + POWERPC_DEF("620", CPU_POWERPC_620, 620),
6042 7621 #if defined (TODO)
6043 7622 /* PowerPC 630 (POWER3) */
6044 7623 /* XXX: code names: "Boxer" "Dino" */
6045   - POWERPC_DEF("630", CPU_POWERPC_630, 630),
6046   - POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
  7624 + POWERPC_DEF("630", CPU_POWERPC_630, 630),
  7625 + POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
6047 7626 #endif
6048 7627 #if defined (TODO)
6049 7628 /* PowerPC 631 (Power 3+) */
6050   - POWERPC_DEF("631", CPU_POWERPC_631, 631),
6051   - POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
  7629 + POWERPC_DEF("631", CPU_POWERPC_631, 631),
  7630 + POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
6052 7631 #endif
6053 7632 #if defined (TODO)
6054 7633 /* POWER4 */
6055   - POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
  7634 + POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
6056 7635 #endif
6057 7636 #if defined (TODO)
6058 7637 /* POWER4p */
6059   - POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
  7638 + POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
6060 7639 #endif
6061 7640 #if defined (TODO)
6062 7641 /* POWER5 */
6063   - POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
  7642 + POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
6064 7643 /* POWER5GR */
6065   - POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
  7644 + POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
6066 7645 #endif
6067 7646 #if defined (TODO)
6068 7647 /* POWER5+ */
6069   - POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
  7648 + POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
6070 7649 /* POWER5GS */
6071   - POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
  7650 + POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
6072 7651 #endif
6073 7652 #if defined (TODO)
6074 7653 /* POWER6 */
6075   - POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
  7654 + POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
6076 7655 /* POWER6 running in POWER5 mode */
6077   - POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
  7656 + POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
6078 7657 /* POWER6A */
6079   - POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
  7658 + POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
6080 7659 #endif
6081 7660 /* PowerPC 970 */
6082   - POWERPC_DEF("970", CPU_POWERPC_970, 970),
  7661 + POWERPC_DEF("970", CPU_POWERPC_970, 970),
6083 7662 /* PowerPC 970FX (G5) */
6084   - POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
  7663 + POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
6085 7664 /* PowerPC 970FX v1.0 (G5) */
6086   - POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 970FX),
  7665 + POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
6087 7666 /* PowerPC 970FX v2.0 (G5) */
6088   - POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 970FX),
  7667 + POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
6089 7668 /* PowerPC 970FX v2.1 (G5) */
6090   - POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 970FX),
  7669 + POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
6091 7670 /* PowerPC 970FX v3.0 (G5) */
6092   - POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 970FX),
  7671 + POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
6093 7672 /* PowerPC 970FX v3.1 (G5) */
6094   - POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 970FX),
  7673 + POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
6095 7674 /* PowerPC 970GX (G5) */
6096   - POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
  7675 + POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
6097 7676 /* PowerPC 970MP */
6098   - POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
  7677 + POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
6099 7678 /* PowerPC 970MP v1.0 */
6100   - POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 970MP),
  7679 + POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
6101 7680 /* PowerPC 970MP v1.1 */
6102   - POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 970MP),
  7681 + POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
6103 7682 #if defined (TODO)
6104 7683 /* PowerPC Cell */
6105   - POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
  7684 + POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
6106 7685 #endif
6107 7686 #if defined (TODO)
6108 7687 /* PowerPC Cell v1.0 */
6109   - POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 970),
  7688 + POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
6110 7689 #endif
6111 7690 #if defined (TODO)
6112 7691 /* PowerPC Cell v2.0 */
6113   - POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 970),
  7692 + POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
6114 7693 #endif
6115 7694 #if defined (TODO)
6116 7695 /* PowerPC Cell v3.0 */
6117   - POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 970),
  7696 + POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
6118 7697 #endif
6119 7698 #if defined (TODO)
6120 7699 /* PowerPC Cell v3.1 */
6121   - POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 970),
  7700 + POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
6122 7701 #endif
6123 7702 #if defined (TODO)
6124 7703 /* PowerPC Cell v3.2 */
6125   - POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 970),
  7704 + POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
6126 7705 #endif
6127 7706 #if defined (TODO)
6128 7707 /* RS64 (Apache/A35) */
... ... @@ -6130,59 +7709,57 @@ static const ppc_def_t ppc_defs[] = {
6130 7709 * and the PowerPC 64 one.
6131 7710 */
6132 7711 /* What about A10 & A30 ? */
6133   - POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
6134   - POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
6135   - POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
  7712 + POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
  7713 + POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
  7714 + POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
6136 7715 #endif
6137 7716 #if defined (TODO)
6138 7717 /* RS64-II (NorthStar/A50) */
6139   - POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
6140   - POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
6141   - POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
  7718 + POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
  7719 + POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
  7720 + POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
6142 7721 #endif
6143 7722 #if defined (TODO)
6144 7723 /* RS64-III (Pulsar) */
6145   - POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
6146   - POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
  7724 + POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
  7725 + POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
6147 7726 #endif
6148 7727 #if defined (TODO)
6149 7728 /* RS64-IV (IceStar/IStar/SStar) */
6150   - POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
6151   - POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
6152   - POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
6153   - POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
  7729 + POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
  7730 + POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
  7731 + POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
  7732 + POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
6154 7733 #endif
6155 7734 #endif /* defined (TARGET_PPC64) */
6156 7735 /* POWER */
6157 7736 #if defined (TODO)
6158 7737 /* Original POWER */
6159   - POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
6160   - POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
6161   - POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
6162   - POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
6163   - POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
  7738 + POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
  7739 + POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
  7740 + POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
  7741 + POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
  7742 + POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
6164 7743 #endif
6165 7744 #if defined (TODO)
6166 7745 /* POWER2 */
6167   - POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
6168   - POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
6169   - POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
  7746 + POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
  7747 + POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
  7748 + POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
6170 7749 #endif
6171 7750 /* PA semi cores */
6172 7751 #if defined (TODO)
6173 7752 /* PA PA6T */
6174   - POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
  7753 + POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
6175 7754 #endif
6176 7755 /* Generic PowerPCs */
6177 7756 #if defined (TARGET_PPC64)
6178   -#if defined (TODO)
6179   - POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
  7757 + POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
6180 7758 #endif
6181   -#endif
6182   - POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
6183   - POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
  7759 + POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
  7760 + POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
6184 7761 /* Fallback */
6185   - POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
  7762 + POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
6186 7763 };
6187 7764  
6188 7765 /*****************************************************************************/
... ... @@ -6210,6 +7787,20 @@ static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
6210 7787 SPR_NOACCESS, SPR_NOACCESS,
6211 7788 &spr_read_generic, SPR_NOACCESS,
6212 7789 def->pvr);
  7790 + /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
  7791 + if (def->svr != POWERPC_SVR_NONE) {
  7792 + if (def->svr & POWERPC_SVR_E500) {
  7793 + spr_register(env, SPR_E500_SVR, "SVR",
  7794 + SPR_NOACCESS, SPR_NOACCESS,
  7795 + &spr_read_generic, SPR_NOACCESS,
  7796 + def->svr & ~POWERPC_SVR_E500);
  7797 + } else {
  7798 + spr_register(env, SPR_SVR, "SVR",
  7799 + SPR_NOACCESS, SPR_NOACCESS,
  7800 + &spr_read_generic, SPR_NOACCESS,
  7801 + def->svr);
  7802 + }
  7803 + }
6213 7804 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6214 7805 (*def->init_proc)(env);
6215 7806 /* MSR bits & flags consistency checks */
... ...