gwj / at91sam9263 · Commits

Commit b4095fed95235c95b04b2337ec29947f509af3bc

Authored by j_mayer
1 parent 05332d70

Define Freescale cores specific MMU model, exceptions and input bus. 

(but do not provide any actual implementation).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 109 additions and 36 deletions
target-ppc/cpu.h
  View file @b4095fe
... ... @@ -104,8 +104,10 @@ enum powerpc_mmu_t {
104 104 POWERPC_MMU_SOFT_4xx,
105 105 /* PowerPC 4xx MMU with software TLB and zones protections */
106 106 POWERPC_MMU_SOFT_4xx_Z,
107   - /* PowerPC 4xx MMU in real mode only */
108   - POWERPC_MMU_REAL_4xx,
  107 + /* PowerPC MMU in real mode only */
  108 + POWERPC_MMU_REAL,
  109 + /* Freescale MPC8xx MMU model */
  110 + POWERPC_MMU_MPC8xx,
109 111 /* BookE MMU model */
110 112 POWERPC_MMU_BOOKE,
111 113 /* BookE FSL MMU model */
... ... @@ -171,8 +173,8 @@ enum {
171 173 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
172 174 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
173 175 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
174   - POWERPC_EXCP_DTLB = 13, /* Data TLB error */
175   - POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */
  176 + POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
  177 + POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
176 178 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
177 179 /* Vectors 16 to 31 are reserved */
178 180 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
... ... @@ -201,21 +203,27 @@ enum {
201 203 /* 602 specific exceptions */
202 204 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
203 205 /* 602/603 specific exceptions */
204   - POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */
  206 + POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
205 207 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
206 208 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
207 209 /* Exceptions available on most PowerPC */
208 210 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
209   - POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */
210   - POWERPC_EXCP_SMI = 83, /* System management interrupt */
211   - POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */
  211 + POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
  212 + POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
  213 + POWERPC_EXCP_SMI = 84, /* System management interrupt */
  214 + POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
212 215 /* 7xx/74xx specific exceptions */
213   - POWERPC_EXCP_THERM = 85, /* Thermal interrupt */
  216 + POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
214 217 /* 74xx specific exceptions */
215   - POWERPC_EXCP_VPUA = 86, /* Vector assist exception */
  218 + POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
216 219 /* 970FX specific exceptions */
217   - POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */
218   - POWERPC_EXCP_MAINT = 88, /* Maintenance exception */
  220 + POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
  221 + POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
  222 + /* Freescale embeded cores specific exceptions */
  223 + POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
  224 + POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
  225 + POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
  226 + POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
219 227 /* EOL */
220 228 POWERPC_EXCP_NB = 96,
221 229 /* Qemu exceptions: used internally during code translation */
... ... @@ -280,6 +288,8 @@ enum powerpc_input_t {
280 288 PPC_FLAGS_INPUT_970,
281 289 /* PowerPC 401 bus */
282 290 PPC_FLAGS_INPUT_401,
  291 + /* Freescale RCPU bus */
  292 + PPC_FLAGS_INPUT_RCPU,
283 293 };
284 294  
285 295 #define PPC_INPUT(env) (env->bus_model)
... ... @@ -1259,6 +1269,22 @@ enum {
1259 1269 PPC40x_INPUT_NB,
1260 1270 };
1261 1271  
  1272 +enum {
  1273 + /* RCPU input pins */
  1274 + PPCRCPU_INPUT_PORESET = 0,
  1275 + PPCRCPU_INPUT_HRESET = 1,
  1276 + PPCRCPU_INPUT_SRESET = 2,
  1277 + PPCRCPU_INPUT_IRQ0 = 3,
  1278 + PPCRCPU_INPUT_IRQ1 = 4,
  1279 + PPCRCPU_INPUT_IRQ2 = 5,
  1280 + PPCRCPU_INPUT_IRQ3 = 6,
  1281 + PPCRCPU_INPUT_IRQ4 = 7,
  1282 + PPCRCPU_INPUT_IRQ5 = 8,
  1283 + PPCRCPU_INPUT_IRQ6 = 9,
  1284 + PPCRCPU_INPUT_IRQ7 = 10,
  1285 + PPCRCPU_INPUT_NB,
  1286 +};
  1287 +
1262 1288 #if defined(TARGET_PPC64)
1263 1289 enum {
1264 1290 /* PowerPC 970 input pins */
... ...
target-ppc/helper.c
  View file @b4095fe
... ... @@ -1357,7 +1357,7 @@ static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
1357 1357 case POWERPC_MMU_SOFT_6xx:
1358 1358 case POWERPC_MMU_SOFT_74xx:
1359 1359 case POWERPC_MMU_SOFT_4xx:
1360   - case POWERPC_MMU_REAL_4xx:
  1360 + case POWERPC_MMU_REAL:
1361 1361 case POWERPC_MMU_BOOKE:
1362 1362 ctx->prot |= PAGE_WRITE;
1363 1363 break;
... ... @@ -1392,6 +1392,10 @@ static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
1392 1392 }
1393 1393 }
1394 1394 break;
  1395 + case POWERPC_MMU_MPC8xx:
  1396 + /* XXX: TODO */
  1397 + cpu_abort(env, "MPC8xx MMU model is not implemented\n");
  1398 + break;
1395 1399 case POWERPC_MMU_BOOKE_FSL:
1396 1400 /* XXX: TODO */
1397 1401 cpu_abort(env, "BookE FSL MMU model not implemented\n");
... ... @@ -1445,12 +1449,16 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1445 1449 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1446 1450 rw, access_type);
1447 1451 break;
  1452 + case POWERPC_MMU_MPC8xx:
  1453 + /* XXX: TODO */
  1454 + cpu_abort(env, "MPC8xx MMU model is not implemented\n");
  1455 + break;
1448 1456 case POWERPC_MMU_BOOKE_FSL:
1449 1457 /* XXX: TODO */
1450 1458 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1451 1459 return -1;
1452   - case POWERPC_MMU_REAL_4xx:
1453   - cpu_abort(env, "PowerPC 401 does not do any translation\n");
  1460 + case POWERPC_MMU_REAL:
  1461 + cpu_abort(env, "PowerPC in real mode do not do any translation\n");
1454 1462 return -1;
1455 1463 default:
1456 1464 cpu_abort(env, "Unknown or invalid MMU model\n");
... ... @@ -1537,15 +1545,19 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1537 1545 break;
1538 1546 case POWERPC_MMU_BOOKE:
1539 1547 /* XXX: TODO */
1540   - cpu_abort(env, "MMU model not implemented\n");
  1548 + cpu_abort(env, "BookE MMU model is not implemented\n");
1541 1549 return -1;
1542 1550 case POWERPC_MMU_BOOKE_FSL:
1543 1551 /* XXX: TODO */
1544   - cpu_abort(env, "MMU model not implemented\n");
  1552 + cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1545 1553 return -1;
1546   - case POWERPC_MMU_REAL_4xx:
1547   - cpu_abort(env, "PowerPC 401 should never raise any MMU "
1548   - "exceptions\n");
  1554 + case POWERPC_MMU_MPC8xx:
  1555 + /* XXX: TODO */
  1556 + cpu_abort(env, "MPC8xx MMU model is not implemented\n");
  1557 + break;
  1558 + case POWERPC_MMU_REAL:
  1559 + cpu_abort(env, "PowerPC in real mode should never raise "
  1560 + "any MMU exceptions\n");
1549 1561 return -1;
1550 1562 default:
1551 1563 cpu_abort(env, "Unknown or invalid MMU model\n");
... ... @@ -1632,17 +1644,21 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1632 1644 else
1633 1645 env->spr[SPR_DSISR] = 0x40000000;
1634 1646 break;
  1647 + case POWERPC_MMU_MPC8xx:
  1648 + /* XXX: TODO */
  1649 + cpu_abort(env, "MPC8xx MMU model is not implemented\n");
  1650 + break;
1635 1651 case POWERPC_MMU_BOOKE:
1636 1652 /* XXX: TODO */
1637   - cpu_abort(env, "MMU model not implemented\n");
  1653 + cpu_abort(env, "BookE MMU model is not implemented\n");
1638 1654 return -1;
1639 1655 case POWERPC_MMU_BOOKE_FSL:
1640 1656 /* XXX: TODO */
1641   - cpu_abort(env, "MMU model not implemented\n");
  1657 + cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1642 1658 return -1;
1643   - case POWERPC_MMU_REAL_4xx:
1644   - cpu_abort(env, "PowerPC 401 should never raise any MMU "
1645   - "exceptions\n");
  1659 + case POWERPC_MMU_REAL:
  1660 + cpu_abort(env, "PowerPC in real mode should never raise "
  1661 + "any MMU exceptions\n");
1646 1662 return -1;
1647 1663 default:
1648 1664 cpu_abort(env, "Unknown or invalid MMU model\n");
... ... @@ -1921,16 +1937,20 @@ void ppc_tlb_invalidate_all (CPUPPCState *env)
1921 1937 case POWERPC_MMU_SOFT_4xx_Z:
1922 1938 ppc4xx_tlb_invalidate_all(env);
1923 1939 break;
1924   - case POWERPC_MMU_REAL_4xx:
  1940 + case POWERPC_MMU_REAL:
1925 1941 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1926 1942 break;
  1943 + case POWERPC_MMU_MPC8xx:
  1944 + /* XXX: TODO */
  1945 + cpu_abort(env, "MPC8xx MMU model is not implemented\n");
  1946 + break;
1927 1947 case POWERPC_MMU_BOOKE:
1928 1948 /* XXX: TODO */
1929   - cpu_abort(env, "MMU model not implemented\n");
  1949 + cpu_abort(env, "BookE MMU model is not implemented\n");
1930 1950 break;
1931 1951 case POWERPC_MMU_BOOKE_FSL:
1932 1952 /* XXX: TODO */
1933   - cpu_abort(env, "MMU model not implemented\n");
  1953 + cpu_abort(env, "BookE MMU model is not implemented\n");
1934 1954 break;
1935 1955 case POWERPC_MMU_32B:
1936 1956 case POWERPC_MMU_601:
... ... @@ -1961,16 +1981,20 @@ void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1961 1981 case POWERPC_MMU_SOFT_4xx_Z:
1962 1982 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1963 1983 break;
1964   - case POWERPC_MMU_REAL_4xx:
  1984 + case POWERPC_MMU_REAL:
1965 1985 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1966 1986 break;
  1987 + case POWERPC_MMU_MPC8xx:
  1988 + /* XXX: TODO */
  1989 + cpu_abort(env, "MPC8xx MMU model is not implemented\n");
  1990 + break;
1967 1991 case POWERPC_MMU_BOOKE:
1968 1992 /* XXX: TODO */
1969   - cpu_abort(env, "MMU model not implemented\n");
  1993 + cpu_abort(env, "BookE MMU model is not implemented\n");
1970 1994 break;
1971 1995 case POWERPC_MMU_BOOKE_FSL:
1972 1996 /* XXX: TODO */
1973   - cpu_abort(env, "MMU model not implemented\n");
  1997 + cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1974 1998 break;
1975 1999 case POWERPC_MMU_32B:
1976 2000 case POWERPC_MMU_601:
... ... @@ -2613,6 +2637,10 @@ static always_inline void powerpc_excp (CPUState *env,
2613 2637 cpu_abort(env, "Floating point assist exception "
2614 2638 "is not implemented yet !\n");
2615 2639 goto store_next;
  2640 + case POWERPC_EXCP_DABR: /* Data address breakpoint */
  2641 + /* XXX: TODO */
  2642 + cpu_abort(env, "DABR exception is not implemented yet !\n");
  2643 + goto store_next;
2616 2644 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2617 2645 /* XXX: TODO */
2618 2646 cpu_abort(env, "IABR exception is not implemented yet !\n");
... ... @@ -2648,6 +2676,16 @@ static always_inline void powerpc_excp (CPUState *env,
2648 2676 cpu_abort(env,
2649 2677 "970 maintenance exception is not implemented yet !\n");
2650 2678 goto store_next;
  2679 + case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
  2680 + /* XXX: TODO */
  2681 + cpu_abort(env, "Maskable external exception "
  2682 + "is not implemented yet !\n");
  2683 + goto store_next;
  2684 + case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
  2685 + /* XXX: TODO */
  2686 + cpu_abort(env, "Non maskable external exception "
  2687 + "is not implemented yet !\n");
  2688 + goto store_next;
2651 2689 default:
2652 2690 excp_invalid:
2653 2691 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
... ... @@ -2899,7 +2937,7 @@ void cpu_ppc_reset (void *opaque)
2899 2937 msr |= (target_ulong)1 << MSR_PR;
2900 2938 #else
2901 2939 env->nip = env->hreset_vector | env->excp_prefix;
2902   - if (env->mmu_model != POWERPC_MMU_REAL_4xx)
  2940 + if (env->mmu_model != POWERPC_MMU_REAL)
2903 2941 ppc_tlb_invalidate_all(env);
2904 2942 #endif
2905 2943 env->msr = msr;
... ...
target-ppc/translate_init.c
  View file @b4095fe
... ... @@ -2656,7 +2656,7 @@ static int check_pow_hid0 (CPUPPCState *env)
2656 2656 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2657 2657 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2658 2658 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2659   -#define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
  2659 +#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
2660 2660 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2661 2661 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2662 2662 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
... ... @@ -2775,7 +2775,7 @@ static void init_proc_IOP480 (CPUPPCState *env)
2775 2775 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2776 2776 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2777 2777 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2778   -#define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
  2778 +#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
2779 2779 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2780 2780 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2781 2781 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
... ... @@ -6639,8 +6639,11 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
6639 6639 mmu_model = "PowerPC 4xx with software driven TLBs "
6640 6640 "and zones protections";
6641 6641 break;
6642   - case POWERPC_MMU_REAL_4xx:
6643   - mmu_model = "PowerPC 4xx real mode only";
  6642 + case POWERPC_MMU_REAL:
  6643 + mmu_model = "PowerPC real mode only";
  6644 + break;
  6645 + case POWERPC_MMU_MPC8xx:
  6646 + mmu_model = "PowerPC MPC8xx";
6644 6647 break;
6645 6648 case POWERPC_MMU_BOOKE:
6646 6649 mmu_model = "PowerPC BookE";
... ... @@ -6648,6 +6651,9 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
6648 6651 case POWERPC_MMU_BOOKE_FSL:
6649 6652 mmu_model = "PowerPC BookE FSL";
6650 6653 break;
  6654 + case POWERPC_MMU_601:
  6655 + mmu_model = "PowerPC 601";
  6656 + break;
6651 6657 #if defined (TARGET_PPC64)
6652 6658 case POWERPC_MMU_64B:
6653 6659 mmu_model = "PowerPC 64";
... ... @@ -6713,6 +6719,9 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
6713 6719 case PPC_FLAGS_INPUT_401:
6714 6720 bus_model = "PowerPC 401/403";
6715 6721 break;
  6722 + case PPC_FLAGS_INPUT_RCPU:
  6723 + bus_model = "RCPU / MPC8xx";
  6724 + break;
6716 6725 #if defined (TARGET_PPC64)
6717 6726 case PPC_FLAGS_INPUT_970:
6718 6727 bus_model = "PowerPC 970";
... ...