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/*
* MIPS emulation micro - operations for qemu .
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*
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* Copyright ( c ) 2004 - 2005 Jocelyn Mayer
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* Copyright ( c ) 2006 Marius Groeger ( FPU operations )
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* Copyright ( c ) 2007 Thiemo Seufer ( 64 - bit FPU support )
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*
* This library is free software ; you can redistribute it and / or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation ; either
* version 2 of the License , or ( at your option ) any later version .
*
* This library is distributed in the hope that it will be useful ,
* but WITHOUT ANY WARRANTY ; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE . See the GNU
* Lesser General Public License for more details .
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library ; if not , write to the Free Software
* Foundation , Inc ., 59 Temple Place , Suite 330 , Boston , MA 02111 - 1307 USA
*/
# include "config.h"
# include "exec.h"
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# include "host-utils.h"
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# ifndef CALL_FROM_TB0
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# define CALL_FROM_TB0 ( func ) func ()
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# endif
# ifndef CALL_FROM_TB1
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# define CALL_FROM_TB1 ( func , arg0 ) func ( arg0 )
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# endif
# ifndef CALL_FROM_TB1_CONST16
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# define CALL_FROM_TB1_CONST16 ( func , arg0 ) CALL_FROM_TB1 ( func , arg0 )
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# endif
# ifndef CALL_FROM_TB2
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# define CALL_FROM_TB2 ( func , arg0 , arg1 ) func ( arg0 , arg1 )
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# endif
# ifndef CALL_FROM_TB2_CONST16
# define CALL_FROM_TB2_CONST16 ( func , arg0 , arg1 ) \
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CALL_FROM_TB2 ( func , arg0 , arg1 )
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# endif
# ifndef CALL_FROM_TB3
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# define CALL_FROM_TB3 ( func , arg0 , arg1 , arg2 ) func ( arg0 , arg1 , arg2 )
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# endif
# ifndef CALL_FROM_TB4
# define CALL_FROM_TB4 ( func , arg0 , arg1 , arg2 , arg3 ) \
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func ( arg0 , arg1 , arg2 , arg3 )
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# endif
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# define REG 1
# include "op_template.c"
# undef REG
# define REG 2
# include "op_template.c"
# undef REG
# define REG 3
# include "op_template.c"
# undef REG
# define REG 4
# include "op_template.c"
# undef REG
# define REG 5
# include "op_template.c"
# undef REG
# define REG 6
# include "op_template.c"
# undef REG
# define REG 7
# include "op_template.c"
# undef REG
# define REG 8
# include "op_template.c"
# undef REG
# define REG 9
# include "op_template.c"
# undef REG
# define REG 10
# include "op_template.c"
# undef REG
# define REG 11
# include "op_template.c"
# undef REG
# define REG 12
# include "op_template.c"
# undef REG
# define REG 13
# include "op_template.c"
# undef REG
# define REG 14
# include "op_template.c"
# undef REG
# define REG 15
# include "op_template.c"
# undef REG
# define REG 16
# include "op_template.c"
# undef REG
# define REG 17
# include "op_template.c"
# undef REG
# define REG 18
# include "op_template.c"
# undef REG
# define REG 19
# include "op_template.c"
# undef REG
# define REG 20
# include "op_template.c"
# undef REG
# define REG 21
# include "op_template.c"
# undef REG
# define REG 22
# include "op_template.c"
# undef REG
# define REG 23
# include "op_template.c"
# undef REG
# define REG 24
# include "op_template.c"
# undef REG
# define REG 25
# include "op_template.c"
# undef REG
# define REG 26
# include "op_template.c"
# undef REG
# define REG 27
# include "op_template.c"
# undef REG
# define REG 28
# include "op_template.c"
# undef REG
# define REG 29
# include "op_template.c"
# undef REG
# define REG 30
# include "op_template.c"
# undef REG
# define REG 31
# include "op_template.c"
# undef REG
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# define TN
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# include "op_template.c"
# undef TN
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# define FREG 0
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# include "fop_template.c"
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# undef FREG
# define FREG 1
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# include "fop_template.c"
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# undef FREG
# define FREG 2
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# include "fop_template.c"
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# undef FREG
# define FREG 3
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# include "fop_template.c"
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# undef FREG
# define FREG 4
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# include "fop_template.c"
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# undef FREG
# define FREG 5
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# include "fop_template.c"
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# undef FREG
# define FREG 6
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# include "fop_template.c"
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# undef FREG
# define FREG 7
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# include "fop_template.c"
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# undef FREG
# define FREG 8
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# include "fop_template.c"
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# undef FREG
# define FREG 9
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# include "fop_template.c"
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# undef FREG
# define FREG 10
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# include "fop_template.c"
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# undef FREG
# define FREG 11
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# include "fop_template.c"
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# undef FREG
# define FREG 12
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# include "fop_template.c"
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# undef FREG
# define FREG 13
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# include "fop_template.c"
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# undef FREG
# define FREG 14
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# include "fop_template.c"
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# undef FREG
# define FREG 15
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# include "fop_template.c"
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# undef FREG
# define FREG 16
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# include "fop_template.c"
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# undef FREG
# define FREG 17
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# include "fop_template.c"
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# undef FREG
# define FREG 18
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# include "fop_template.c"
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# undef FREG
# define FREG 19
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# include "fop_template.c"
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# undef FREG
# define FREG 20
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# include "fop_template.c"
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# undef FREG
# define FREG 21
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# include "fop_template.c"
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# undef FREG
# define FREG 22
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# include "fop_template.c"
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# undef FREG
# define FREG 23
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# include "fop_template.c"
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# undef FREG
# define FREG 24
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# include "fop_template.c"
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# undef FREG
# define FREG 25
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# include "fop_template.c"
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# undef FREG
# define FREG 26
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# include "fop_template.c"
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# undef FREG
# define FREG 27
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# include "fop_template.c"
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# undef FREG
# define FREG 28
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# include "fop_template.c"
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# undef FREG
# define FREG 29
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# include "fop_template.c"
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# undef FREG
# define FREG 30
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# include "fop_template.c"
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# undef FREG
# define FREG 31
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# include "fop_template.c"
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# undef FREG
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# define FTN
# include "fop_template.c"
# undef FTN
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void op_dup_T0 ( void )
{
T2 = T0 ;
RETURN ();
}
void op_load_HI ( void )
{
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T0 = env -> HI [ PARAM1 ][ env -> current_tc ];
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RETURN ();
}
void op_store_HI ( void )
{
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env -> HI [ PARAM1 ][ env -> current_tc ] = T0 ;
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RETURN ();
}
void op_load_LO ( void )
{
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T0 = env -> LO [ PARAM1 ][ env -> current_tc ];
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RETURN ();
}
void op_store_LO ( void )
{
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env -> LO [ PARAM1 ][ env -> current_tc ] = T0 ;
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RETURN ();
}
/* Load and store */
# define MEMSUFFIX _raw
# include "op_mem.c"
# undef MEMSUFFIX
# if ! defined ( CONFIG_USER_ONLY )
# define MEMSUFFIX _user
# include "op_mem.c"
# undef MEMSUFFIX
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# define MEMSUFFIX _super
# include "op_mem.c"
# undef MEMSUFFIX
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# define MEMSUFFIX _kernel
# include "op_mem.c"
# undef MEMSUFFIX
# endif
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/* Addresses computation */
void op_addr_add ( void )
{
/* For compatibility with 32 - bit code , data reference in user mode
with Status_UX = 0 should be casted to 32 - bit and sign extended .
See the MIPS64 PRA manual , section 4 . 10 . */
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# if defined ( TARGET_MIPSN32 ) || defined ( TARGET_MIPS64 )
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if ((( env -> hflags & MIPS_HFLAG_KSU ) == MIPS_HFLAG_UM ) &&
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! ( env -> CP0_Status & ( 1 << CP0St_UX )))
T0 = ( int64_t )( int32_t )( T0 + T1 );
else
# endif
T0 += T1 ;
RETURN ();
}
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/* Arithmetic */
void op_add ( void )
{
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T0 = ( int32_t )(( int32_t ) T0 + ( int32_t ) T1 );
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RETURN ();
}
void op_addo ( void )
{
target_ulong tmp ;
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tmp = ( int32_t ) T0 ;
T0 = ( int32_t ) T0 + ( int32_t ) T1 ;
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if ((( tmp ^ T1 ^ ( - 1 )) & ( T0 ^ T1 )) >> 31 ) {
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/* operands of same sign, result different sign */
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CALL_FROM_TB1 ( do_raise_exception , EXCP_OVERFLOW );
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}
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T0 = ( int32_t ) T0 ;
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RETURN ();
}
void op_sub ( void )
{
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T0 = ( int32_t )(( int32_t ) T0 - ( int32_t ) T1 );
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RETURN ();
}
void op_subo ( void )
{
target_ulong tmp ;
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tmp = ( int32_t ) T0 ;
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T0 = ( int32_t ) T0 - ( int32_t ) T1 ;
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if ((( tmp ^ T1 ) & ( tmp ^ T0 )) >> 31 ) {
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/* operands of different sign, first operand and result different sign */
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CALL_FROM_TB1 ( do_raise_exception , EXCP_OVERFLOW );
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}
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T0 = ( int32_t ) T0 ;
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RETURN ();
}
void op_mul ( void )
{
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T0 = ( int32_t )(( int32_t ) T0 * ( int32_t ) T1 );
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RETURN ();
}
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# if HOST_LONG_BITS < 64
void op_div ( void )
{
CALL_FROM_TB0 ( do_div );
RETURN ();
}
# else
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void op_div ( void )
{
if ( T1 != 0 ) {
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env -> LO [ 0 ][ env -> current_tc ] = ( int32_t )(( int64_t )( int32_t ) T0 / ( int32_t ) T1 );
env -> HI [ 0 ][ env -> current_tc ] = ( int32_t )(( int64_t )( int32_t ) T0 % ( int32_t ) T1 );
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}
RETURN ();
}
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# endif
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void op_divu ( void )
{
if ( T1 != 0 ) {
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env -> LO [ 0 ][ env -> current_tc ] = ( int32_t )(( uint32_t ) T0 / ( uint32_t ) T1 );
env -> HI [ 0 ][ env -> current_tc ] = ( int32_t )(( uint32_t ) T0 % ( uint32_t ) T1 );
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}
RETURN ();
}
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# if defined ( TARGET_MIPSN32 ) || defined ( TARGET_MIPS64 )
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/* Arithmetic */
void op_dadd ( void )
{
T0 += T1 ;
RETURN ();
}
void op_daddo ( void )
{
target_long tmp ;
tmp = T0 ;
T0 += T1 ;
if ((( tmp ^ T1 ^ ( - 1 )) & ( T0 ^ T1 )) >> 63 ) {
/* operands of same sign, result different sign */
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CALL_FROM_TB1 ( do_raise_exception , EXCP_OVERFLOW );
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}
RETURN ();
}
void op_dsub ( void )
{
T0 -= T1 ;
RETURN ();
}
void op_dsubo ( void )
{
target_long tmp ;
tmp = T0 ;
T0 = ( int64_t ) T0 - ( int64_t ) T1 ;
if ((( tmp ^ T1 ) & ( tmp ^ T0 )) >> 63 ) {
/* operands of different sign, first operand and result different sign */
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CALL_FROM_TB1 ( do_raise_exception , EXCP_OVERFLOW );
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}
RETURN ();
}
void op_dmul ( void )
{
T0 = ( int64_t ) T0 * ( int64_t ) T1 ;
RETURN ();
}
/* Those might call libgcc functions. */
void op_ddiv ( void )
{
do_ddiv ();
RETURN ();
}
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# if TARGET_LONG_BITS > HOST_LONG_BITS
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void op_ddivu ( void )
{
do_ddivu ();
RETURN ();
}
# else
void op_ddivu ( void )
{
if ( T1 != 0 ) {
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env -> LO [ 0 ][ env -> current_tc ] = T0 / T1 ;
env -> HI [ 0 ][ env -> current_tc ] = T0 % T1 ;
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}
RETURN ();
}
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# endif
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# endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
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/* Logical */
void op_and ( void )
{
T0 &= T1 ;
RETURN ();
}
void op_nor ( void )
{
T0 = ~ ( T0 | T1 );
RETURN ();
}
void op_or ( void )
{
T0 |= T1 ;
RETURN ();
}
void op_xor ( void )
{
T0 ^= T1 ;
RETURN ();
}
void op_sll ( void )
{
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T0 = ( int32_t )(( uint32_t ) T0 << T1 );
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RETURN ();
}
void op_sra ( void )
{
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T0 = ( int32_t )(( int32_t ) T0 >> T1 );
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RETURN ();
}
void op_srl ( void )
{
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T0 = ( int32_t )(( uint32_t ) T0 >> T1 );
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RETURN ();
}
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void op_rotr ( void )
{
target_ulong tmp ;
if ( T1 ) {
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tmp = ( int32_t )(( uint32_t ) T0 << ( 0x20 - T1 ));
T0 = ( int32_t )(( uint32_t ) T0 >> T1 ) | tmp ;
}
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RETURN ();
}
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void op_sllv ( void )
{
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T0 = ( int32_t )(( uint32_t ) T1 << (( uint32_t ) T0 & 0x1F ));
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RETURN ();
}
void op_srav ( void )
{
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T0 = ( int32_t )(( int32_t ) T1 >> ( T0 & 0x1F ));
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RETURN ();
}
void op_srlv ( void )
{
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T0 = ( int32_t )(( uint32_t ) T1 >> ( T0 & 0x1F ));
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RETURN ();
}
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void op_rotrv ( void )
{
target_ulong tmp ;
T0 &= 0x1F ;
if ( T0 ) {
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tmp = ( int32_t )(( uint32_t ) T1 << ( 0x20 - T0 ));
T0 = ( int32_t )(( uint32_t ) T1 >> T0 ) | tmp ;
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} else
T0 = T1 ;
RETURN ();
}
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void op_clo ( void )
{
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T0 = clo32 ( T0 );
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RETURN ();
}
void op_clz ( void )
{
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T0 = clz32 ( T0 );
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RETURN ();
}
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# if defined ( TARGET_MIPSN32 ) || defined ( TARGET_MIPS64 )
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# if TARGET_LONG_BITS > HOST_LONG_BITS
/* Those might call libgcc functions. */
void op_dsll ( void )
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{
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CALL_FROM_TB0 ( do_dsll );
RETURN ();
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}
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void op_dsll32 ( void )
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{
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CALL_FROM_TB0 ( do_dsll32 );
RETURN ();
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}
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void op_dsra ( void )
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{
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CALL_FROM_TB0 ( do_dsra );
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RETURN ();
}
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void op_dsra32 ( void )
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{
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CALL_FROM_TB0 ( do_dsra32 );
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RETURN ();
}
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void op_dsrl ( void )
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{
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CALL_FROM_TB0 ( do_dsrl );
RETURN ();
}
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void op_dsrl32 ( void )
{
CALL_FROM_TB0 ( do_dsrl32 );
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RETURN ();
}
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void op_drotr ( void )
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{
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CALL_FROM_TB0 ( do_drotr );
RETURN ();
}
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void op_drotr32 ( void )
{
CALL_FROM_TB0 ( do_drotr32 );
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RETURN ();
}
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void op_dsllv ( void )
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{
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CALL_FROM_TB0 ( do_dsllv );
RETURN ();
}
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void op_dsrav ( void )
{
CALL_FROM_TB0 ( do_dsrav );
616
617
618
RETURN ();
}
ths
authored
18 years ago
619
void op_dsrlv ( void )
620
{
ths
authored
18 years ago
621
622
623
CALL_FROM_TB0 ( do_dsrlv );
RETURN ();
}
624
ths
authored
18 years ago
625
626
627
void op_drotrv ( void )
{
CALL_FROM_TB0 ( do_drotrv );
628
629
RETURN ();
}
ths
authored
18 years ago
630
ths
authored
17 years ago
631
632
633
634
635
636
637
638
639
640
641
642
void op_dclo ( void )
{
CALL_FROM_TB0 ( do_dclo );
RETURN ();
}
void op_dclz ( void )
{
CALL_FROM_TB0 ( do_dclz );
RETURN ();
}
ths
authored
18 years ago
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
# else /* TARGET_LONG_BITS > HOST_LONG_BITS */
void op_dsll ( void )
{
T0 = T0 << T1 ;
RETURN ();
}
void op_dsll32 ( void )
{
T0 = T0 << ( T1 + 32 );
RETURN ();
}
void op_dsra ( void )
{
T0 = ( int64_t ) T0 >> T1 ;
RETURN ();
}
void op_dsra32 ( void )
{
T0 = ( int64_t ) T0 >> ( T1 + 32 );
RETURN ();
}
void op_dsrl ( void )
{
T0 = T0 >> T1 ;
RETURN ();
}
void op_dsrl32 ( void )
{
T0 = T0 >> ( T1 + 32 );
RETURN ();
}
void op_drotr ( void )
{
target_ulong tmp ;
if ( T1 ) {
tmp = T0 << ( 0x40 - T1 );
T0 = ( T0 >> T1 ) | tmp ;
ths
authored
18 years ago
688
}
ths
authored
18 years ago
689
690
691
692
693
694
695
696
697
698
RETURN ();
}
void op_drotr32 ( void )
{
target_ulong tmp ;
if ( T1 ) {
tmp = T0 << ( 0x40 - ( 32 + T1 ));
T0 = ( T0 >> ( 32 + T1 )) | tmp ;
ths
authored
18 years ago
699
}
ths
authored
18 years ago
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
RETURN ();
}
void op_dsllv ( void )
{
T0 = T1 << ( T0 & 0x3F );
RETURN ();
}
void op_dsrav ( void )
{
T0 = ( int64_t ) T1 >> ( T0 & 0x3F );
RETURN ();
}
void op_dsrlv ( void )
{
T0 = T1 >> ( T0 & 0x3F );
RETURN ();
}
void op_drotrv ( void )
{
target_ulong tmp ;
T0 &= 0x3F ;
if ( T0 ) {
tmp = T1 << ( 0x40 - T0 );
T0 = ( T1 >> T0 ) | tmp ;
} else
T0 = T1 ;
RETURN ();
}
void op_dclo ( void )
{
ths
authored
17 years ago
736
T0 = clo64 ( T0 );
ths
authored
18 years ago
737
738
739
740
741
RETURN ();
}
void op_dclz ( void )
{
ths
authored
17 years ago
742
T0 = clz64 ( T0 );
ths
authored
18 years ago
743
744
RETURN ();
}
ths
authored
17 years ago
745
# endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
ths
authored
17 years ago
746
# endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
ths
authored
18 years ago
747
748
749
/* 64 bits arithmetic */
# if TARGET_LONG_BITS > HOST_LONG_BITS
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
void op_mult ( void )
{
CALL_FROM_TB0 ( do_mult );
RETURN ();
}
void op_multu ( void )
{
CALL_FROM_TB0 ( do_multu );
RETURN ();
}
void op_madd ( void )
{
CALL_FROM_TB0 ( do_madd );
RETURN ();
}
void op_maddu ( void )
{
CALL_FROM_TB0 ( do_maddu );
RETURN ();
}
void op_msub ( void )
{
CALL_FROM_TB0 ( do_msub );
RETURN ();
}
void op_msubu ( void )
{
CALL_FROM_TB0 ( do_msubu );
RETURN ();
}
ths
authored
18 years ago
785
786
787
# else /* TARGET_LONG_BITS > HOST_LONG_BITS */
ths
authored
17 years ago
788
static always_inline uint64_t get_HILO ( void )
ths
authored
18 years ago
789
{
ths
authored
17 years ago
790
791
return (( uint64_t ) env -> HI [ 0 ][ env -> current_tc ] << 32 ) |
(( uint64_t )( uint32_t ) env -> LO [ 0 ][ env -> current_tc ]);
ths
authored
18 years ago
792
793
}
ths
authored
17 years ago
794
static always_inline void set_HILO ( uint64_t HILO )
ths
authored
18 years ago
795
{
ths
authored
17 years ago
796
797
env -> LO [ 0 ][ env -> current_tc ] = ( int32_t )( HILO & 0xFFFFFFFF );
env -> HI [ 0 ][ env -> current_tc ] = ( int32_t )( HILO >> 32 );
ths
authored
18 years ago
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
}
void op_mult ( void )
{
set_HILO (( int64_t )( int32_t ) T0 * ( int64_t )( int32_t ) T1 );
RETURN ();
}
void op_multu ( void )
{
set_HILO (( uint64_t )( uint32_t ) T0 * ( uint64_t )( uint32_t ) T1 );
RETURN ();
}
void op_madd ( void )
{
int64_t tmp ;
tmp = (( int64_t )( int32_t ) T0 * ( int64_t )( int32_t ) T1 );
set_HILO (( int64_t ) get_HILO () + tmp );
RETURN ();
}
void op_maddu ( void )
{
uint64_t tmp ;
tmp = (( uint64_t )( uint32_t ) T0 * ( uint64_t )( uint32_t ) T1 );
set_HILO ( get_HILO () + tmp );
RETURN ();
}
void op_msub ( void )
{
int64_t tmp ;
tmp = (( int64_t )( int32_t ) T0 * ( int64_t )( int32_t ) T1 );
set_HILO (( int64_t ) get_HILO () - tmp );
RETURN ();
}
void op_msubu ( void )
{
uint64_t tmp ;
tmp = (( uint64_t )( uint32_t ) T0 * ( uint64_t )( uint32_t ) T1 );
set_HILO ( get_HILO () - tmp );
RETURN ();
}
# endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
ths
authored
17 years ago
849
# if defined ( TARGET_MIPSN32 ) || defined ( TARGET_MIPS64 )
ths
authored
18 years ago
850
851
void op_dmult ( void )
{
ths
authored
17 years ago
852
CALL_FROM_TB4 ( muls64 , & ( env -> LO [ 0 ][ env -> current_tc ]), & ( env -> HI [ 0 ][ env -> current_tc ]), T0 , T1 );
ths
authored
18 years ago
853
854
855
856
857
RETURN ();
}
void op_dmultu ( void )
{
ths
authored
17 years ago
858
CALL_FROM_TB4 ( mulu64 , & ( env -> LO [ 0 ][ env -> current_tc ]), & ( env -> HI [ 0 ][ env -> current_tc ]), T0 , T1 );
ths
authored
18 years ago
859
860
RETURN ();
}
861
862
863
864
865
866
# endif
/* Conditional moves */
void op_movn ( void )
{
if ( T1 != 0 )
ths
authored
17 years ago
867
env -> gpr [ PARAM1 ][ env -> current_tc ] = T0 ;
868
869
870
871
872
873
RETURN ();
}
void op_movz ( void )
{
if ( T1 == 0 )
ths
authored
17 years ago
874
env -> gpr [ PARAM1 ][ env -> current_tc ] = T0 ;
875
876
877
RETURN ();
}
ths
authored
18 years ago
878
879
void op_movf ( void )
{
ths
authored
17 years ago
880
if ( ! ( env -> fpu -> fcr31 & PARAM1 ))
ths
authored
18 years ago
881
T0 = T1 ;
ths
authored
18 years ago
882
883
884
885
886
RETURN ();
}
void op_movt ( void )
{
ths
authored
17 years ago
887
if ( env -> fpu -> fcr31 & PARAM1 )
ths
authored
18 years ago
888
T0 = T1 ;
ths
authored
18 years ago
889
890
891
RETURN ();
}
892
893
894
895
896
897
898
899
900
901
902
903
904
905
/* Tests */
# define OP_COND ( name , cond ) \
void glue ( op_ , name ) ( void ) \
{ \
if ( cond ) { \
T0 = 1 ; \
} else { \
T0 = 0 ; \
} \
RETURN (); \
}
OP_COND ( eq , T0 == T1 );
OP_COND ( ne , T0 != T1 );
ths
authored
18 years ago
906
OP_COND ( ge , ( target_long ) T0 >= ( target_long ) T1 );
907
OP_COND ( geu , T0 >= T1 );
ths
authored
18 years ago
908
OP_COND ( lt , ( target_long ) T0 < ( target_long ) T1 );
909
OP_COND ( ltu , T0 < T1 );
ths
authored
18 years ago
910
911
912
913
OP_COND ( gez , ( target_long ) T0 >= 0 );
OP_COND ( gtz , ( target_long ) T0 > 0 );
OP_COND ( lez , ( target_long ) T0 <= 0 );
OP_COND ( ltz , ( target_long ) T0 < 0 );
914
ths
authored
18 years ago
915
/* Branches */
916
917
918
void OPPROTO op_goto_tb0 ( void )
{
GOTO_TB ( op_goto_tb0 , PARAM1 , 0 );
ths
authored
18 years ago
919
RETURN ();
920
921
922
923
924
}
void OPPROTO op_goto_tb1 ( void )
{
GOTO_TB ( op_goto_tb1 , PARAM1 , 1 );
ths
authored
18 years ago
925
RETURN ();
926
}
927
928
929
930
931
/* Branch to register */
void op_save_breg_target ( void )
{
env -> btarget = T2 ;
ths
authored
18 years ago
932
RETURN ();
933
934
935
936
937
}
void op_restore_breg_target ( void )
{
T2 = env -> btarget ;
ths
authored
18 years ago
938
RETURN ();
939
940
941
942
}
void op_breg ( void )
{
ths
authored
17 years ago
943
env -> PC [ env -> current_tc ] = T2 ;
944
945
946
947
948
949
950
951
952
RETURN ();
}
void op_save_btarget ( void )
{
env -> btarget = PARAM1 ;
RETURN ();
}
ths
authored
17 years ago
953
# if defined ( TARGET_MIPSN32 ) || defined ( TARGET_MIPS64 )
ths
authored
18 years ago
954
955
956
957
958
959
960
void op_save_btarget64 ( void )
{
env -> btarget = (( uint64_t ) PARAM1 << 32 ) | ( uint32_t ) PARAM2 ;
RETURN ();
}
# endif
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
/* Conditional branch */
void op_set_bcond ( void )
{
T2 = T0 ;
RETURN ();
}
void op_save_bcond ( void )
{
env -> bcond = T2 ;
RETURN ();
}
void op_restore_bcond ( void )
{
T2 = env -> bcond ;
RETURN ();
}
980
void op_jnz_T2 ( void )
981
{
982
983
if ( T2 )
GOTO_LABEL_PARAM ( 1 );
984
985
986
987
RETURN ();
}
/* CP0 functions */
ths
authored
18 years ago
988
void op_mfc0_index ( void )
989
{
ths
authored
18 years ago
990
T0 = env -> CP0_Index ;
ths
authored
18 years ago
991
992
993
RETURN ();
}
ths
authored
17 years ago
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
void op_mfc0_mvpcontrol ( void )
{
T0 = env -> mvp -> CP0_MVPControl ;
RETURN ();
}
void op_mfc0_mvpconf0 ( void )
{
T0 = env -> mvp -> CP0_MVPConf0 ;
RETURN ();
}
void op_mfc0_mvpconf1 ( void )
{
T0 = env -> mvp -> CP0_MVPConf1 ;
RETURN ();
}
ths
authored
18 years ago
1012
1013
1014
1015
1016
1017
void op_mfc0_random ( void )
{
CALL_FROM_TB0 ( do_mfc0_random );
RETURN ();
}
ths
authored
17 years ago
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
void op_mfc0_vpecontrol ( void )
{
T0 = env -> CP0_VPEControl ;
RETURN ();
}
void op_mfc0_vpeconf0 ( void )
{
T0 = env -> CP0_VPEConf0 ;
RETURN ();
}
void op_mfc0_vpeconf1 ( void )
{
T0 = env -> CP0_VPEConf1 ;
RETURN ();
}
void op_mfc0_yqmask ( void )
{
T0 = env -> CP0_YQMask ;
RETURN ();
}
void op_mfc0_vpeschedule ( void )
{
T0 = env -> CP0_VPESchedule ;
RETURN ();
}
void op_mfc0_vpeschefback ( void )
{
T0 = env -> CP0_VPEScheFBack ;
RETURN ();
}
void op_mfc0_vpeopt ( void )
{
T0 = env -> CP0_VPEOpt ;
RETURN ();
}
ths
authored
18 years ago
1060
1061
void op_mfc0_entrylo0 ( void )
{
ths
authored
18 years ago
1062
T0 = ( int32_t ) env -> CP0_EntryLo0 ;
ths
authored
18 years ago
1063
1064
1065
RETURN ();
}
ths
authored
17 years ago
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
void op_mfc0_tcstatus ( void )
{
T0 = env -> CP0_TCStatus [ env -> current_tc ];
RETURN ();
}
void op_mftc0_tcstatus ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> CP0_TCStatus [ other_tc ];
RETURN ();
}
void op_mfc0_tcbind ( void )
{
T0 = env -> CP0_TCBind [ env -> current_tc ];
RETURN ();
}
void op_mftc0_tcbind ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> CP0_TCBind [ other_tc ];
RETURN ();
}
void op_mfc0_tcrestart ( void )
{
T0 = env -> PC [ env -> current_tc ];
RETURN ();
}
void op_mftc0_tcrestart ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> PC [ other_tc ];
RETURN ();
}
void op_mfc0_tchalt ( void )
{
T0 = env -> CP0_TCHalt [ env -> current_tc ];
RETURN ();
}
void op_mftc0_tchalt ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> CP0_TCHalt [ other_tc ];
RETURN ();
}
void op_mfc0_tccontext ( void )
{
T0 = env -> CP0_TCContext [ env -> current_tc ];
RETURN ();
}
void op_mftc0_tccontext ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> CP0_TCContext [ other_tc ];
RETURN ();
}
void op_mfc0_tcschedule ( void )
{
T0 = env -> CP0_TCSchedule [ env -> current_tc ];
RETURN ();
}
void op_mftc0_tcschedule ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> CP0_TCSchedule [ other_tc ];
RETURN ();
}
void op_mfc0_tcschefback ( void )
{
T0 = env -> CP0_TCScheFBack [ env -> current_tc ];
RETURN ();
}
void op_mftc0_tcschefback ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> CP0_TCScheFBack [ other_tc ];
RETURN ();
}
ths
authored
18 years ago
1164
1165
void op_mfc0_entrylo1 ( void )
{
ths
authored
18 years ago
1166
T0 = ( int32_t ) env -> CP0_EntryLo1 ;
ths
authored
18 years ago
1167
1168
1169
1170
1171
RETURN ();
}
void op_mfc0_context ( void )
{
ths
authored
18 years ago
1172
T0 = ( int32_t ) env -> CP0_Context ;
ths
authored
18 years ago
1173
1174
1175
1176
1177
RETURN ();
}
void op_mfc0_pagemask ( void )
{
ths
authored
18 years ago
1178
T0 = env -> CP0_PageMask ;
ths
authored
18 years ago
1179
1180
1181
RETURN ();
}
ths
authored
18 years ago
1182
1183
void op_mfc0_pagegrain ( void )
{
ths
authored
18 years ago
1184
T0 = env -> CP0_PageGrain ;
ths
authored
18 years ago
1185
1186
1187
RETURN ();
}
ths
authored
18 years ago
1188
1189
void op_mfc0_wired ( void )
{
ths
authored
18 years ago
1190
T0 = env -> CP0_Wired ;
ths
authored
18 years ago
1191
1192
1193
RETURN ();
}
ths
authored
17 years ago
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
void op_mfc0_srsconf0 ( void )
{
T0 = env -> CP0_SRSConf0 ;
RETURN ();
}
void op_mfc0_srsconf1 ( void )
{
T0 = env -> CP0_SRSConf1 ;
RETURN ();
}
void op_mfc0_srsconf2 ( void )
{
T0 = env -> CP0_SRSConf2 ;
RETURN ();
}
void op_mfc0_srsconf3 ( void )
{
T0 = env -> CP0_SRSConf3 ;
RETURN ();
}
void op_mfc0_srsconf4 ( void )
{
T0 = env -> CP0_SRSConf4 ;
RETURN ();
}
ths
authored
18 years ago
1224
1225
void op_mfc0_hwrena ( void )
{
ths
authored
18 years ago
1226
T0 = env -> CP0_HWREna ;
ths
authored
18 years ago
1227
1228
1229
RETURN ();
}
ths
authored
18 years ago
1230
1231
void op_mfc0_badvaddr ( void )
{
ths
authored
18 years ago
1232
T0 = ( int32_t ) env -> CP0_BadVAddr ;
ths
authored
18 years ago
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
RETURN ();
}
void op_mfc0_count ( void )
{
CALL_FROM_TB0 ( do_mfc0_count );
RETURN ();
}
void op_mfc0_entryhi ( void )
{
ths
authored
18 years ago
1244
T0 = ( int32_t ) env -> CP0_EntryHi ;
ths
authored
18 years ago
1245
1246
1247
RETURN ();
}
ths
authored
17 years ago
1248
1249
1250
1251
1252
1253
1254
1255
void op_mftc0_entryhi ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = ( env -> CP0_EntryHi & ~ 0xff ) | ( env -> CP0_TCStatus [ other_tc ] & 0xff );
RETURN ();
}
ths
authored
18 years ago
1256
1257
void op_mfc0_compare ( void )
{
ths
authored
18 years ago
1258
T0 = env -> CP0_Compare ;
ths
authored
18 years ago
1259
1260
1261
1262
1263
RETURN ();
}
void op_mfc0_status ( void )
{
ths
authored
18 years ago
1264
T0 = env -> CP0_Status ;
ths
authored
18 years ago
1265
1266
1267
RETURN ();
}
ths
authored
17 years ago
1268
1269
1270
1271
1272
1273
1274
1275
void op_mftc0_status ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
uint32_t tcstatus = env -> CP0_TCStatus [ other_tc ];
T0 = env -> CP0_Status & ~ 0xf1000018 ;
T0 |= tcstatus & ( 0xf << CP0TCSt_TCU0 );
T0 |= ( tcstatus & ( 1 << CP0TCSt_TMX )) >> ( CP0TCSt_TMX - CP0St_MX );
ths
authored
17 years ago
1276
T0 |= ( tcstatus & ( 0x3 << CP0TCSt_TKSU )) >> ( CP0TCSt_TKSU - CP0St_KSU );
ths
authored
17 years ago
1277
1278
1279
RETURN ();
}
ths
authored
18 years ago
1280
1281
void op_mfc0_intctl ( void )
{
ths
authored
18 years ago
1282
T0 = env -> CP0_IntCtl ;
ths
authored
18 years ago
1283
1284
1285
1286
1287
RETURN ();
}
void op_mfc0_srsctl ( void )
{
ths
authored
18 years ago
1288
1289
1290
1291
1292
1293
1294
T0 = env -> CP0_SRSCtl ;
RETURN ();
}
void op_mfc0_srsmap ( void )
{
T0 = env -> CP0_SRSMap ;
ths
authored
18 years ago
1295
1296
1297
RETURN ();
}
ths
authored
18 years ago
1298
1299
void op_mfc0_cause ( void )
{
ths
authored
18 years ago
1300
T0 = env -> CP0_Cause ;
ths
authored
18 years ago
1301
1302
1303
1304
1305
RETURN ();
}
void op_mfc0_epc ( void )
{
ths
authored
18 years ago
1306
T0 = ( int32_t ) env -> CP0_EPC ;
ths
authored
18 years ago
1307
1308
1309
1310
1311
RETURN ();
}
void op_mfc0_prid ( void )
{
ths
authored
18 years ago
1312
T0 = env -> CP0_PRid ;
ths
authored
18 years ago
1313
1314
1315
RETURN ();
}
ths
authored
18 years ago
1316
1317
void op_mfc0_ebase ( void )
{
ths
authored
18 years ago
1318
T0 = env -> CP0_EBase ;
ths
authored
18 years ago
1319
1320
1321
RETURN ();
}
ths
authored
18 years ago
1322
1323
void op_mfc0_config0 ( void )
{
ths
authored
18 years ago
1324
T0 = env -> CP0_Config0 ;
ths
authored
18 years ago
1325
1326
1327
1328
1329
RETURN ();
}
void op_mfc0_config1 ( void )
{
ths
authored
18 years ago
1330
T0 = env -> CP0_Config1 ;
ths
authored
18 years ago
1331
1332
1333
RETURN ();
}
ths
authored
18 years ago
1334
1335
void op_mfc0_config2 ( void )
{
ths
authored
18 years ago
1336
T0 = env -> CP0_Config2 ;
ths
authored
18 years ago
1337
1338
1339
1340
1341
RETURN ();
}
void op_mfc0_config3 ( void )
{
ths
authored
18 years ago
1342
T0 = env -> CP0_Config3 ;
ths
authored
18 years ago
1343
1344
1345
RETURN ();
}
ths
authored
18 years ago
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
void op_mfc0_config6 ( void )
{
T0 = env -> CP0_Config6 ;
RETURN ();
}
void op_mfc0_config7 ( void )
{
T0 = env -> CP0_Config7 ;
RETURN ();
}
ths
authored
18 years ago
1358
1359
void op_mfc0_lladdr ( void )
{
ths
authored
18 years ago
1360
T0 = ( int32_t ) env -> CP0_LLAddr >> 4 ;
ths
authored
18 years ago
1361
1362
1363
RETURN ();
}
ths
authored
18 years ago
1364
void op_mfc0_watchlo ( void )
ths
authored
18 years ago
1365
{
ths
authored
18 years ago
1366
T0 = ( int32_t ) env -> CP0_WatchLo [ PARAM1 ];
ths
authored
18 years ago
1367
1368
1369
RETURN ();
}
ths
authored
18 years ago
1370
void op_mfc0_watchhi ( void )
ths
authored
18 years ago
1371
{
ths
authored
18 years ago
1372
T0 = env -> CP0_WatchHi [ PARAM1 ];
ths
authored
18 years ago
1373
1374
1375
RETURN ();
}
ths
authored
18 years ago
1376
1377
void op_mfc0_xcontext ( void )
{
ths
authored
18 years ago
1378
T0 = ( int32_t ) env -> CP0_XContext ;
ths
authored
18 years ago
1379
1380
1381
1382
1383
1384
1385
1386
1387
RETURN ();
}
void op_mfc0_framemask ( void )
{
T0 = env -> CP0_Framemask ;
RETURN ();
}
ths
authored
18 years ago
1388
1389
void op_mfc0_debug ( void )
{
ths
authored
18 years ago
1390
T0 = env -> CP0_Debug ;
ths
authored
18 years ago
1391
1392
1393
1394
1395
if ( env -> hflags & MIPS_HFLAG_DM )
T0 |= 1 << CP0DB_DM ;
RETURN ();
}
ths
authored
17 years ago
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
void op_mftc0_debug ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
/* XXX: Might be wrong, check with EJTAG spec. */
T0 = ( env -> CP0_Debug & ~ (( 1 << CP0DB_SSt ) | ( 1 << CP0DB_Halt ))) |
( env -> CP0_Debug_tcstatus [ other_tc ] &
(( 1 << CP0DB_SSt ) | ( 1 << CP0DB_Halt )));
RETURN ();
}
ths
authored
18 years ago
1407
1408
void op_mfc0_depc ( void )
{
ths
authored
18 years ago
1409
T0 = ( int32_t ) env -> CP0_DEPC ;
ths
authored
18 years ago
1410
1411
1412
RETURN ();
}
ths
authored
18 years ago
1413
1414
void op_mfc0_performance0 ( void )
{
ths
authored
18 years ago
1415
T0 = env -> CP0_Performance0 ;
ths
authored
18 years ago
1416
1417
1418
RETURN ();
}
ths
authored
18 years ago
1419
1420
void op_mfc0_taglo ( void )
{
ths
authored
18 years ago
1421
T0 = env -> CP0_TagLo ;
ths
authored
18 years ago
1422
1423
1424
1425
1426
RETURN ();
}
void op_mfc0_datalo ( void )
{
ths
authored
18 years ago
1427
T0 = env -> CP0_DataLo ;
ths
authored
18 years ago
1428
1429
1430
RETURN ();
}
ths
authored
18 years ago
1431
1432
void op_mfc0_taghi ( void )
{
ths
authored
18 years ago
1433
T0 = env -> CP0_TagHi ;
ths
authored
18 years ago
1434
1435
1436
1437
1438
RETURN ();
}
void op_mfc0_datahi ( void )
{
ths
authored
18 years ago
1439
T0 = env -> CP0_DataHi ;
ths
authored
18 years ago
1440
1441
1442
RETURN ();
}
ths
authored
18 years ago
1443
1444
void op_mfc0_errorepc ( void )
{
ths
authored
18 years ago
1445
T0 = ( int32_t ) env -> CP0_ErrorEPC ;
ths
authored
18 years ago
1446
1447
1448
1449
1450
RETURN ();
}
void op_mfc0_desave ( void )
{
ths
authored
18 years ago
1451
T0 = env -> CP0_DESAVE ;
1452
1453
1454
RETURN ();
}
ths
authored
18 years ago
1455
void op_mtc0_index ( void )
1456
{
ths
authored
17 years ago
1457
1458
1459
1460
1461
1462
1463
1464
int num = 1 ;
unsigned int tmp = env -> tlb -> nb_tlb ;
do {
tmp >>= 1 ;
num <<= 1 ;
} while ( tmp );
env -> CP0_Index = ( env -> CP0_Index & 0x80000000 ) | ( T0 & ( num - 1 ));
ths
authored
17 years ago
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
RETURN ();
}
void op_mtc0_mvpcontrol ( void )
{
uint32_t mask = 0 ;
uint32_t newval ;
if ( env -> CP0_VPEConf0 & ( 1 << CP0VPEC0_MVP ))
mask |= ( 1 << CP0MVPCo_CPA ) | ( 1 << CP0MVPCo_VPC ) |
( 1 << CP0MVPCo_EVP );
if ( env -> mvp -> CP0_MVPControl & ( 1 << CP0MVPCo_VPC ))
mask |= ( 1 << CP0MVPCo_STLB );
newval = ( env -> mvp -> CP0_MVPControl & ~ mask ) | ( T0 & mask );
// TODO : Enable / disable shared TLB , enable / disable VPEs .
env -> mvp -> CP0_MVPControl = newval ;
RETURN ();
}
void op_mtc0_vpecontrol ( void )
{
uint32_t mask ;
uint32_t newval ;
mask = ( 1 << CP0VPECo_YSI ) | ( 1 << CP0VPECo_GSI ) |
( 1 << CP0VPECo_TE ) | ( 0xff << CP0VPECo_TargTC );
newval = ( env -> CP0_VPEControl & ~ mask ) | ( T0 & mask );
/* Yield scheduler intercept not implemented. */
/* Gating storage scheduler intercept not implemented. */
// TODO : Enable / disable TCs .
env -> CP0_VPEControl = newval ;
RETURN ();
}
void op_mtc0_vpeconf0 ( void )
{
uint32_t mask = 0 ;
uint32_t newval ;
if ( env -> CP0_VPEConf0 & ( 1 << CP0VPEC0_MVP )) {
if ( env -> CP0_VPEConf0 & ( 1 << CP0VPEC0_VPA ))
mask |= ( 0xff << CP0VPEC0_XTC );
mask |= ( 1 << CP0VPEC0_MVP ) | ( 1 << CP0VPEC0_VPA );
}
newval = ( env -> CP0_VPEConf0 & ~ mask ) | ( T0 & mask );
// TODO : TC exclusive handling due to ERL / EXL .
env -> CP0_VPEConf0 = newval ;
RETURN ();
}
void op_mtc0_vpeconf1 ( void )
{
uint32_t mask = 0 ;
uint32_t newval ;
if ( env -> mvp -> CP0_MVPControl & ( 1 << CP0MVPCo_VPC ))
mask |= ( 0xff << CP0VPEC1_NCX ) | ( 0xff << CP0VPEC1_NCP2 ) |
( 0xff << CP0VPEC1_NCP1 );
newval = ( env -> CP0_VPEConf1 & ~ mask ) | ( T0 & mask );
/* UDI not implemented. */
/* CP2 not implemented. */
// TODO : Handle FPU ( CP1 ) binding .
env -> CP0_VPEConf1 = newval ;
RETURN ();
}
void op_mtc0_yqmask ( void )
{
/* Yield qualifier inputs not implemented. */
env -> CP0_YQMask = 0x00000000 ;
RETURN ();
}
void op_mtc0_vpeschedule ( void )
{
env -> CP0_VPESchedule = T0 ;
RETURN ();
}
void op_mtc0_vpeschefback ( void )
{
env -> CP0_VPEScheFBack = T0 ;
RETURN ();
}
void op_mtc0_vpeopt ( void )
{
env -> CP0_VPEOpt = T0 & 0x0000ffff ;
ths
authored
18 years ago
1563
1564
1565
1566
1567
RETURN ();
}
void op_mtc0_entrylo0 ( void )
{
ths
authored
18 years ago
1568
1569
/* Large physaddr not implemented */
/* 1k pages not implemented */
ths
authored
18 years ago
1570
env -> CP0_EntryLo0 = T0 & 0x3FFFFFFF ;
ths
authored
18 years ago
1571
1572
1573
RETURN ();
}
ths
authored
17 years ago
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
void op_mtc0_tcstatus ( void )
{
uint32_t mask = env -> CP0_TCStatus_rw_bitmask ;
uint32_t newval ;
newval = ( env -> CP0_TCStatus [ env -> current_tc ] & ~ mask ) | ( T0 & mask );
// TODO : Sync with CP0_Status .
env -> CP0_TCStatus [ env -> current_tc ] = newval ;
RETURN ();
}
void op_mttc0_tcstatus ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
// TODO : Sync with CP0_Status .
env -> CP0_TCStatus [ other_tc ] = T0 ;
RETURN ();
}
void op_mtc0_tcbind ( void )
{
uint32_t mask = ( 1 << CP0TCBd_TBE );
uint32_t newval ;
if ( env -> mvp -> CP0_MVPControl & ( 1 << CP0MVPCo_VPC ))
mask |= ( 1 << CP0TCBd_CurVPE );
newval = ( env -> CP0_TCBind [ env -> current_tc ] & ~ mask ) | ( T0 & mask );
env -> CP0_TCBind [ env -> current_tc ] = newval ;
RETURN ();
}
void op_mttc0_tcbind ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
uint32_t mask = ( 1 << CP0TCBd_TBE );
uint32_t newval ;
if ( env -> mvp -> CP0_MVPControl & ( 1 << CP0MVPCo_VPC ))
mask |= ( 1 << CP0TCBd_CurVPE );
newval = ( env -> CP0_TCBind [ other_tc ] & ~ mask ) | ( T0 & mask );
env -> CP0_TCBind [ other_tc ] = newval ;
RETURN ();
}
void op_mtc0_tcrestart ( void )
{
env -> PC [ env -> current_tc ] = T0 ;
env -> CP0_TCStatus [ env -> current_tc ] &= ~ ( 1 << CP0TCSt_TDS );
env -> CP0_LLAddr = 0ULL ;
/* MIPS16 not implemented. */
RETURN ();
}
void op_mttc0_tcrestart ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
env -> PC [ other_tc ] = T0 ;
env -> CP0_TCStatus [ other_tc ] &= ~ ( 1 << CP0TCSt_TDS );
env -> CP0_LLAddr = 0ULL ;
/* MIPS16 not implemented. */
RETURN ();
}
void op_mtc0_tchalt ( void )
{
env -> CP0_TCHalt [ env -> current_tc ] = T0 & 0x1 ;
// TODO : Halt TC / Restart ( if allocated + active ) TC .
RETURN ();
}
void op_mttc0_tchalt ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
// TODO : Halt TC / Restart ( if allocated + active ) TC .
env -> CP0_TCHalt [ other_tc ] = T0 ;
RETURN ();
}
void op_mtc0_tccontext ( void )
{
env -> CP0_TCContext [ env -> current_tc ] = T0 ;
RETURN ();
}
void op_mttc0_tccontext ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
env -> CP0_TCContext [ other_tc ] = T0 ;
RETURN ();
}
void op_mtc0_tcschedule ( void )
{
env -> CP0_TCSchedule [ env -> current_tc ] = T0 ;
RETURN ();
}
void op_mttc0_tcschedule ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
env -> CP0_TCSchedule [ other_tc ] = T0 ;
RETURN ();
}
void op_mtc0_tcschefback ( void )
{
env -> CP0_TCScheFBack [ env -> current_tc ] = T0 ;
RETURN ();
}
void op_mttc0_tcschefback ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
env -> CP0_TCScheFBack [ other_tc ] = T0 ;
RETURN ();
}
ths
authored
18 years ago
1703
1704
void op_mtc0_entrylo1 ( void )
{
ths
authored
18 years ago
1705
1706
/* Large physaddr not implemented */
/* 1k pages not implemented */
ths
authored
18 years ago
1707
env -> CP0_EntryLo1 = T0 & 0x3FFFFFFF ;
ths
authored
18 years ago
1708
1709
1710
1711
1712
RETURN ();
}
void op_mtc0_context ( void )
{
ths
authored
18 years ago
1713
env -> CP0_Context = ( env -> CP0_Context & 0x007FFFFF ) | ( T0 & ~ 0x007FFFFF );
ths
authored
18 years ago
1714
1715
1716
1717
1718
RETURN ();
}
void op_mtc0_pagemask ( void )
{
ths
authored
18 years ago
1719
/* 1k pages not implemented */
ths
authored
18 years ago
1720
env -> CP0_PageMask = T0 & ( 0x1FFFFFFF & ( TARGET_PAGE_MASK << 1 ));
ths
authored
18 years ago
1721
1722
1723
1724
1725
1726
1727
1728
1729
RETURN ();
}
void op_mtc0_pagegrain ( void )
{
/* SmartMIPS not implemented */
/* Large physaddr not implemented */
/* 1k pages not implemented */
env -> CP0_PageGrain = 0 ;
ths
authored
18 years ago
1730
1731
1732
1733
1734
RETURN ();
}
void op_mtc0_wired ( void )
{
ths
authored
17 years ago
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
env -> CP0_Wired = T0 % env -> tlb -> nb_tlb ;
RETURN ();
}
void op_mtc0_srsconf0 ( void )
{
env -> CP0_SRSConf0 |= T0 & env -> CP0_SRSConf0_rw_bitmask ;
RETURN ();
}
void op_mtc0_srsconf1 ( void )
{
env -> CP0_SRSConf1 |= T0 & env -> CP0_SRSConf1_rw_bitmask ;
RETURN ();
}
void op_mtc0_srsconf2 ( void )
{
env -> CP0_SRSConf2 |= T0 & env -> CP0_SRSConf2_rw_bitmask ;
RETURN ();
}
void op_mtc0_srsconf3 ( void )
{
env -> CP0_SRSConf3 |= T0 & env -> CP0_SRSConf3_rw_bitmask ;
RETURN ();
}
void op_mtc0_srsconf4 ( void )
{
env -> CP0_SRSConf4 |= T0 & env -> CP0_SRSConf4_rw_bitmask ;
ths
authored
18 years ago
1766
1767
1768
1769
1770
1771
RETURN ();
}
void op_mtc0_hwrena ( void )
{
env -> CP0_HWREna = T0 & 0x0000000F ;
ths
authored
18 years ago
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
RETURN ();
}
void op_mtc0_count ( void )
{
CALL_FROM_TB2 ( cpu_mips_store_count , env , T0 );
RETURN ();
}
void op_mtc0_entryhi ( void )
{
ths
authored
18 years ago
1783
target_ulong old , val ;
ths
authored
18 years ago
1784
ths
authored
18 years ago
1785
/* 1k pages not implemented */
ths
authored
18 years ago
1786
val = T0 & (( TARGET_PAGE_MASK << 1 ) | 0xFF );
ths
authored
17 years ago
1787
# if defined ( TARGET_MIPSN32 ) || defined ( TARGET_MIPS64 )
ths
authored
18 years ago
1788
val &= env -> SEGMask ;
ths
authored
18 years ago
1789
# endif
ths
authored
18 years ago
1790
1791
old = env -> CP0_EntryHi ;
env -> CP0_EntryHi = val ;
ths
authored
17 years ago
1792
1793
1794
1795
if ( env -> CP0_Config3 & ( 1 << CP0C3_MT )) {
uint32_t tcst = env -> CP0_TCStatus [ env -> current_tc ] & ~ 0xff ;
env -> CP0_TCStatus [ env -> current_tc ] = tcst | ( val & 0xff );
}
ths
authored
18 years ago
1796
1797
1798
1799
1800
1801
/* If the ASID changes, flush qemu's TLB. */
if (( old & 0xFF ) != ( val & 0xFF ))
CALL_FROM_TB2 ( cpu_mips_tlb_flush , env , 1 );
RETURN ();
}
ths
authored
17 years ago
1802
1803
1804
1805
1806
1807
1808
1809
1810
void op_mttc0_entryhi ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
env -> CP0_EntryHi = ( env -> CP0_EntryHi & 0xff ) | ( T0 & ~ 0xff );
env -> CP0_TCStatus [ other_tc ] = ( env -> CP0_TCStatus [ other_tc ] & ~ 0xff ) | ( T0 & 0xff );
RETURN ();
}
ths
authored
18 years ago
1811
1812
1813
1814
1815
1816
1817
1818
void op_mtc0_compare ( void )
{
CALL_FROM_TB2 ( cpu_mips_store_compare , env , T0 );
RETURN ();
}
void op_mtc0_status ( void )
{
ths
authored
18 years ago
1819
uint32_t val , old ;
ths
authored
17 years ago
1820
uint32_t mask = env -> CP0_Status_rw_bitmask ;
ths
authored
18 years ago
1821
ths
authored
18 years ago
1822
val = T0 & mask ;
ths
authored
18 years ago
1823
old = env -> CP0_Status ;
ths
authored
18 years ago
1824
env -> CP0_Status = ( env -> CP0_Status & ~ mask ) | val ;
ths
authored
17 years ago
1825
CALL_FROM_TB1 ( compute_hflags , env );
ths
authored
18 years ago
1826
1827
if ( loglevel & CPU_LOG_EXEC )
CALL_FROM_TB2 ( do_mtc0_status_debug , old , val );
ths
authored
18 years ago
1828
CALL_FROM_TB1 ( cpu_mips_update_irq , env );
ths
authored
18 years ago
1829
1830
1831
RETURN ();
}
ths
authored
17 years ago
1832
1833
1834
1835
1836
1837
1838
1839
void op_mttc0_status ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
uint32_t tcstatus = env -> CP0_TCStatus [ other_tc ];
env -> CP0_Status = T0 & ~ 0xf1000018 ;
tcstatus = ( tcstatus & ~ ( 0xf << CP0TCSt_TCU0 )) | ( T0 & ( 0xf << CP0St_CU0 ));
tcstatus = ( tcstatus & ~ ( 1 << CP0TCSt_TMX )) | (( T0 & ( 1 << CP0St_MX )) << ( CP0TCSt_TMX - CP0St_MX ));
ths
authored
17 years ago
1840
tcstatus = ( tcstatus & ~ ( 0x3 << CP0TCSt_TKSU )) | (( T0 & ( 0x3 << CP0St_KSU )) << ( CP0TCSt_TKSU - CP0St_KSU ));
ths
authored
17 years ago
1841
1842
1843
1844
env -> CP0_TCStatus [ other_tc ] = tcstatus ;
RETURN ();
}
ths
authored
18 years ago
1845
1846
void op_mtc0_intctl ( void )
{
ths
authored
17 years ago
1847
1848
/* vectored interrupts not implemented, no performance counters. */
env -> CP0_IntCtl = ( env -> CP0_IntCtl & ~ 0x000002e0 ) | ( T0 & 0x000002e0 );
ths
authored
18 years ago
1849
1850
1851
1852
1853
RETURN ();
}
void op_mtc0_srsctl ( void )
{
ths
authored
17 years ago
1854
1855
uint32_t mask = ( 0xf << CP0SRSCtl_ESS ) | ( 0xf << CP0SRSCtl_PSS );
env -> CP0_SRSCtl = ( env -> CP0_SRSCtl & ~ mask ) | ( T0 & mask );
ths
authored
18 years ago
1856
1857
1858
RETURN ();
}
ths
authored
18 years ago
1859
1860
void op_mtc0_srsmap ( void )
{
ths
authored
17 years ago
1861
env -> CP0_SRSMap = T0 ;
ths
authored
18 years ago
1862
1863
1864
RETURN ();
}
ths
authored
18 years ago
1865
1866
void op_mtc0_cause ( void )
{
ths
authored
18 years ago
1867
uint32_t mask = 0x00C00300 ;
ths
authored
17 years ago
1868
uint32_t old = env -> CP0_Cause ;
ths
authored
18 years ago
1869
ths
authored
17 years ago
1870
if ( env -> insn_flags & ISA_MIPS32R2 )
ths
authored
18 years ago
1871
1872
mask |= 1 << CP0Ca_DC ;
ths
authored
18 years ago
1873
env -> CP0_Cause = ( env -> CP0_Cause & ~ mask ) | ( T0 & mask );
ths
authored
18 years ago
1874
ths
authored
17 years ago
1875
1876
1877
1878
1879
1880
1881
if (( old ^ env -> CP0_Cause ) & ( 1 << CP0Ca_DC )) {
if ( env -> CP0_Cause & ( 1 << CP0Ca_DC ))
CALL_FROM_TB1 ( cpu_mips_stop_count , env );
else
CALL_FROM_TB1 ( cpu_mips_start_count , env );
}
ths
authored
18 years ago
1882
1883
1884
1885
/* Handle the software interrupt as an hardware one , as they
are very similar */
if ( T0 & CP0Ca_IP_mask ) {
CALL_FROM_TB1 ( cpu_mips_update_irq , env );
ths
authored
18 years ago
1886
1887
1888
1889
1890
1891
}
RETURN ();
}
void op_mtc0_epc ( void )
{
ths
authored
18 years ago
1892
env -> CP0_EPC = T0 ;
ths
authored
18 years ago
1893
1894
1895
RETURN ();
}
ths
authored
18 years ago
1896
1897
1898
1899
void op_mtc0_ebase ( void )
{
/* vectored interrupts not implemented */
/* Multi-CPU not implemented */
ths
authored
18 years ago
1900
env -> CP0_EBase = 0x80000000 | ( T0 & 0x3FFFF000 );
ths
authored
18 years ago
1901
1902
1903
RETURN ();
}
ths
authored
18 years ago
1904
1905
void op_mtc0_config0 ( void )
{
ths
authored
18 years ago
1906
env -> CP0_Config0 = ( env -> CP0_Config0 & 0x81FFFFF8 ) | ( T0 & 0x00000007 );
ths
authored
18 years ago
1907
1908
1909
RETURN ();
}
ths
authored
18 years ago
1910
1911
1912
1913
1914
1915
1916
void op_mtc0_config2 ( void )
{
/* tertiary/secondary caches not implemented */
env -> CP0_Config2 = ( env -> CP0_Config2 & 0x8FFF0FFF );
RETURN ();
}
ths
authored
18 years ago
1917
void op_mtc0_watchlo ( void )
ths
authored
18 years ago
1918
{
ths
authored
18 years ago
1919
1920
/* Watch exceptions for instructions , data loads , data stores
not implemented . */
ths
authored
18 years ago
1921
env -> CP0_WatchLo [ PARAM1 ] = ( T0 & ~ 0x7 );
ths
authored
18 years ago
1922
1923
1924
RETURN ();
}
ths
authored
18 years ago
1925
void op_mtc0_watchhi ( void )
ths
authored
18 years ago
1926
{
ths
authored
18 years ago
1927
1928
env -> CP0_WatchHi [ PARAM1 ] = ( T0 & 0x40FF0FF8 );
env -> CP0_WatchHi [ PARAM1 ] &= ~ ( env -> CP0_WatchHi [ PARAM1 ] & T0 & 0x7 );
ths
authored
18 years ago
1929
1930
1931
RETURN ();
}
ths
authored
17 years ago
1932
1933
1934
1935
1936
1937
1938
void op_mtc0_xcontext ( void )
{
target_ulong mask = ( 1ULL << ( env -> SEGBITS - 7 )) - 1 ;
env -> CP0_XContext = ( env -> CP0_XContext & mask ) | ( T0 & ~ mask );
RETURN ();
}
ths
authored
18 years ago
1939
1940
1941
1942
1943
1944
void op_mtc0_framemask ( void )
{
env -> CP0_Framemask = T0 ; /* XXX */
RETURN ();
}
ths
authored
18 years ago
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
void op_mtc0_debug ( void )
{
env -> CP0_Debug = ( env -> CP0_Debug & 0x8C03FC1F ) | ( T0 & 0x13300120 );
if ( T0 & ( 1 << CP0DB_DM ))
env -> hflags |= MIPS_HFLAG_DM ;
else
env -> hflags &= ~ MIPS_HFLAG_DM ;
RETURN ();
}
ths
authored
17 years ago
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
void op_mttc0_debug ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
/* XXX: Might be wrong, check with EJTAG spec. */
env -> CP0_Debug_tcstatus [ other_tc ] = T0 & (( 1 << CP0DB_SSt ) | ( 1 << CP0DB_Halt ));
env -> CP0_Debug = ( env -> CP0_Debug & (( 1 << CP0DB_SSt ) | ( 1 << CP0DB_Halt ))) |
( T0 & ~ (( 1 << CP0DB_SSt ) | ( 1 << CP0DB_Halt )));
RETURN ();
}
ths
authored
18 years ago
1966
1967
void op_mtc0_depc ( void )
{
ths
authored
18 years ago
1968
env -> CP0_DEPC = T0 ;
ths
authored
18 years ago
1969
1970
1971
RETURN ();
}
ths
authored
18 years ago
1972
1973
void op_mtc0_performance0 ( void )
{
ths
authored
17 years ago
1974
env -> CP0_Performance0 = T0 & 0x000007ff ;
ths
authored
18 years ago
1975
1976
1977
RETURN ();
}
ths
authored
18 years ago
1978
1979
void op_mtc0_taglo ( void )
{
ths
authored
18 years ago
1980
env -> CP0_TagLo = T0 & 0xFFFFFCF6 ;
ths
authored
18 years ago
1981
1982
1983
RETURN ();
}
ths
authored
18 years ago
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
void op_mtc0_datalo ( void )
{
env -> CP0_DataLo = T0 ; /* XXX */
RETURN ();
}
void op_mtc0_taghi ( void )
{
env -> CP0_TagHi = T0 ; /* XXX */
RETURN ();
}
void op_mtc0_datahi ( void )
{
env -> CP0_DataHi = T0 ; /* XXX */
RETURN ();
}
ths
authored
18 years ago
2002
2003
void op_mtc0_errorepc ( void )
{
ths
authored
18 years ago
2004
env -> CP0_ErrorEPC = T0 ;
ths
authored
18 years ago
2005
2006
2007
2008
2009
2010
RETURN ();
}
void op_mtc0_desave ( void )
{
env -> CP0_DESAVE = T0 ;
2011
2012
2013
RETURN ();
}
ths
authored
17 years ago
2014
# if defined ( TARGET_MIPSN32 ) || defined ( TARGET_MIPS64 )
ths
authored
17 years ago
2015
void op_dmfc0_yqmask ( void )
ths
authored
18 years ago
2016
{
ths
authored
17 years ago
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
T0 = env -> CP0_YQMask ;
RETURN ();
}
void op_dmfc0_vpeschedule ( void )
{
T0 = env -> CP0_VPESchedule ;
RETURN ();
}
void op_dmfc0_vpeschefback ( void )
{
T0 = env -> CP0_VPEScheFBack ;
ths
authored
18 years ago
2030
2031
2032
RETURN ();
}
ths
authored
18 years ago
2033
2034
2035
2036
2037
2038
void op_dmfc0_entrylo0 ( void )
{
T0 = env -> CP0_EntryLo0 ;
RETURN ();
}
ths
authored
17 years ago
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
void op_dmfc0_tcrestart ( void )
{
T0 = env -> PC [ env -> current_tc ];
RETURN ();
}
void op_dmfc0_tchalt ( void )
{
T0 = env -> CP0_TCHalt [ env -> current_tc ];
RETURN ();
}
void op_dmfc0_tccontext ( void )
{
T0 = env -> CP0_TCContext [ env -> current_tc ];
RETURN ();
}
void op_dmfc0_tcschedule ( void )
{
T0 = env -> CP0_TCSchedule [ env -> current_tc ];
RETURN ();
}
void op_dmfc0_tcschefback ( void )
{
T0 = env -> CP0_TCScheFBack [ env -> current_tc ];
RETURN ();
}
ths
authored
18 years ago
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
void op_dmfc0_entrylo1 ( void )
{
T0 = env -> CP0_EntryLo1 ;
RETURN ();
}
void op_dmfc0_context ( void )
{
T0 = env -> CP0_Context ;
RETURN ();
}
void op_dmfc0_badvaddr ( void )
{
T0 = env -> CP0_BadVAddr ;
RETURN ();
}
void op_dmfc0_entryhi ( void )
{
T0 = env -> CP0_EntryHi ;
RETURN ();
}
void op_dmfc0_epc ( void )
{
T0 = env -> CP0_EPC ;
RETURN ();
}
void op_dmfc0_lladdr ( void )
{
T0 = env -> CP0_LLAddr >> 4 ;
RETURN ();
}
ths
authored
18 years ago
2105
void op_dmfc0_watchlo ( void )
ths
authored
18 years ago
2106
{
ths
authored
18 years ago
2107
T0 = env -> CP0_WatchLo [ PARAM1 ];
ths
authored
18 years ago
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
RETURN ();
}
void op_dmfc0_xcontext ( void )
{
T0 = env -> CP0_XContext ;
RETURN ();
}
void op_dmfc0_depc ( void )
{
T0 = env -> CP0_DEPC ;
RETURN ();
}
void op_dmfc0_errorepc ( void )
{
T0 = env -> CP0_ErrorEPC ;
RETURN ();
}
ths
authored
17 years ago
2128
# endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
ths
authored
18 years ago
2129
ths
authored
17 years ago
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
/* MIPS MT functions */
void op_mftgpr ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> gpr [ PARAM1 ][ other_tc ];
RETURN ();
}
void op_mftlo ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> LO [ PARAM1 ][ other_tc ];
RETURN ();
}
void op_mfthi ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> HI [ PARAM1 ][ other_tc ];
RETURN ();
}
void op_mftacx ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> ACX [ PARAM1 ][ other_tc ];
RETURN ();
}
void op_mftdsp ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> DSPControl [ other_tc ];
RETURN ();
}
void op_mttgpr ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> gpr [ PARAM1 ][ other_tc ];
RETURN ();
}
void op_mttlo ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> LO [ PARAM1 ][ other_tc ];
RETURN ();
}
void op_mtthi ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> HI [ PARAM1 ][ other_tc ];
RETURN ();
}
void op_mttacx ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> ACX [ PARAM1 ][ other_tc ];
RETURN ();
}
void op_mttdsp ( void )
{
int other_tc = env -> CP0_VPEControl & ( 0xff << CP0VPECo_TargTC );
T0 = env -> DSPControl [ other_tc ];
RETURN ();
}
void op_dmt ( void )
{
// TODO
T0 = 0 ;
// rt = T0
RETURN ();
}
void op_emt ( void )
{
// TODO
T0 = 0 ;
// rt = T0
RETURN ();
}
void op_dvpe ( void )
{
// TODO
T0 = 0 ;
// rt = T0
RETURN ();
}
void op_evpe ( void )
{
// TODO
T0 = 0 ;
// rt = T0
RETURN ();
}
void op_fork ( void )
{
// T0 = rt , T1 = rs
T0 = 0 ;
// TODO : store to TC register
RETURN ();
}
void op_yield ( void )
{
if ( T0 < 0 ) {
/* No scheduling policy implemented. */
if ( T0 != - 2 ) {
if ( env -> CP0_VPEControl & ( 1 << CP0VPECo_YSI ) &&
env -> CP0_TCStatus [ env -> current_tc ] & ( 1 << CP0TCSt_DT )) {
env -> CP0_VPEControl &= ~ ( 0x7 << CP0VPECo_EXCPT );
env -> CP0_VPEControl |= 4 << CP0VPECo_EXCPT ;
CALL_FROM_TB1 ( do_raise_exception , EXCP_THREAD );
}
}
} else if ( T0 == 0 ) {
if ( 0 /* TODO: TC underflow */ ) {
env -> CP0_VPEControl &= ~ ( 0x7 << CP0VPECo_EXCPT );
CALL_FROM_TB1 ( do_raise_exception , EXCP_THREAD );
} else {
// TODO : Deallocate TC
}
} else if ( T0 > 0 ) {
/* Yield qualifier inputs not implemented. */
env -> CP0_VPEControl &= ~ ( 0x7 << CP0VPECo_EXCPT );
env -> CP0_VPEControl |= 2 << CP0VPECo_EXCPT ;
CALL_FROM_TB1 ( do_raise_exception , EXCP_THREAD );
}
T0 = env -> CP0_YQMask ;
RETURN ();
}
ths
authored
18 years ago
2281
/* CP1 functions */
2282
2283
2284
2285
2286
2287
# if 0
# define DEBUG_FPU_STATE () CALL_FROM_TB1 ( dump_fpu , env )
# else
# define DEBUG_FPU_STATE () do { } while ( 0 )
# endif
ths
authored
18 years ago
2288
2289
void op_cfc1 ( void )
{
ths
authored
17 years ago
2290
CALL_FROM_TB1 ( do_cfc1 , PARAM1 );
ths
authored
18 years ago
2291
2292
2293
2294
2295
2296
DEBUG_FPU_STATE ();
RETURN ();
}
void op_ctc1 ( void )
{
ths
authored
17 years ago
2297
CALL_FROM_TB1 ( do_ctc1 , PARAM1 );
2298
2299
2300
2301
2302
2303
DEBUG_FPU_STATE ();
RETURN ();
}
void op_mfc1 ( void )
{
ths
authored
17 years ago
2304
T0 = ( int32_t ) WT0 ;
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
DEBUG_FPU_STATE ();
RETURN ();
}
void op_mtc1 ( void )
{
WT0 = T0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
ths
authored
18 years ago
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
void op_dmfc1 ( void )
{
T0 = DT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
void op_dmtc1 ( void )
{
DT0 = T0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
void op_mfhc1 ( void )
{
ths
authored
17 years ago
2332
T0 = ( int32_t ) WTH0 ;
ths
authored
18 years ago
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
DEBUG_FPU_STATE ();
RETURN ();
}
void op_mthc1 ( void )
{
WTH0 = T0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
2344
2345
/* Float support .
Single precition routines have a "s" suffix , double precision a
ths
authored
18 years ago
2346
2347
"d" suffix , 32 bit integer "w" , 64 bit integer "l" , paired singe "ps" ,
paired single lowwer "pl" , paired single upper "pu" . */
2348
2349
2350
# define FLOAT_OP ( name , p ) void OPPROTO op_float_ ## name ## _ ## p ( void )
2351
2352
FLOAT_OP ( cvtd , s )
{
ths
authored
18 years ago
2353
CALL_FROM_TB0 ( do_float_cvtd_s );
2354
2355
2356
DEBUG_FPU_STATE ();
RETURN ();
}
2357
2358
FLOAT_OP ( cvtd , w )
{
ths
authored
18 years ago
2359
CALL_FROM_TB0 ( do_float_cvtd_w );
ths
authored
18 years ago
2360
2361
2362
2363
2364
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvtd , l )
{
ths
authored
18 years ago
2365
CALL_FROM_TB0 ( do_float_cvtd_l );
ths
authored
18 years ago
2366
2367
2368
2369
2370
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvtl , d )
{
ths
authored
18 years ago
2371
CALL_FROM_TB0 ( do_float_cvtl_d );
ths
authored
18 years ago
2372
2373
2374
2375
2376
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvtl , s )
{
ths
authored
18 years ago
2377
CALL_FROM_TB0 ( do_float_cvtl_s );
ths
authored
18 years ago
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvtps , s )
{
WT2 = WT0 ;
WTH2 = WT1 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvtps , pw )
{
ths
authored
18 years ago
2390
CALL_FROM_TB0 ( do_float_cvtps_pw );
ths
authored
18 years ago
2391
2392
2393
2394
2395
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvtpw , ps )
{
ths
authored
18 years ago
2396
CALL_FROM_TB0 ( do_float_cvtpw_ps );
2397
2398
2399
DEBUG_FPU_STATE ();
RETURN ();
}
2400
2401
FLOAT_OP ( cvts , d )
{
ths
authored
18 years ago
2402
CALL_FROM_TB0 ( do_float_cvts_d );
2403
2404
2405
DEBUG_FPU_STATE ();
RETURN ();
}
2406
2407
FLOAT_OP ( cvts , w )
{
ths
authored
18 years ago
2408
CALL_FROM_TB0 ( do_float_cvts_w );
ths
authored
18 years ago
2409
2410
2411
2412
2413
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvts , l )
{
ths
authored
18 years ago
2414
CALL_FROM_TB0 ( do_float_cvts_l );
ths
authored
18 years ago
2415
2416
2417
2418
2419
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvts , pl )
{
ths
authored
18 years ago
2420
CALL_FROM_TB0 ( do_float_cvts_pl );
ths
authored
18 years ago
2421
2422
2423
2424
2425
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvts , pu )
{
ths
authored
18 years ago
2426
CALL_FROM_TB0 ( do_float_cvts_pu );
2427
2428
2429
2430
2431
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvtw , s )
{
ths
authored
18 years ago
2432
CALL_FROM_TB0 ( do_float_cvtw_s );
2433
2434
2435
2436
2437
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( cvtw , d )
{
ths
authored
18 years ago
2438
CALL_FROM_TB0 ( do_float_cvtw_d );
ths
authored
18 years ago
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( pll , ps )
{
DT2 = (( uint64_t ) WT0 << 32 ) | WT1 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( plu , ps )
{
DT2 = (( uint64_t ) WT0 << 32 ) | WTH1 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( pul , ps )
{
DT2 = (( uint64_t ) WTH0 << 32 ) | WT1 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( puu , ps )
{
DT2 = (( uint64_t ) WTH0 << 32 ) | WTH1 ;
2464
2465
2466
2467
DEBUG_FPU_STATE ();
RETURN ();
}
ths
authored
18 years ago
2468
2469
2470
2471
2472
2473
# define FLOAT_ROUNDOP ( op , ttype , stype ) \
FLOAT_OP ( op ## ttype , stype ) \
{ \
CALL_FROM_TB0 ( do_float_ ## op ## ttype ## _ ## stype ); \
DEBUG_FPU_STATE (); \
RETURN (); \
2474
2475
}
ths
authored
18 years ago
2476
2477
2478
2479
FLOAT_ROUNDOP ( round , l , d )
FLOAT_ROUNDOP ( round , l , s )
FLOAT_ROUNDOP ( round , w , d )
FLOAT_ROUNDOP ( round , w , s )
2480
ths
authored
18 years ago
2481
2482
2483
2484
FLOAT_ROUNDOP ( trunc , l , d )
FLOAT_ROUNDOP ( trunc , l , s )
FLOAT_ROUNDOP ( trunc , w , d )
FLOAT_ROUNDOP ( trunc , w , s )
2485
ths
authored
18 years ago
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
FLOAT_ROUNDOP ( ceil , l , d )
FLOAT_ROUNDOP ( ceil , l , s )
FLOAT_ROUNDOP ( ceil , w , d )
FLOAT_ROUNDOP ( ceil , w , s )
FLOAT_ROUNDOP ( floor , l , d )
FLOAT_ROUNDOP ( floor , l , s )
FLOAT_ROUNDOP ( floor , w , d )
FLOAT_ROUNDOP ( floor , w , s )
# undef FLOAR_ROUNDOP
2496
ths
authored
18 years ago
2497
2498
FLOAT_OP ( movf , d )
{
ths
authored
17 years ago
2499
if ( ! ( env -> fpu -> fcr31 & PARAM1 ))
ths
authored
18 years ago
2500
2501
2502
2503
2504
2505
DT2 = DT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movf , s )
{
ths
authored
17 years ago
2506
if ( ! ( env -> fpu -> fcr31 & PARAM1 ))
ths
authored
18 years ago
2507
2508
2509
2510
2511
2512
WT2 = WT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movf , ps )
{
ths
authored
17 years ago
2513
if ( ! ( env -> fpu -> fcr31 & PARAM1 )) {
ths
authored
18 years ago
2514
2515
2516
2517
2518
2519
2520
2521
WT2 = WT0 ;
WTH2 = WTH0 ;
}
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movt , d )
{
ths
authored
17 years ago
2522
if ( env -> fpu -> fcr31 & PARAM1 )
ths
authored
18 years ago
2523
2524
2525
2526
2527
2528
DT2 = DT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movt , s )
{
ths
authored
17 years ago
2529
if ( env -> fpu -> fcr31 & PARAM1 )
ths
authored
18 years ago
2530
2531
2532
2533
2534
2535
WT2 = WT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movt , ps )
{
ths
authored
17 years ago
2536
if ( env -> fpu -> fcr31 & PARAM1 ) {
ths
authored
18 years ago
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
WT2 = WT0 ;
WTH2 = WTH0 ;
}
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movz , d )
{
if ( ! T0 )
DT2 = DT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movz , s )
{
if ( ! T0 )
WT2 = WT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movz , ps )
{
if ( ! T0 ) {
WT2 = WT0 ;
WTH2 = WTH0 ;
}
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movn , d )
{
if ( T0 )
DT2 = DT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movn , s )
{
if ( T0 )
WT2 = WT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( movn , ps )
{
if ( T0 ) {
WT2 = WT0 ;
WTH2 = WTH0 ;
}
DEBUG_FPU_STATE ();
RETURN ();
}
ths
authored
18 years ago
2590
2591
/* operations calling helpers, for s, d and ps */
# define FLOAT_HOP ( name ) \
2592
2593
FLOAT_OP ( name , d ) \
{ \
ths
authored
18 years ago
2594
CALL_FROM_TB0 ( do_float_ ## name ## _d ); \
2595
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2596
RETURN (); \
2597
2598
2599
} \
FLOAT_OP ( name , s ) \
{ \
ths
authored
18 years ago
2600
CALL_FROM_TB0 ( do_float_ ## name ## _s ); \
ths
authored
18 years ago
2601
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2602
RETURN (); \
ths
authored
18 years ago
2603
2604
2605
} \
FLOAT_OP ( name , ps ) \
{ \
ths
authored
18 years ago
2606
CALL_FROM_TB0 ( do_float_ ## name ## _ps ); \
2607
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2608
RETURN (); \
2609
}
ths
authored
18 years ago
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
FLOAT_HOP ( add )
FLOAT_HOP ( sub )
FLOAT_HOP ( mul )
FLOAT_HOP ( div )
FLOAT_HOP ( recip2 )
FLOAT_HOP ( rsqrt2 )
FLOAT_HOP ( rsqrt1 )
FLOAT_HOP ( recip1 )
# undef FLOAT_HOP
/* operations calling helpers, for s and d */
# define FLOAT_HOP ( name ) \
FLOAT_OP ( name , d ) \
{ \
CALL_FROM_TB0 ( do_float_ ## name ## _d ); \
DEBUG_FPU_STATE (); \
RETURN (); \
} \
FLOAT_OP ( name , s ) \
{ \
CALL_FROM_TB0 ( do_float_ ## name ## _s ); \
DEBUG_FPU_STATE (); \
RETURN (); \
}
FLOAT_HOP ( rsqrt )
FLOAT_HOP ( recip )
# undef FLOAT_HOP
2637
ths
authored
18 years ago
2638
2639
2640
2641
2642
2643
2644
/* operations calling helpers, for ps */
# define FLOAT_HOP ( name ) \
FLOAT_OP ( name , ps ) \
{ \
CALL_FROM_TB0 ( do_float_ ## name ## _ps ); \
DEBUG_FPU_STATE (); \
RETURN (); \
ths
authored
18 years ago
2645
}
ths
authored
18 years ago
2646
2647
2648
FLOAT_HOP ( addr )
FLOAT_HOP ( mulr )
# undef FLOAT_HOP
ths
authored
18 years ago
2649
ths
authored
18 years ago
2650
2651
2652
2653
/* ternary operations */
# define FLOAT_TERNOP ( name1 , name2 ) \
FLOAT_OP ( name1 ## name2 , d ) \
{ \
ths
authored
17 years ago
2654
2655
FDT0 = float64_ ## name1 ( FDT0 , FDT1 , & env -> fpu -> fp_status ); \
FDT2 = float64_ ## name2 ( FDT0 , FDT2 , & env -> fpu -> fp_status ); \
ths
authored
18 years ago
2656
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2657
RETURN (); \
ths
authored
18 years ago
2658
2659
2660
} \
FLOAT_OP ( name1 ## name2 , s ) \
{ \
ths
authored
17 years ago
2661
2662
FST0 = float32_ ## name1 ( FST0 , FST1 , & env -> fpu -> fp_status ); \
FST2 = float32_ ## name2 ( FST0 , FST2 , & env -> fpu -> fp_status ); \
ths
authored
18 years ago
2663
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2664
RETURN (); \
ths
authored
18 years ago
2665
2666
2667
} \
FLOAT_OP ( name1 ## name2 , ps ) \
{ \
ths
authored
17 years ago
2668
2669
2670
2671
FST0 = float32_ ## name1 ( FST0 , FST1 , & env -> fpu -> fp_status ); \
FSTH0 = float32_ ## name1 ( FSTH0 , FSTH1 , & env -> fpu -> fp_status ); \
FST2 = float32_ ## name2 ( FST0 , FST2 , & env -> fpu -> fp_status ); \
FSTH2 = float32_ ## name2 ( FSTH0 , FSTH2 , & env -> fpu -> fp_status ); \
ths
authored
18 years ago
2672
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2673
RETURN (); \
ths
authored
18 years ago
2674
2675
2676
2677
2678
}
FLOAT_TERNOP ( mul , add )
FLOAT_TERNOP ( mul , sub )
# undef FLOAT_TERNOP
ths
authored
18 years ago
2679
2680
2681
2682
/* negated ternary operations */
# define FLOAT_NTERNOP ( name1 , name2 ) \
FLOAT_OP ( n ## name1 ## name2 , d ) \
{ \
ths
authored
17 years ago
2683
2684
FDT0 = float64_ ## name1 ( FDT0 , FDT1 , & env -> fpu -> fp_status ); \
FDT2 = float64_ ## name2 ( FDT0 , FDT2 , & env -> fpu -> fp_status ); \
ths
authored
18 years ago
2685
2686
2687
2688
2689
2690
FDT2 ^= 1ULL << 63 ; \
DEBUG_FPU_STATE (); \
RETURN (); \
} \
FLOAT_OP ( n ## name1 ## name2 , s ) \
{ \
ths
authored
17 years ago
2691
2692
FST0 = float32_ ## name1 ( FST0 , FST1 , & env -> fpu -> fp_status ); \
FST2 = float32_ ## name2 ( FST0 , FST2 , & env -> fpu -> fp_status ); \
ths
authored
18 years ago
2693
2694
2695
2696
2697
2698
FST2 ^= 1 << 31 ; \
DEBUG_FPU_STATE (); \
RETURN (); \
} \
FLOAT_OP ( n ## name1 ## name2 , ps ) \
{ \
ths
authored
17 years ago
2699
2700
2701
2702
FST0 = float32_ ## name1 ( FST0 , FST1 , & env -> fpu -> fp_status ); \
FSTH0 = float32_ ## name1 ( FSTH0 , FSTH1 , & env -> fpu -> fp_status ); \
FST2 = float32_ ## name2 ( FST0 , FST2 , & env -> fpu -> fp_status ); \
FSTH2 = float32_ ## name2 ( FSTH0 , FSTH2 , & env -> fpu -> fp_status ); \
ths
authored
18 years ago
2703
2704
2705
2706
2707
2708
2709
2710
2711
FST2 ^= 1 << 31 ; \
FSTH2 ^= 1 << 31 ; \
DEBUG_FPU_STATE (); \
RETURN (); \
}
FLOAT_NTERNOP ( mul , add )
FLOAT_NTERNOP ( mul , sub )
# undef FLOAT_NTERNOP
2712
2713
2714
2715
/* unary operations, modifying fp status */
# define FLOAT_UNOP ( name ) \
FLOAT_OP ( name , d ) \
{ \
ths
authored
17 years ago
2716
FDT2 = float64_ ## name ( FDT0 , & env -> fpu -> fp_status ); \
2717
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2718
RETURN (); \
2719
2720
2721
} \
FLOAT_OP ( name , s ) \
{ \
ths
authored
17 years ago
2722
FST2 = float32_ ## name ( FST0 , & env -> fpu -> fp_status ); \
2723
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2724
RETURN (); \
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
}
FLOAT_UNOP ( sqrt )
# undef FLOAT_UNOP
/* unary operations, not modifying fp status */
# define FLOAT_UNOP ( name ) \
FLOAT_OP ( name , d ) \
{ \
FDT2 = float64_ ## name ( FDT0 ); \
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2735
RETURN (); \
2736
2737
2738
2739
2740
} \
FLOAT_OP ( name , s ) \
{ \
FST2 = float32_ ## name ( FST0 ); \
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2741
RETURN (); \
ths
authored
18 years ago
2742
2743
2744
2745
2746
2747
} \
FLOAT_OP ( name , ps ) \
{ \
FST2 = float32_ ## name ( FST0 ); \
FSTH2 = float32_ ## name ( FSTH0 ); \
DEBUG_FPU_STATE (); \
ths
authored
18 years ago
2748
RETURN (); \
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
}
FLOAT_UNOP ( abs )
FLOAT_UNOP ( chs )
# undef FLOAT_UNOP
FLOAT_OP ( mov , d )
{
FDT2 = FDT0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( mov , s )
{
FST2 = FST0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
ths
authored
18 years ago
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
FLOAT_OP ( mov , ps )
{
FST2 = FST0 ;
FSTH2 = FSTH0 ;
DEBUG_FPU_STATE ();
RETURN ();
}
FLOAT_OP ( alnv , ps )
{
switch ( T0 & 0x7 ) {
case 0 :
FST2 = FST0 ;
FSTH2 = FSTH0 ;
break ;
case 4 :
# ifdef TARGET_WORDS_BIGENDIAN
FSTH2 = FST0 ;
FST2 = FSTH1 ;
# else
FSTH2 = FST1 ;
FST2 = FSTH0 ;
# endif
break ;
default : /* unpredictable */
break ;
}
DEBUG_FPU_STATE ();
RETURN ();
}
2795
2796
2797
# ifdef CONFIG_SOFTFLOAT
# define clear_invalid () do { \
ths
authored
17 years ago
2798
int flags = get_float_exception_flags ( & env -> fpu -> fp_status ); \
2799
flags &= ~ float_flag_invalid ; \
ths
authored
17 years ago
2800
set_float_exception_flags ( flags , & env -> fpu -> fp_status ); \
2801
2802
2803
2804
2805
2806
2807
} while ( 0 )
# else
# define clear_invalid () do { } while ( 0 )
# endif
extern void dump_fpu_s ( CPUState * env );
ths
authored
18 years ago
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
# define CMP_OP ( fmt , op ) \
void OPPROTO op_cmp ## _ ## fmt ## _ ## op ( void ) \
{ \
CALL_FROM_TB1 ( do_cmp ## _ ## fmt ## _ ## op , PARAM1 ); \
DEBUG_FPU_STATE (); \
RETURN (); \
} \
void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op ( void ) \
{ \
CALL_FROM_TB1 ( do_cmpabs ## _ ## fmt ## _ ## op , PARAM1 ); \
DEBUG_FPU_STATE (); \
RETURN (); \
}
# define CMP_OPS ( op ) \
CMP_OP ( d , op ) \
CMP_OP ( s , op ) \
CMP_OP ( ps , op )
CMP_OPS ( f )
CMP_OPS ( un )
CMP_OPS ( eq )
CMP_OPS ( ueq )
CMP_OPS ( olt )
CMP_OPS ( ult )
CMP_OPS ( ole )
CMP_OPS ( ule )
CMP_OPS ( sf )
CMP_OPS ( ngle )
CMP_OPS ( seq )
CMP_OPS ( ngl )
CMP_OPS ( lt )
CMP_OPS ( nge )
CMP_OPS ( le )
CMP_OPS ( ngt )
# undef CMP_OPS
# undef CMP_OP
2844
2845
2846
void op_bc1f ( void )
{
ths
authored
17 years ago
2847
T0 = !! ( ~ GET_FP_COND ( env -> fpu ) & ( 0x1 << PARAM1 ));
ths
authored
18 years ago
2848
2849
2850
DEBUG_FPU_STATE ();
RETURN ();
}
ths
authored
18 years ago
2851
void op_bc1any2f ( void )
ths
authored
18 years ago
2852
{
ths
authored
17 years ago
2853
T0 = !! ( ~ GET_FP_COND ( env -> fpu ) & ( 0x3 << PARAM1 ));
ths
authored
18 years ago
2854
2855
2856
DEBUG_FPU_STATE ();
RETURN ();
}
ths
authored
18 years ago
2857
void op_bc1any4f ( void )
ths
authored
18 years ago
2858
{
ths
authored
17 years ago
2859
T0 = !! ( ~ GET_FP_COND ( env -> fpu ) & ( 0xf << PARAM1 ));
2860
2861
2862
2863
2864
2865
DEBUG_FPU_STATE ();
RETURN ();
}
void op_bc1t ( void )
{
ths
authored
17 years ago
2866
T0 = !! ( GET_FP_COND ( env -> fpu ) & ( 0x1 << PARAM1 ));
ths
authored
18 years ago
2867
2868
2869
DEBUG_FPU_STATE ();
RETURN ();
}
ths
authored
18 years ago
2870
void op_bc1any2t ( void )
ths
authored
18 years ago
2871
{
ths
authored
17 years ago
2872
T0 = !! ( GET_FP_COND ( env -> fpu ) & ( 0x3 << PARAM1 ));
ths
authored
18 years ago
2873
2874
2875
DEBUG_FPU_STATE ();
RETURN ();
}
ths
authored
18 years ago
2876
void op_bc1any4t ( void )
ths
authored
18 years ago
2877
{
ths
authored
17 years ago
2878
T0 = !! ( GET_FP_COND ( env -> fpu ) & ( 0xf << PARAM1 ));
2879
2880
2881
2882
DEBUG_FPU_STATE ();
RETURN ();
}
2883
2884
void op_tlbwi ( void )
{
ths
authored
17 years ago
2885
CALL_FROM_TB0 ( env -> tlb -> do_tlbwi );
2886
2887
2888
2889
2890
RETURN ();
}
void op_tlbwr ( void )
{
ths
authored
17 years ago
2891
CALL_FROM_TB0 ( env -> tlb -> do_tlbwr );
2892
2893
2894
2895
2896
RETURN ();
}
void op_tlbp ( void )
{
ths
authored
17 years ago
2897
CALL_FROM_TB0 ( env -> tlb -> do_tlbp );
2898
2899
2900
2901
2902
RETURN ();
}
void op_tlbr ( void )
{
ths
authored
17 years ago
2903
CALL_FROM_TB0 ( env -> tlb -> do_tlbr );
2904
2905
2906
2907
RETURN ();
}
/* Specials */
ths
authored
18 years ago
2908
2909
2910
# if defined ( CONFIG_USER_ONLY )
void op_tls_value ( void )
{
ths
authored
18 years ago
2911
T0 = env -> tls_value ;
ths
authored
18 years ago
2912
2913
2914
}
# endif
2915
2916
2917
void op_pmon ( void )
{
CALL_FROM_TB1 ( do_pmon , PARAM1 );
ths
authored
18 years ago
2918
2919
2920
2921
2922
2923
RETURN ();
}
void op_di ( void )
{
T0 = env -> CP0_Status ;
ths
authored
18 years ago
2924
2925
env -> CP0_Status = T0 & ~ ( 1 << CP0St_IE );
CALL_FROM_TB1 ( cpu_mips_update_irq , env );
ths
authored
18 years ago
2926
2927
2928
2929
2930
2931
RETURN ();
}
void op_ei ( void )
{
T0 = env -> CP0_Status ;
ths
authored
18 years ago
2932
2933
env -> CP0_Status = T0 | ( 1 << CP0St_IE );
CALL_FROM_TB1 ( cpu_mips_update_irq , env );
ths
authored
18 years ago
2934
RETURN ();
2935
2936
2937
2938
2939
}
void op_trap ( void )
{
if ( T0 ) {
ths
authored
18 years ago
2940
CALL_FROM_TB1 ( do_raise_exception , EXCP_TRAP );
2941
2942
2943
2944
}
RETURN ();
}
2945
2946
void op_debug ( void )
{
ths
authored
18 years ago
2947
2948
CALL_FROM_TB1 ( do_raise_exception , EXCP_DEBUG );
RETURN ();
2949
2950
}
2951
2952
2953
void op_set_lladdr ( void )
{
env -> CP0_LLAddr = T2 ;
ths
authored
18 years ago
2954
RETURN ();
2955
2956
}
ths
authored
18 years ago
2957
2958
void debug_pre_eret ( void );
void debug_post_eret ( void );
2959
2960
void op_eret ( void )
{
ths
authored
18 years ago
2961
2962
if ( loglevel & CPU_LOG_EXEC )
CALL_FROM_TB0 ( debug_pre_eret );
ths
authored
18 years ago
2963
if ( env -> CP0_Status & ( 1 << CP0St_ERL )) {
ths
authored
17 years ago
2964
env -> PC [ env -> current_tc ] = env -> CP0_ErrorEPC ;
ths
authored
18 years ago
2965
env -> CP0_Status &= ~ ( 1 << CP0St_ERL );
2966
} else {
ths
authored
17 years ago
2967
env -> PC [ env -> current_tc ] = env -> CP0_EPC ;
ths
authored
18 years ago
2968
env -> CP0_Status &= ~ ( 1 << CP0St_EXL );
2969
}
ths
authored
17 years ago
2970
CALL_FROM_TB1 ( compute_hflags , env );
ths
authored
18 years ago
2971
2972
if ( loglevel & CPU_LOG_EXEC )
CALL_FROM_TB0 ( debug_post_eret );
2973
env -> CP0_LLAddr = 1 ;
ths
authored
18 years ago
2974
RETURN ();
2975
2976
2977
2978
}
void op_deret ( void )
{
ths
authored
18 years ago
2979
2980
if ( loglevel & CPU_LOG_EXEC )
CALL_FROM_TB0 ( debug_pre_eret );
ths
authored
17 years ago
2981
env -> PC [ env -> current_tc ] = env -> CP0_DEPC ;
ths
authored
17 years ago
2982
2983
env -> hflags &= MIPS_HFLAG_DM ;
CALL_FROM_TB1 ( compute_hflags , env );
ths
authored
18 years ago
2984
2985
if ( loglevel & CPU_LOG_EXEC )
CALL_FROM_TB0 ( debug_post_eret );
ths
authored
18 years ago
2986
env -> CP0_LLAddr = 1 ;
ths
authored
18 years ago
2987
2988
2989
2990
2991
RETURN ();
}
void op_rdhwr_cpunum ( void )
{
ths
authored
17 years ago
2992
2993
if (( env -> hflags & MIPS_HFLAG_CP0 ) ||
( env -> CP0_HWREna & ( 1 << 0 )))
ths
authored
18 years ago
2994
T0 = env -> CP0_EBase & 0x3ff ;
ths
authored
18 years ago
2995
else
ths
authored
18 years ago
2996
CALL_FROM_TB1 ( do_raise_exception , EXCP_RI );
ths
authored
18 years ago
2997
2998
2999
3000
3001
RETURN ();
}
void op_rdhwr_synci_step ( void )
{
ths
authored
17 years ago
3002
3003
if (( env -> hflags & MIPS_HFLAG_CP0 ) ||
( env -> CP0_HWREna & ( 1 << 1 )))
ths
authored
18 years ago
3004
T0 = env -> SYNCI_Step ;
ths
authored
18 years ago
3005
else
ths
authored
18 years ago
3006
CALL_FROM_TB1 ( do_raise_exception , EXCP_RI );
ths
authored
18 years ago
3007
3008
3009
3010
3011
RETURN ();
}
void op_rdhwr_cc ( void )
{
ths
authored
17 years ago
3012
3013
if (( env -> hflags & MIPS_HFLAG_CP0 ) ||
( env -> CP0_HWREna & ( 1 << 2 )))
ths
authored
18 years ago
3014
T0 = env -> CP0_Count ;
ths
authored
18 years ago
3015
else
ths
authored
18 years ago
3016
CALL_FROM_TB1 ( do_raise_exception , EXCP_RI );
ths
authored
18 years ago
3017
3018
3019
3020
3021
RETURN ();
}
void op_rdhwr_ccres ( void )
{
ths
authored
17 years ago
3022
3023
if (( env -> hflags & MIPS_HFLAG_CP0 ) ||
( env -> CP0_HWREna & ( 1 << 3 )))
ths
authored
18 years ago
3024
T0 = env -> CCRes ;
ths
authored
18 years ago
3025
else
ths
authored
18 years ago
3026
3027
3028
3029
CALL_FROM_TB1 ( do_raise_exception , EXCP_RI );
RETURN ();
}
3030
3031
3032
3033
3034
3035
3036
3037
void op_save_state ( void )
{
env -> hflags = PARAM1 ;
RETURN ();
}
void op_save_pc ( void )
{
ths
authored
17 years ago
3038
env -> PC [ env -> current_tc ] = PARAM1 ;
3039
3040
3041
RETURN ();
}
ths
authored
17 years ago
3042
# if defined ( TARGET_MIPSN32 ) || defined ( TARGET_MIPS64 )
ths
authored
18 years ago
3043
3044
void op_save_pc64 ( void )
{
ths
authored
17 years ago
3045
env -> PC [ env -> current_tc ] = (( uint64_t ) PARAM1 << 32 ) | ( uint32_t ) PARAM2 ;
ths
authored
18 years ago
3046
3047
3048
3049
RETURN ();
}
# endif
ths
authored
18 years ago
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
void op_interrupt_restart ( void )
{
if ( ! ( env -> CP0_Status & ( 1 << CP0St_EXL )) &&
! ( env -> CP0_Status & ( 1 << CP0St_ERL )) &&
! ( env -> hflags & MIPS_HFLAG_DM ) &&
( env -> CP0_Status & ( 1 << CP0St_IE )) &&
( env -> CP0_Status & env -> CP0_Cause & CP0Ca_IP_mask )) {
env -> CP0_Cause &= ~ ( 0x1f << CP0Ca_EC );
CALL_FROM_TB1 ( do_raise_exception , EXCP_EXT_INTERRUPT );
}
RETURN ();
}
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
void op_raise_exception ( void )
{
CALL_FROM_TB1 ( do_raise_exception , PARAM1 );
RETURN ();
}
void op_raise_exception_err ( void )
{
CALL_FROM_TB2 ( do_raise_exception_err , PARAM1 , PARAM2 );
RETURN ();
}
void op_exit_tb ( void )
{
EXIT_TB ();
ths
authored
18 years ago
3078
RETURN ();
3079
3080
}
3081
3082
3083
3084
void op_wait ( void )
{
env -> halted = 1 ;
CALL_FROM_TB1 ( do_raise_exception , EXCP_HLT );
ths
authored
18 years ago
3085
3086
3087
3088
3089
3090
3091
3092
3093
RETURN ();
}
/* Bitfield operations. */
void op_ext ( void )
{
unsigned int pos = PARAM1 ;
unsigned int size = PARAM2 ;
ths
authored
18 years ago
3094
T0 = (( uint32_t ) T1 >> pos ) & (( size < 32 ) ? (( 1 << size ) - 1 ) : ~ 0 );
ths
authored
18 years ago
3095
3096
3097
3098
3099
3100
3101
RETURN ();
}
void op_ins ( void )
{
unsigned int pos = PARAM1 ;
unsigned int size = PARAM2 ;
ths
authored
18 years ago
3102
target_ulong mask = (( size < 32 ) ? (( 1 << size ) - 1 ) : ~ 0 ) << pos ;
ths
authored
18 years ago
3103
ths
authored
18 years ago
3104
T0 = ( T0 & ~ mask ) | ((( uint32_t ) T1 << pos ) & mask );
ths
authored
18 years ago
3105
3106
3107
3108
3109
3110
3111
3112
3113
RETURN ();
}
void op_wsbh ( void )
{
T0 = (( T1 << 8 ) & ~ 0x00FF00FF ) | (( T1 >> 8 ) & 0x00FF00FF );
RETURN ();
}
ths
authored
17 years ago
3114
# if defined ( TARGET_MIPSN32 ) || defined ( TARGET_MIPS64 )
ths
authored
18 years ago
3115
3116
3117
3118
3119
void op_dext ( void )
{
unsigned int pos = PARAM1 ;
unsigned int size = PARAM2 ;
ths
authored
18 years ago
3120
T0 = ( T1 >> pos ) & (( size < 32 ) ? (( 1 << size ) - 1 ) : ~ 0 );
ths
authored
18 years ago
3121
3122
3123
3124
3125
3126
3127
RETURN ();
}
void op_dins ( void )
{
unsigned int pos = PARAM1 ;
unsigned int size = PARAM2 ;
ths
authored
18 years ago
3128
target_ulong mask = (( size < 32 ) ? (( 1 << size ) - 1 ) : ~ 0 ) << pos ;
ths
authored
18 years ago
3129
ths
authored
18 years ago
3130
T0 = ( T0 & ~ mask ) | (( T1 << pos ) & mask );
ths
authored
18 years ago
3131
3132
3133
RETURN ();
}
ths
authored
18 years ago
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
void op_dsbh ( void )
{
T0 = (( T1 << 8 ) & ~ 0x00FF00FF00FF00FFULL ) | (( T1 >> 8 ) & 0x00FF00FF00FF00FFULL );
RETURN ();
}
void op_dshd ( void )
{
T0 = (( T1 << 16 ) & ~ 0x0000FFFF0000FFFFULL ) | (( T1 >> 16 ) & 0x0000FFFF0000FFFFULL );
RETURN ();
}
ths
authored
18 years ago
3145
# endif
ths
authored
18 years ago
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
void op_seb ( void )
{
T0 = (( T1 & 0xFF ) ^ 0x80 ) - 0x80 ;
RETURN ();
}
void op_seh ( void )
{
T0 = (( T1 & 0xFFFF ) ^ 0x8000 ) - 0x8000 ;
RETURN ();
3157
}