gwj / at91sam9263 · Commits

Commit 9c2149c8e06cf6fbf1bd5096a50486abc3b71f17

Authored by ths
1 parent 17c275d9

Implementing dmfc/dmtc. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2348 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 1434 additions and 86 deletions
target-mips/cpu.h
  View file @9c2149c
... ... @@ -44,7 +44,7 @@ union fpr_t {
44 44 typedef struct tlb_t tlb_t;
45 45 struct tlb_t {
46 46 target_ulong VPN;
47   - uint_fast32_t PageMask;
  47 + uint32_t PageMask;
48 48 uint_fast8_t ASID;
49 49 uint_fast16_t G:1;
50 50 uint_fast16_t C0:3;
... ... @@ -110,20 +110,20 @@ struct CPUMIPSState {
110 110 tlb_t tlb[MIPS_TLB_MAX];
111 111 uint32_t tlb_in_use;
112 112 #endif
113   - uint32_t CP0_index;
114   - uint32_t CP0_random;
115   - uint64_t CP0_EntryLo0;
116   - uint64_t CP0_EntryLo1;
117   - uint64_t CP0_Context;
118   - uint32_t CP0_PageMask;
119   - uint32_t CP0_PageGrain;
120   - uint32_t CP0_Wired;
121   - uint32_t CP0_HWREna;
  113 + int32_t CP0_Index;
  114 + int32_t CP0_Random;
  115 + target_ulong CP0_EntryLo0;
  116 + target_ulong CP0_EntryLo1;
  117 + target_ulong CP0_Context;
  118 + int32_t CP0_PageMask;
  119 + int32_t CP0_PageGrain;
  120 + int32_t CP0_Wired;
  121 + int32_t CP0_HWREna;
122 122 target_ulong CP0_BadVAddr;
123   - uint32_t CP0_Count;
124   - uint64_t CP0_EntryHi;
125   - uint32_t CP0_Compare;
126   - uint32_t CP0_Status;
  123 + int32_t CP0_Count;
  124 + target_ulong CP0_EntryHi;
  125 + int32_t CP0_Compare;
  126 + int32_t CP0_Status;
127 127 #define CP0St_CU3 31
128 128 #define CP0St_CU2 30
129 129 #define CP0St_CU1 29
... ... @@ -146,9 +146,10 @@ struct CPUMIPSState {
146 146 #define CP0St_ERL 2
147 147 #define CP0St_EXL 1
148 148 #define CP0St_IE 0
149   - uint32_t CP0_IntCtl;
150   - uint32_t CP0_SRSCtl;
151   - uint32_t CP0_Cause;
  149 + int32_t CP0_IntCtl;
  150 + int32_t CP0_SRSCtl;
  151 + int32_t CP0_SRSMap;
  152 + int32_t CP0_Cause;
152 153 #define CP0Ca_BD 31
153 154 #define CP0Ca_TI 30
154 155 #define CP0Ca_CE 28
... ... @@ -159,9 +160,9 @@ struct CPUMIPSState {
159 160 #define CP0Ca_IP 8
160 161 #define CP0Ca_EC 2
161 162 target_ulong CP0_EPC;
162   - uint32_t CP0_PRid;
  163 + int32_t CP0_PRid;
163 164 target_ulong CP0_EBase;
164   - uint32_t CP0_Config0;
  165 + int32_t CP0_Config0;
165 166 #define CP0C0_M 31
166 167 #define CP0C0_K23 28
167 168 #define CP0C0_KU 25
... ... @@ -174,7 +175,7 @@ struct CPUMIPSState {
174 175 #define CP0C0_MT 7
175 176 #define CP0C0_VI 3
176 177 #define CP0C0_K0 0
177   - uint32_t CP0_Config1;
  178 + int32_t CP0_Config1;
178 179 #define CP0C1_M 31
179 180 #define CP0C1_MMU 25
180 181 #define CP0C1_IS 22
... ... @@ -190,7 +191,7 @@ struct CPUMIPSState {
190 191 #define CP0C1_CA 2
191 192 #define CP0C1_EP 1
192 193 #define CP0C1_FP 0
193   - uint32_t CP0_Config2;
  194 + int32_t CP0_Config2;
194 195 #define CP0C2_M 31
195 196 #define CP0C2_TU 28
196 197 #define CP0C2_TS 24
... ... @@ -200,7 +201,7 @@ struct CPUMIPSState {
200 201 #define CP0C2_SS 8
201 202 #define CP0C2_SL 4
202 203 #define CP0C2_SA 0
203   - uint32_t CP0_Config3;
  204 + int32_t CP0_Config3;
204 205 #define CP0C3_M 31
205 206 #define CP0C3_DSPP 10
206 207 #define CP0C3_LPA 7
... ... @@ -211,11 +212,11 @@ struct CPUMIPSState {
211 212 #define CP0C3_SM 1
212 213 #define CP0C3_TL 0
213 214 target_ulong CP0_LLAddr;
214   - uint32_t CP0_WatchLo;
215   - uint32_t CP0_WatchHi;
216   - uint32_t CP0_XContext;
217   - uint32_t CP0_Framemask;
218   - uint32_t CP0_Debug;
  215 + target_ulong CP0_WatchLo;
  216 + int32_t CP0_WatchHi;
  217 + target_ulong CP0_XContext;
  218 + int32_t CP0_Framemask;
  219 + int32_t CP0_Debug;
219 220 #define CPDB_DBD 31
220 221 #define CP0DB_DM 30
221 222 #define CP0DB_LSNM 28
... ... @@ -235,13 +236,13 @@ struct CPUMIPSState {
235 236 #define CP0DB_DBp 1
236 237 #define CP0DB_DSS 0
237 238 target_ulong CP0_DEPC;
238   - uint32_t CP0_Performance0;
239   - uint32_t CP0_TagLo;
240   - uint32_t CP0_DataLo;
241   - uint32_t CP0_TagHi;
242   - uint32_t CP0_DataHi;
  239 + int32_t CP0_Performance0;
  240 + int32_t CP0_TagLo;
  241 + int32_t CP0_DataLo;
  242 + int32_t CP0_TagHi;
  243 + int32_t CP0_DataHi;
243 244 target_ulong CP0_ErrorEPC;
244   - uint32_t CP0_DESAVE;
  245 + int32_t CP0_DESAVE;
245 246 /* Qemu */
246 247 int interrupt_request;
247 248 jmp_buf jmp_env;
... ...
target-mips/op.c
  View file @9c2149c
... ... @@ -1032,7 +1032,7 @@ void op_jnz_T2 (void)
1032 1032 /* CP0 functions */
1033 1033 void op_mfc0_index (void)
1034 1034 {
1035   - T0 = (int32_t)(env->CP0_index);
  1035 + T0 = env->CP0_Index;
1036 1036 RETURN();
1037 1037 }
1038 1038  
... ... @@ -1044,49 +1044,49 @@ void op_mfc0_random (void)
1044 1044  
1045 1045 void op_mfc0_entrylo0 (void)
1046 1046 {
1047   - T0 = env->CP0_EntryLo0;
  1047 + T0 = (int32_t)env->CP0_EntryLo0;
1048 1048 RETURN();
1049 1049 }
1050 1050  
1051 1051 void op_mfc0_entrylo1 (void)
1052 1052 {
1053   - T0 = env->CP0_EntryLo1;
  1053 + T0 = (int32_t)env->CP0_EntryLo1;
1054 1054 RETURN();
1055 1055 }
1056 1056  
1057 1057 void op_mfc0_context (void)
1058 1058 {
1059   - T0 = env->CP0_Context;
  1059 + T0 = (int32_t)env->CP0_Context;
1060 1060 RETURN();
1061 1061 }
1062 1062  
1063 1063 void op_mfc0_pagemask (void)
1064 1064 {
1065   - T0 = (int32_t)env->CP0_PageMask;
  1065 + T0 = env->CP0_PageMask;
1066 1066 RETURN();
1067 1067 }
1068 1068  
1069 1069 void op_mfc0_pagegrain (void)
1070 1070 {
1071   - T0 = (int32_t)env->CP0_PageGrain;
  1071 + T0 = env->CP0_PageGrain;
1072 1072 RETURN();
1073 1073 }
1074 1074  
1075 1075 void op_mfc0_wired (void)
1076 1076 {
1077   - T0 = (int32_t)env->CP0_Wired;
  1077 + T0 = env->CP0_Wired;
1078 1078 RETURN();
1079 1079 }
1080 1080  
1081 1081 void op_mfc0_hwrena (void)
1082 1082 {
1083   - T0 = (int32_t)env->CP0_HWREna;
  1083 + T0 = env->CP0_HWREna;
1084 1084 RETURN();
1085 1085 }
1086 1086  
1087 1087 void op_mfc0_badvaddr (void)
1088 1088 {
1089   - T0 = env->CP0_BadVAddr;
  1089 + T0 = (int32_t)env->CP0_BadVAddr;
1090 1090 RETURN();
1091 1091 }
1092 1092  
... ... @@ -1098,19 +1098,19 @@ void op_mfc0_count (void)
1098 1098  
1099 1099 void op_mfc0_entryhi (void)
1100 1100 {
1101   - T0 = env->CP0_EntryHi;
  1101 + T0 = (int32_t)env->CP0_EntryHi;
1102 1102 RETURN();
1103 1103 }
1104 1104  
1105 1105 void op_mfc0_compare (void)
1106 1106 {
1107   - T0 = (int32_t)env->CP0_Compare;
  1107 + T0 = env->CP0_Compare;
1108 1108 RETURN();
1109 1109 }
1110 1110  
1111 1111 void op_mfc0_status (void)
1112 1112 {
1113   - T0 = (int32_t)env->CP0_Status;
  1113 + T0 = env->CP0_Status;
1114 1114 if (env->hflags & MIPS_HFLAG_UM)
1115 1115 T0 |= (1 << CP0St_UM);
1116 1116 if (env->hflags & MIPS_HFLAG_ERL)
... ... @@ -1122,67 +1122,73 @@ void op_mfc0_status (void)
1122 1122  
1123 1123 void op_mfc0_intctl (void)
1124 1124 {
1125   - T0 = (int32_t)env->CP0_IntCtl;
  1125 + T0 = env->CP0_IntCtl;
1126 1126 RETURN();
1127 1127 }
1128 1128  
1129 1129 void op_mfc0_srsctl (void)
1130 1130 {
1131   - T0 = (int32_t)env->CP0_SRSCtl;
  1131 + T0 = env->CP0_SRSCtl;
  1132 + RETURN();
  1133 +}
  1134 +
  1135 +void op_mfc0_srsmap (void)
  1136 +{
  1137 + T0 = env->CP0_SRSMap;
1132 1138 RETURN();
1133 1139 }
1134 1140  
1135 1141 void op_mfc0_cause (void)
1136 1142 {
1137   - T0 = (int32_t)env->CP0_Cause;
  1143 + T0 = env->CP0_Cause;
1138 1144 RETURN();
1139 1145 }
1140 1146  
1141 1147 void op_mfc0_epc (void)
1142 1148 {
1143   - T0 = env->CP0_EPC;
  1149 + T0 = (int32_t)env->CP0_EPC;
1144 1150 RETURN();
1145 1151 }
1146 1152  
1147 1153 void op_mfc0_prid (void)
1148 1154 {
1149   - T0 = (int32_t)env->CP0_PRid;
  1155 + T0 = env->CP0_PRid;
1150 1156 RETURN();
1151 1157 }
1152 1158  
1153 1159 void op_mfc0_ebase (void)
1154 1160 {
1155   - T0 = env->CP0_EBase;
  1161 + T0 = (int32_t)env->CP0_EBase;
1156 1162 RETURN();
1157 1163 }
1158 1164  
1159 1165 void op_mfc0_config0 (void)
1160 1166 {
1161   - T0 = (int32_t)env->CP0_Config0;
  1167 + T0 = env->CP0_Config0;
1162 1168 RETURN();
1163 1169 }
1164 1170  
1165 1171 void op_mfc0_config1 (void)
1166 1172 {
1167   - T0 = (int32_t)env->CP0_Config1;
  1173 + T0 = env->CP0_Config1;
1168 1174 RETURN();
1169 1175 }
1170 1176  
1171 1177 void op_mfc0_config2 (void)
1172 1178 {
1173   - T0 = (int32_t)env->CP0_Config2;
  1179 + T0 = env->CP0_Config2;
1174 1180 RETURN();
1175 1181 }
1176 1182  
1177 1183 void op_mfc0_config3 (void)
1178 1184 {
1179   - T0 = (int32_t)env->CP0_Config3;
  1185 + T0 = env->CP0_Config3;
1180 1186 RETURN();
1181 1187 }
1182 1188  
1183 1189 void op_mfc0_lladdr (void)
1184 1190 {
1185   - T0 = env->CP0_LLAddr >> 4;
  1191 + T0 = (int32_t)env->CP0_LLAddr >> 4;
1186 1192 RETURN();
1187 1193 }
1188 1194  
... ... @@ -1194,13 +1200,13 @@ void op_mfc0_watchlo0 (void)
1194 1200  
1195 1201 void op_mfc0_watchhi0 (void)
1196 1202 {
1197   - T0 = (int32_t)env->CP0_WatchHi;
  1203 + T0 = env->CP0_WatchHi;
1198 1204 RETURN();
1199 1205 }
1200 1206  
1201 1207 void op_mfc0_xcontext (void)
1202 1208 {
1203   - T0 = env->CP0_XContext;
  1209 + T0 = (int32_t)env->CP0_XContext;
1204 1210 RETURN();
1205 1211 }
1206 1212  
... ... @@ -1212,7 +1218,7 @@ void op_mfc0_framemask (void)
1212 1218  
1213 1219 void op_mfc0_debug (void)
1214 1220 {
1215   - T0 = (int32_t)env->CP0_Debug;
  1221 + T0 = env->CP0_Debug;
1216 1222 if (env->hflags & MIPS_HFLAG_DM)
1217 1223 T0 |= 1 << CP0DB_DM;
1218 1224 RETURN();
... ... @@ -1220,55 +1226,55 @@ void op_mfc0_debug (void)
1220 1226  
1221 1227 void op_mfc0_depc (void)
1222 1228 {
1223   - T0 = env->CP0_DEPC;
  1229 + T0 = (int32_t)env->CP0_DEPC;
1224 1230 RETURN();
1225 1231 }
1226 1232  
1227 1233 void op_mfc0_performance0 (void)
1228 1234 {
1229   - T0 = (int32_t)env->CP0_Performance0;
  1235 + T0 = env->CP0_Performance0;
1230 1236 RETURN();
1231 1237 }
1232 1238  
1233 1239 void op_mfc0_taglo (void)
1234 1240 {
1235   - T0 = (int32_t)env->CP0_TagLo;
  1241 + T0 = env->CP0_TagLo;
1236 1242 RETURN();
1237 1243 }
1238 1244  
1239 1245 void op_mfc0_datalo (void)
1240 1246 {
1241   - T0 = (int32_t)env->CP0_DataLo;
  1247 + T0 = env->CP0_DataLo;
1242 1248 RETURN();
1243 1249 }
1244 1250  
1245 1251 void op_mfc0_taghi (void)
1246 1252 {
1247   - T0 = (int32_t)env->CP0_TagHi;
  1253 + T0 = env->CP0_TagHi;
1248 1254 RETURN();
1249 1255 }
1250 1256  
1251 1257 void op_mfc0_datahi (void)
1252 1258 {
1253   - T0 = (int32_t)env->CP0_DataHi;
  1259 + T0 = env->CP0_DataHi;
1254 1260 RETURN();
1255 1261 }
1256 1262  
1257 1263 void op_mfc0_errorepc (void)
1258 1264 {
1259   - T0 = env->CP0_ErrorEPC;
  1265 + T0 = (int32_t)env->CP0_ErrorEPC;
1260 1266 RETURN();
1261 1267 }
1262 1268  
1263 1269 void op_mfc0_desave (void)
1264 1270 {
1265   - T0 = (int32_t)env->CP0_DESAVE;
  1271 + T0 = env->CP0_DESAVE;
1266 1272 RETURN();
1267 1273 }
1268 1274  
1269 1275 void op_mtc0_index (void)
1270 1276 {
1271   - env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
  1277 + env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
1272 1278 RETURN();
1273 1279 }
1274 1280  
... ... @@ -1276,7 +1282,7 @@ void op_mtc0_entrylo0 (void)
1276 1282 {
1277 1283 /* Large physaddr not implemented */
1278 1284 /* 1k pages not implemented */
1279   - env->CP0_EntryLo0 = T0 & (int32_t)0x3FFFFFFF;
  1285 + env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
1280 1286 RETURN();
1281 1287 }
1282 1288  
... ... @@ -1284,7 +1290,7 @@ void op_mtc0_entrylo1 (void)
1284 1290 {
1285 1291 /* Large physaddr not implemented */
1286 1292 /* 1k pages not implemented */
1287   - env->CP0_EntryLo1 = T0 & (int32_t)0x3FFFFFFF;
  1293 + env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
1288 1294 RETURN();
1289 1295 }
1290 1296  
... ... @@ -1334,7 +1340,7 @@ void op_mtc0_entryhi (void)
1334 1340  
1335 1341 /* 1k pages not implemented */
1336 1342 /* Ignore MIPS64 TLB for now */
1337   - val = T0 & (int32_t)0xFFFFE0FF;
  1343 + val = (int32_t)T0 & 0xFFFFE0FF;
1338 1344 old = env->CP0_EntryHi;
1339 1345 env->CP0_EntryHi = val;
1340 1346 /* If the ASID changes, flush qemu's TLB. */
... ... @@ -1353,7 +1359,7 @@ void op_mtc0_status (void)
1353 1359 {
1354 1360 uint32_t val, old, mask;
1355 1361  
1356   - val = T0 & (int32_t)0xFA78FF01;
  1362 + val = (int32_t)T0 & 0xFA78FF01;
1357 1363 old = env->CP0_Status;
1358 1364 if (T0 & (1 << CP0St_UM))
1359 1365 env->hflags |= MIPS_HFLAG_UM;
... ... @@ -1400,6 +1406,13 @@ void op_mtc0_srsctl (void)
1400 1406 RETURN();
1401 1407 }
1402 1408  
  1409 +void op_mtc0_srsmap (void)
  1410 +{
  1411 + /* shadow registers not implemented */
  1412 + env->CP0_SRSMap = 0;
  1413 + RETURN();
  1414 +}
  1415 +
1403 1416 void op_mtc0_cause (void)
1404 1417 {
1405 1418 uint32_t val, old;
... ... @@ -1423,7 +1436,7 @@ void op_mtc0_cause (void)
1423 1436  
1424 1437 void op_mtc0_epc (void)
1425 1438 {
1426   - env->CP0_EPC = T0;
  1439 + env->CP0_EPC = (int32_t)T0;
1427 1440 RETURN();
1428 1441 }
1429 1442  
... ... @@ -1455,7 +1468,7 @@ void op_mtc0_config2 (void)
1455 1468  
1456 1469 void op_mtc0_watchlo0 (void)
1457 1470 {
1458   - env->CP0_WatchLo = T0;
  1471 + env->CP0_WatchLo = (int32_t)T0;
1459 1472 RETURN();
1460 1473 }
1461 1474  
... ... @@ -1467,7 +1480,7 @@ void op_mtc0_watchhi0 (void)
1467 1480  
1468 1481 void op_mtc0_xcontext (void)
1469 1482 {
1470   - env->CP0_XContext = T0; /* XXX */
  1483 + env->CP0_XContext = (int32_t)T0; /* XXX */
1471 1484 RETURN();
1472 1485 }
1473 1486  
... ... @@ -1489,7 +1502,7 @@ void op_mtc0_debug (void)
1489 1502  
1490 1503 void op_mtc0_depc (void)
1491 1504 {
1492   - env->CP0_DEPC = T0;
  1505 + env->CP0_DEPC = (int32_t)T0;
1493 1506 RETURN();
1494 1507 }
1495 1508  
... ... @@ -1501,7 +1514,7 @@ void op_mtc0_performance0 (void)
1501 1514  
1502 1515 void op_mtc0_taglo (void)
1503 1516 {
1504   - env->CP0_TagLo = T0 & (int32_t)0xFFFFFCF6;
  1517 + env->CP0_TagLo = T0 & 0xFFFFFCF6;
1505 1518 RETURN();
1506 1519 }
1507 1520  
... ... @@ -1525,7 +1538,7 @@ void op_mtc0_datahi (void)
1525 1538  
1526 1539 void op_mtc0_errorepc (void)
1527 1540 {
1528   - env->CP0_ErrorEPC = T0;
  1541 + env->CP0_ErrorEPC = (int32_t)T0;
1529 1542 RETURN();
1530 1543 }
1531 1544  
... ... @@ -1535,6 +1548,139 @@ void op_mtc0_desave (void)
1535 1548 RETURN();
1536 1549 }
1537 1550  
  1551 +void op_dmfc0_entrylo0 (void)
  1552 +{
  1553 + T0 = env->CP0_EntryLo0;
  1554 + RETURN();
  1555 +}
  1556 +
  1557 +void op_dmfc0_entrylo1 (void)
  1558 +{
  1559 + T0 = env->CP0_EntryLo1;
  1560 + RETURN();
  1561 +}
  1562 +
  1563 +void op_dmfc0_context (void)
  1564 +{
  1565 + T0 = env->CP0_Context;
  1566 + RETURN();
  1567 +}
  1568 +
  1569 +void op_dmfc0_badvaddr (void)
  1570 +{
  1571 + T0 = env->CP0_BadVAddr;
  1572 + RETURN();
  1573 +}
  1574 +
  1575 +void op_dmfc0_entryhi (void)
  1576 +{
  1577 + T0 = env->CP0_EntryHi;
  1578 + RETURN();
  1579 +}
  1580 +
  1581 +void op_dmfc0_epc (void)
  1582 +{
  1583 + T0 = env->CP0_EPC;
  1584 + RETURN();
  1585 +}
  1586 +
  1587 +void op_dmfc0_ebase (void)
  1588 +{
  1589 + T0 = env->CP0_EBase;
  1590 + RETURN();
  1591 +}
  1592 +
  1593 +void op_dmfc0_lladdr (void)
  1594 +{
  1595 + T0 = env->CP0_LLAddr >> 4;
  1596 + RETURN();
  1597 +}
  1598 +
  1599 +void op_dmfc0_watchlo0 (void)
  1600 +{
  1601 + T0 = env->CP0_WatchLo;
  1602 + RETURN();
  1603 +}
  1604 +
  1605 +void op_dmfc0_xcontext (void)
  1606 +{
  1607 + T0 = env->CP0_XContext;
  1608 + RETURN();
  1609 +}
  1610 +
  1611 +void op_dmfc0_depc (void)
  1612 +{
  1613 + T0 = env->CP0_DEPC;
  1614 + RETURN();
  1615 +}
  1616 +
  1617 +void op_dmfc0_errorepc (void)
  1618 +{
  1619 + T0 = env->CP0_ErrorEPC;
  1620 + RETURN();
  1621 +}
  1622 +
  1623 +void op_dmtc0_entrylo0 (void)
  1624 +{
  1625 + /* Large physaddr not implemented */
  1626 + /* 1k pages not implemented */
  1627 + env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
  1628 + RETURN();
  1629 +}
  1630 +
  1631 +void op_dmtc0_entrylo1 (void)
  1632 +{
  1633 + /* Large physaddr not implemented */
  1634 + /* 1k pages not implemented */
  1635 + env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
  1636 + RETURN();
  1637 +}
  1638 +
  1639 +void op_dmtc0_context (void)
  1640 +{
  1641 + env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
  1642 + RETURN();
  1643 +}
  1644 +
  1645 +void op_dmtc0_epc (void)
  1646 +{
  1647 + env->CP0_EPC = T0;
  1648 + RETURN();
  1649 +}
  1650 +
  1651 +void op_dmtc0_ebase (void)
  1652 +{
  1653 + /* vectored interrupts not implemented */
  1654 + /* Multi-CPU not implemented */
  1655 + /* XXX: 64bit addressing broken */
  1656 + env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
  1657 + RETURN();
  1658 +}
  1659 +
  1660 +void op_dmtc0_watchlo0 (void)
  1661 +{
  1662 + env->CP0_WatchLo = T0;
  1663 + RETURN();
  1664 +}
  1665 +
  1666 +void op_dmtc0_xcontext (void)
  1667 +{
  1668 + env->CP0_XContext = T0; /* XXX */
  1669 + RETURN();
  1670 +}
  1671 +
  1672 +void op_dmtc0_depc (void)
  1673 +{
  1674 + env->CP0_DEPC = T0;
  1675 + RETURN();
  1676 +}
  1677 +
  1678 +void op_dmtc0_errorepc (void)
  1679 +{
  1680 + env->CP0_ErrorEPC = T0;
  1681 + RETURN();
  1682 +}
  1683 +
1538 1684 #ifdef MIPS_USES_FPU
1539 1685  
1540 1686 #if 0
... ...
target-mips/op_helper.c
  View file @9c2149c
... ... @@ -411,10 +411,10 @@ void do_tlbwi (void)
411 411 that might be a further win. */
412 412 mips_tlb_flush_extra (env, MIPS_TLB_NB);
413 413  
414   - /* Wildly undefined effects for CP0_index containing a too high value and
  414 + /* Wildly undefined effects for CP0_Index containing a too high value and
415 415 MIPS_TLB_NB not being a power of two. But so does real silicon. */
416   - invalidate_tlb(env, env->CP0_index & (MIPS_TLB_NB - 1), 0);
417   - fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
  416 + invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0);
  417 + fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
418 418 }
419 419  
420 420 void do_tlbwr (void)
... ... @@ -439,7 +439,7 @@ void do_tlbp (void)
439 439 /* Check ASID, virtual page number & size */
440 440 if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
441 441 /* TLB match */
442   - env->CP0_index = i;
  442 + env->CP0_Index = i;
443 443 break;
444 444 }
445 445 }
... ... @@ -455,7 +455,7 @@ void do_tlbp (void)
455 455 }
456 456 }
457 457  
458   - env->CP0_index |= 0x80000000;
  458 + env->CP0_Index |= 0x80000000;
459 459 }
460 460 }
461 461  
... ... @@ -465,7 +465,7 @@ void do_tlbr (void)
465 465 uint8_t ASID;
466 466  
467 467 ASID = env->CP0_EntryHi & 0xFF;
468   - tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
  468 + tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
469 469  
470 470 /* If this will change the current ASID, flush qemu's TLB. */
471 471 if (ASID != tlb->ASID)
... ...
target-mips/translate.c
  View file @9c2149c
... ... @@ -2827,6 +2827,1181 @@ die:
2827 2827 generate_exception(ctx, EXCP_RI);
2828 2828 }
2829 2829  
  2830 +static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
  2831 +{
  2832 + const char *rn = "invalid";
  2833 +
  2834 + switch (reg) {
  2835 + case 0:
  2836 + switch (sel) {
  2837 + case 0:
  2838 + gen_op_mfc0_index();
  2839 + rn = "Index";
  2840 + break;
  2841 + case 1:
  2842 +// gen_op_dmfc0_mvpcontrol(); /* MT ASE */
  2843 + rn = "MVPControl";
  2844 +// break;
  2845 + case 2:
  2846 +// gen_op_dmfc0_mvpconf0(); /* MT ASE */
  2847 + rn = "MVPConf0";
  2848 +// break;
  2849 + case 3:
  2850 +// gen_op_dmfc0_mvpconf1(); /* MT ASE */
  2851 + rn = "MVPConf1";
  2852 +// break;
  2853 + default:
  2854 + goto die;
  2855 + }
  2856 + break;
  2857 + case 1:
  2858 + switch (sel) {
  2859 + case 0:
  2860 + gen_op_mfc0_random();
  2861 + rn = "Random";
  2862 + break;
  2863 + case 1:
  2864 +// gen_op_dmfc0_vpecontrol(); /* MT ASE */
  2865 + rn = "VPEControl";
  2866 +// break;
  2867 + case 2:
  2868 +// gen_op_dmfc0_vpeconf0(); /* MT ASE */
  2869 + rn = "VPEConf0";
  2870 +// break;
  2871 + case 3:
  2872 +// gen_op_dmfc0_vpeconf1(); /* MT ASE */
  2873 + rn = "VPEConf1";
  2874 +// break;
  2875 + case 4:
  2876 +// gen_op_dmfc0_YQMask(); /* MT ASE */
  2877 + rn = "YQMask";
  2878 +// break;
  2879 + case 5:
  2880 +// gen_op_dmfc0_vpeschedule(); /* MT ASE */
  2881 + rn = "VPESchedule";
  2882 +// break;
  2883 + case 6:
  2884 +// gen_op_dmfc0_vpeschefback(); /* MT ASE */
  2885 + rn = "VPEScheFBack";
  2886 +// break;
  2887 + case 7:
  2888 +// gen_op_dmfc0_vpeopt(); /* MT ASE */
  2889 + rn = "VPEOpt";
  2890 +// break;
  2891 + default:
  2892 + goto die;
  2893 + }
  2894 + break;
  2895 + case 2:
  2896 + switch (sel) {
  2897 + case 0:
  2898 + gen_op_dmfc0_entrylo0();
  2899 + rn = "EntryLo0";
  2900 + break;
  2901 + case 1:
  2902 +// gen_op_dmfc0_tcstatus(); /* MT ASE */
  2903 + rn = "TCStatus";
  2904 +// break;
  2905 + case 2:
  2906 +// gen_op_dmfc0_tcbind(); /* MT ASE */
  2907 + rn = "TCBind";
  2908 +// break;
  2909 + case 3:
  2910 +// gen_op_dmfc0_tcrestart(); /* MT ASE */
  2911 + rn = "TCRestart";
  2912 +// break;
  2913 + case 4:
  2914 +// gen_op_dmfc0_tchalt(); /* MT ASE */
  2915 + rn = "TCHalt";
  2916 +// break;
  2917 + case 5:
  2918 +// gen_op_dmfc0_tccontext(); /* MT ASE */
  2919 + rn = "TCContext";
  2920 +// break;
  2921 + case 6:
  2922 +// gen_op_dmfc0_tcschedule(); /* MT ASE */
  2923 + rn = "TCSchedule";
  2924 +// break;
  2925 + case 7:
  2926 +// gen_op_dmfc0_tcschefback(); /* MT ASE */
  2927 + rn = "TCScheFBack";
  2928 +// break;
  2929 + default:
  2930 + goto die;
  2931 + }
  2932 + break;
  2933 + case 3:
  2934 + switch (sel) {
  2935 + case 0:
  2936 + gen_op_dmfc0_entrylo1();
  2937 + rn = "EntryLo1";
  2938 + break;
  2939 + default:
  2940 + goto die;
  2941 + }
  2942 + break;
  2943 + case 4:
  2944 + switch (sel) {
  2945 + case 0:
  2946 + gen_op_dmfc0_context();
  2947 + rn = "Context";
  2948 + break;
  2949 + case 1:
  2950 +// gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
  2951 + rn = "ContextConfig";
  2952 +// break;
  2953 + default:
  2954 + goto die;
  2955 + }
  2956 + break;
  2957 + case 5:
  2958 + switch (sel) {
  2959 + case 0:
  2960 + gen_op_mfc0_pagemask();
  2961 + rn = "PageMask";
  2962 + break;
  2963 + case 1:
  2964 + gen_op_mfc0_pagegrain();
  2965 + rn = "PageGrain";
  2966 + break;
  2967 + default:
  2968 + goto die;
  2969 + }
  2970 + break;
  2971 + case 6:
  2972 + switch (sel) {
  2973 + case 0:
  2974 + gen_op_mfc0_wired();
  2975 + rn = "Wired";
  2976 + break;
  2977 + case 1:
  2978 +// gen_op_dmfc0_srsconf0(); /* shadow registers */
  2979 + rn = "SRSConf0";
  2980 +// break;
  2981 + case 2:
  2982 +// gen_op_dmfc0_srsconf1(); /* shadow registers */
  2983 + rn = "SRSConf1";
  2984 +// break;
  2985 + case 3:
  2986 +// gen_op_dmfc0_srsconf2(); /* shadow registers */
  2987 + rn = "SRSConf2";
  2988 +// break;
  2989 + case 4:
  2990 +// gen_op_dmfc0_srsconf3(); /* shadow registers */
  2991 + rn = "SRSConf3";
  2992 +// break;
  2993 + case 5:
  2994 +// gen_op_dmfc0_srsconf4(); /* shadow registers */
  2995 + rn = "SRSConf4";
  2996 +// break;
  2997 + default:
  2998 + goto die;
  2999 + }
  3000 + break;
  3001 + case 7:
  3002 + switch (sel) {
  3003 + case 0:
  3004 + gen_op_mfc0_hwrena();
  3005 + rn = "HWREna";
  3006 + break;
  3007 + default:
  3008 + goto die;
  3009 + }
  3010 + break;
  3011 + case 8:
  3012 + switch (sel) {
  3013 + case 0:
  3014 + gen_op_dmfc0_badvaddr();
  3015 + rn = "BadVaddr";
  3016 + break;
  3017 + default:
  3018 + goto die;
  3019 + }
  3020 + break;
  3021 + case 9:
  3022 + switch (sel) {
  3023 + case 0:
  3024 + gen_op_mfc0_count();
  3025 + rn = "Count";
  3026 + break;
  3027 + /* 6,7 are implementation dependent */
  3028 + default:
  3029 + goto die;
  3030 + }
  3031 + break;
  3032 + case 10:
  3033 + switch (sel) {
  3034 + case 0:
  3035 + gen_op_dmfc0_entryhi();
  3036 + rn = "EntryHi";
  3037 + break;
  3038 + default:
  3039 + goto die;
  3040 + }
  3041 + break;
  3042 + case 11:
  3043 + switch (sel) {
  3044 + case 0:
  3045 + gen_op_mfc0_compare();
  3046 + rn = "Compare";
  3047 + break;
  3048 + /* 6,7 are implementation dependent */
  3049 + default:
  3050 + goto die;
  3051 + }
  3052 + break;
  3053 + case 12:
  3054 + switch (sel) {
  3055 + case 0:
  3056 + gen_op_mfc0_status();
  3057 + rn = "Status";
  3058 + break;
  3059 + case 1:
  3060 + gen_op_mfc0_intctl();
  3061 + rn = "IntCtl";
  3062 + break;
  3063 + case 2:
  3064 + gen_op_mfc0_srsctl();
  3065 + rn = "SRSCtl";
  3066 + break;
  3067 + case 3:
  3068 + gen_op_mfc0_srsmap(); /* shadow registers */
  3069 + rn = "SRSMap";
  3070 + break;
  3071 + default:
  3072 + goto die;
  3073 + }
  3074 + break;
  3075 + case 13:
  3076 + switch (sel) {
  3077 + case 0:
  3078 + gen_op_mfc0_cause();
  3079 + rn = "Cause";
  3080 + break;
  3081 + default:
  3082 + goto die;
  3083 + }
  3084 + break;
  3085 + case 14:
  3086 + switch (sel) {
  3087 + case 0:
  3088 + gen_op_dmfc0_epc();
  3089 + rn = "EPC";
  3090 + break;
  3091 + default:
  3092 + goto die;
  3093 + }
  3094 + break;
  3095 + case 15:
  3096 + switch (sel) {
  3097 + case 0:
  3098 + gen_op_mfc0_prid();
  3099 + rn = "PRid";
  3100 + break;
  3101 + case 1:
  3102 + gen_op_dmfc0_ebase();
  3103 + rn = "EBase";
  3104 + break;
  3105 + default:
  3106 + goto die;
  3107 + }
  3108 + break;
  3109 + case 16:
  3110 + switch (sel) {
  3111 + case 0:
  3112 + gen_op_mfc0_config0();
  3113 + rn = "Config";
  3114 + break;
  3115 + case 1:
  3116 + gen_op_mfc0_config1();
  3117 + rn = "Config1";
  3118 + break;
  3119 + case 2:
  3120 + gen_op_mfc0_config2();
  3121 + rn = "Config2";
  3122 + break;
  3123 + case 3:
  3124 + gen_op_mfc0_config3();
  3125 + rn = "Config3";
  3126 + break;
  3127 + /* 6,7 are implementation dependent */
  3128 + default:
  3129 + goto die;
  3130 + }
  3131 + break;
  3132 + case 17:
  3133 + switch (sel) {
  3134 + case 0:
  3135 + gen_op_dmfc0_lladdr();
  3136 + rn = "LLAddr";
  3137 + break;
  3138 + default:
  3139 + goto die;
  3140 + }
  3141 + break;
  3142 + case 18:
  3143 + switch (sel) {
  3144 + case 0:
  3145 + gen_op_dmfc0_watchlo0();
  3146 + rn = "WatchLo";
  3147 + break;
  3148 + case 1:
  3149 +// gen_op_dmfc0_watchlo1();
  3150 + rn = "WatchLo1";
  3151 +// break;
  3152 + case 2:
  3153 +// gen_op_dmfc0_watchlo2();
  3154 + rn = "WatchLo2";
  3155 +// break;
  3156 + case 3:
  3157 +// gen_op_dmfc0_watchlo3();
  3158 + rn = "WatchLo3";
  3159 +// break;
  3160 + case 4:
  3161 +// gen_op_dmfc0_watchlo4();
  3162 + rn = "WatchLo4";
  3163 +// break;
  3164 + case 5:
  3165 +// gen_op_dmfc0_watchlo5();
  3166 + rn = "WatchLo5";
  3167 +// break;
  3168 + case 6:
  3169 +// gen_op_dmfc0_watchlo6();
  3170 + rn = "WatchLo6";
  3171 +// break;
  3172 + case 7:
  3173 +// gen_op_dmfc0_watchlo7();
  3174 + rn = "WatchLo7";
  3175 +// break;
  3176 + default:
  3177 + goto die;
  3178 + }
  3179 + break;
  3180 + case 19:
  3181 + switch (sel) {
  3182 + case 0:
  3183 + gen_op_mfc0_watchhi0();
  3184 + rn = "WatchHi";
  3185 + break;
  3186 + case 1:
  3187 +// gen_op_mfc0_watchhi1();
  3188 + rn = "WatchHi1";
  3189 +// break;
  3190 + case 2:
  3191 +// gen_op_mfc0_watchhi2();
  3192 + rn = "WatchHi2";
  3193 +// break;
  3194 + case 3:
  3195 +// gen_op_mfc0_watchhi3();
  3196 + rn = "WatchHi3";
  3197 +// break;
  3198 + case 4:
  3199 +// gen_op_mfc0_watchhi4();
  3200 + rn = "WatchHi4";
  3201 +// break;
  3202 + case 5:
  3203 +// gen_op_mfc0_watchhi5();
  3204 + rn = "WatchHi5";
  3205 +// break;
  3206 + case 6:
  3207 +// gen_op_mfc0_watchhi6();
  3208 + rn = "WatchHi6";
  3209 +// break;
  3210 + case 7:
  3211 +// gen_op_mfc0_watchhi7();
  3212 + rn = "WatchHi7";
  3213 +// break;
  3214 + default:
  3215 + goto die;
  3216 + }
  3217 + break;
  3218 + case 20:
  3219 + switch (sel) {
  3220 + case 0:
  3221 + /* 64 bit MMU only */
  3222 + gen_op_dmfc0_xcontext();
  3223 + rn = "XContext";
  3224 + break;
  3225 + default:
  3226 + goto die;
  3227 + }
  3228 + break;
  3229 + case 21:
  3230 + /* Officially reserved, but sel 0 is used for R1x000 framemask */
  3231 + switch (sel) {
  3232 + case 0:
  3233 + gen_op_mfc0_framemask();
  3234 + rn = "Framemask";
  3235 + break;
  3236 + default:
  3237 + goto die;
  3238 + }
  3239 + break;
  3240 + case 22:
  3241 + /* ignored */
  3242 + rn = "'Diagnostic"; /* implementation dependent */
  3243 + break;
  3244 + case 23:
  3245 + switch (sel) {
  3246 + case 0:
  3247 + gen_op_mfc0_debug(); /* EJTAG support */
  3248 + rn = "Debug";
  3249 + break;
  3250 + case 1:
  3251 +// gen_op_dmfc0_tracecontrol(); /* PDtrace support */
  3252 + rn = "TraceControl";
  3253 +// break;
  3254 + case 2:
  3255 +// gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
  3256 + rn = "TraceControl2";
  3257 +// break;
  3258 + case 3:
  3259 +// gen_op_dmfc0_usertracedata(); /* PDtrace support */
  3260 + rn = "UserTraceData";
  3261 +// break;
  3262 + case 4:
  3263 +// gen_op_dmfc0_debug(); /* PDtrace support */
  3264 + rn = "TraceBPC";
  3265 +// break;
  3266 + default:
  3267 + goto die;
  3268 + }
  3269 + break;
  3270 + case 24:
  3271 + switch (sel) {
  3272 + case 0:
  3273 + gen_op_dmfc0_depc(); /* EJTAG support */
  3274 + rn = "DEPC";
  3275 + break;
  3276 + default:
  3277 + goto die;
  3278 + }
  3279 + break;
  3280 + case 25:
  3281 + switch (sel) {
  3282 + case 0:
  3283 + gen_op_mfc0_performance0();
  3284 + rn = "Performance0";
  3285 + break;
  3286 + case 1:
  3287 +// gen_op_dmfc0_performance1();
  3288 + rn = "Performance1";
  3289 +// break;
  3290 + case 2:
  3291 +// gen_op_dmfc0_performance2();
  3292 + rn = "Performance2";
  3293 +// break;
  3294 + case 3:
  3295 +// gen_op_dmfc0_performance3();
  3296 + rn = "Performance3";
  3297 +// break;
  3298 + case 4:
  3299 +// gen_op_dmfc0_performance4();
  3300 + rn = "Performance4";
  3301 +// break;
  3302 + case 5:
  3303 +// gen_op_dmfc0_performance5();
  3304 + rn = "Performance5";
  3305 +// break;
  3306 + case 6:
  3307 +// gen_op_dmfc0_performance6();
  3308 + rn = "Performance6";
  3309 +// break;
  3310 + case 7:
  3311 +// gen_op_dmfc0_performance7();
  3312 + rn = "Performance7";
  3313 +// break;
  3314 + default:
  3315 + goto die;
  3316 + }
  3317 + break;
  3318 + case 26:
  3319 + rn = "ECC";
  3320 + break;
  3321 + case 27:
  3322 + switch (sel) {
  3323 + /* ignored */
  3324 + case 0 ... 3:
  3325 + rn = "CacheErr";
  3326 + break;
  3327 + default:
  3328 + goto die;
  3329 + }
  3330 + break;
  3331 + case 28:
  3332 + switch (sel) {
  3333 + case 0:
  3334 + case 2:
  3335 + case 4:
  3336 + case 6:
  3337 + gen_op_mfc0_taglo();
  3338 + rn = "TagLo";
  3339 + break;
  3340 + case 1:
  3341 + case 3:
  3342 + case 5:
  3343 + case 7:
  3344 + gen_op_mfc0_datalo();
  3345 + rn = "DataLo";
  3346 + break;
  3347 + default:
  3348 + goto die;
  3349 + }
  3350 + break;
  3351 + case 29:
  3352 + switch (sel) {
  3353 + case 0:
  3354 + case 2:
  3355 + case 4:
  3356 + case 6:
  3357 + gen_op_mfc0_taghi();
  3358 + rn = "TagHi";
  3359 + break;
  3360 + case 1:
  3361 + case 3:
  3362 + case 5:
  3363 + case 7:
  3364 + gen_op_mfc0_datahi();
  3365 + rn = "DataHi";
  3366 + break;
  3367 + default:
  3368 + goto die;
  3369 + }
  3370 + break;
  3371 + case 30:
  3372 + switch (sel) {
  3373 + case 0:
  3374 + gen_op_dmfc0_errorepc();
  3375 + rn = "ErrorEPC";
  3376 + break;
  3377 + default:
  3378 + goto die;
  3379 + }
  3380 + break;
  3381 + case 31:
  3382 + switch (sel) {
  3383 + case 0:
  3384 + gen_op_mfc0_desave(); /* EJTAG support */
  3385 + rn = "DESAVE";
  3386 + break;
  3387 + default:
  3388 + goto die;
  3389 + }
  3390 + break;
  3391 + default:
  3392 + goto die;
  3393 + }
  3394 +#if defined MIPS_DEBUG_DISAS
  3395 + if (loglevel & CPU_LOG_TB_IN_ASM) {
  3396 + fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
  3397 + rn, reg, sel);
  3398 + }
  3399 +#endif
  3400 + return;
  3401 +
  3402 +die:
  3403 +#if defined MIPS_DEBUG_DISAS
  3404 + if (loglevel & CPU_LOG_TB_IN_ASM) {
  3405 + fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
  3406 + rn, reg, sel);
  3407 + }
  3408 +#endif
  3409 + generate_exception(ctx, EXCP_RI);
  3410 +}
  3411 +
  3412 +static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
  3413 +{
  3414 + const char *rn = "invalid";
  3415 +
  3416 + switch (reg) {
  3417 + case 0:
  3418 + switch (sel) {
  3419 + case 0:
  3420 + gen_op_mtc0_index();
  3421 + rn = "Index";
  3422 + break;
  3423 + case 1:
  3424 +// gen_op_dmtc0_mvpcontrol(); /* MT ASE */
  3425 + rn = "MVPControl";
  3426 +// break;
  3427 + case 2:
  3428 +// gen_op_dmtc0_mvpconf0(); /* MT ASE */
  3429 + rn = "MVPConf0";
  3430 +// break;
  3431 + case 3:
  3432 +// gen_op_dmtc0_mvpconf1(); /* MT ASE */
  3433 + rn = "MVPConf1";
  3434 +// break;
  3435 + default:
  3436 + goto die;
  3437 + }
  3438 + break;
  3439 + case 1:
  3440 + switch (sel) {
  3441 + case 0:
  3442 + /* ignored */
  3443 + rn = "Random";
  3444 + break;
  3445 + case 1:
  3446 +// gen_op_dmtc0_vpecontrol(); /* MT ASE */
  3447 + rn = "VPEControl";
  3448 +// break;
  3449 + case 2:
  3450 +// gen_op_dmtc0_vpeconf0(); /* MT ASE */
  3451 + rn = "VPEConf0";
  3452 +// break;
  3453 + case 3:
  3454 +// gen_op_dmtc0_vpeconf1(); /* MT ASE */
  3455 + rn = "VPEConf1";
  3456 +// break;
  3457 + case 4:
  3458 +// gen_op_dmtc0_YQMask(); /* MT ASE */
  3459 + rn = "YQMask";
  3460 +// break;
  3461 + case 5:
  3462 +// gen_op_dmtc0_vpeschedule(); /* MT ASE */
  3463 + rn = "VPESchedule";
  3464 +// break;
  3465 + case 6:
  3466 +// gen_op_dmtc0_vpeschefback(); /* MT ASE */
  3467 + rn = "VPEScheFBack";
  3468 +// break;
  3469 + case 7:
  3470 +// gen_op_dmtc0_vpeopt(); /* MT ASE */
  3471 + rn = "VPEOpt";
  3472 +// break;
  3473 + default:
  3474 + goto die;
  3475 + }
  3476 + break;
  3477 + case 2:
  3478 + switch (sel) {
  3479 + case 0:
  3480 + gen_op_dmtc0_entrylo0();
  3481 + rn = "EntryLo0";
  3482 + break;
  3483 + case 1:
  3484 +// gen_op_dmtc0_tcstatus(); /* MT ASE */
  3485 + rn = "TCStatus";
  3486 +// break;
  3487 + case 2:
  3488 +// gen_op_dmtc0_tcbind(); /* MT ASE */
  3489 + rn = "TCBind";
  3490 +// break;
  3491 + case 3:
  3492 +// gen_op_dmtc0_tcrestart(); /* MT ASE */
  3493 + rn = "TCRestart";
  3494 +// break;
  3495 + case 4:
  3496 +// gen_op_dmtc0_tchalt(); /* MT ASE */
  3497 + rn = "TCHalt";
  3498 +// break;
  3499 + case 5:
  3500 +// gen_op_dmtc0_tccontext(); /* MT ASE */
  3501 + rn = "TCContext";
  3502 +// break;
  3503 + case 6:
  3504 +// gen_op_dmtc0_tcschedule(); /* MT ASE */
  3505 + rn = "TCSchedule";
  3506 +// break;
  3507 + case 7:
  3508 +// gen_op_dmtc0_tcschefback(); /* MT ASE */
  3509 + rn = "TCScheFBack";
  3510 +// break;
  3511 + default:
  3512 + goto die;
  3513 + }
  3514 + break;
  3515 + case 3:
  3516 + switch (sel) {
  3517 + case 0:
  3518 + gen_op_dmtc0_entrylo1();
  3519 + rn = "EntryLo1";
  3520 + break;
  3521 + default:
  3522 + goto die;
  3523 + }
  3524 + break;
  3525 + case 4:
  3526 + switch (sel) {
  3527 + case 0:
  3528 + gen_op_dmtc0_context();
  3529 + rn = "Context";
  3530 + break;
  3531 + case 1:
  3532 +// gen_op_dmtc0_contextconfig(); /* SmartMIPS ASE */
  3533 + rn = "ContextConfig";
  3534 +// break;
  3535 + default:
  3536 + goto die;
  3537 + }
  3538 + break;
  3539 + case 5:
  3540 + switch (sel) {
  3541 + case 0:
  3542 + gen_op_mtc0_pagemask();
  3543 + rn = "PageMask";
  3544 + break;
  3545 + case 1:
  3546 + gen_op_mtc0_pagegrain();
  3547 + rn = "PageGrain";
  3548 + break;
  3549 + default:
  3550 + goto die;
  3551 + }
  3552 + break;
  3553 + case 6:
  3554 + switch (sel) {
  3555 + case 0:
  3556 + gen_op_mtc0_wired();
  3557 + rn = "Wired";
  3558 + break;
  3559 + case 1:
  3560 +// gen_op_dmtc0_srsconf0(); /* shadow registers */
  3561 + rn = "SRSConf0";
  3562 +// break;
  3563 + case 2:
  3564 +// gen_op_dmtc0_srsconf1(); /* shadow registers */
  3565 + rn = "SRSConf1";
  3566 +// break;
  3567 + case 3:
  3568 +// gen_op_dmtc0_srsconf2(); /* shadow registers */
  3569 + rn = "SRSConf2";
  3570 +// break;
  3571 + case 4:
  3572 +// gen_op_dmtc0_srsconf3(); /* shadow registers */
  3573 + rn = "SRSConf3";
  3574 +// break;
  3575 + case 5:
  3576 +// gen_op_dmtc0_srsconf4(); /* shadow registers */
  3577 + rn = "SRSConf4";
  3578 +// break;
  3579 + default:
  3580 + goto die;
  3581 + }
  3582 + break;
  3583 + case 7:
  3584 + switch (sel) {
  3585 + case 0:
  3586 + gen_op_mtc0_hwrena();
  3587 + rn = "HWREna";
  3588 + break;
  3589 + default:
  3590 + goto die;
  3591 + }
  3592 + break;
  3593 + case 8:
  3594 + /* ignored */
  3595 + rn = "BadVaddr";
  3596 + break;
  3597 + case 9:
  3598 + switch (sel) {
  3599 + case 0:
  3600 + gen_op_mtc0_count();
  3601 + rn = "Count";
  3602 + break;
  3603 + /* 6,7 are implementation dependent */
  3604 + default:
  3605 + goto die;
  3606 + }
  3607 + /* Stop translation as we may have switched the execution mode */
  3608 + ctx->bstate = BS_STOP;
  3609 + break;
  3610 + case 10:
  3611 + switch (sel) {
  3612 + case 0:
  3613 + gen_op_mtc0_entryhi();
  3614 + rn = "EntryHi";
  3615 + break;
  3616 + default:
  3617 + goto die;
  3618 + }
  3619 + break;
  3620 + case 11:
  3621 + switch (sel) {
  3622 + case 0:
  3623 + gen_op_mtc0_compare();
  3624 + rn = "Compare";
  3625 + break;
  3626 + /* 6,7 are implementation dependent */
  3627 + default:
  3628 + goto die;
  3629 + }
  3630 + /* Stop translation as we may have switched the execution mode */
  3631 + ctx->bstate = BS_STOP;
  3632 + break;
  3633 + case 12:
  3634 + switch (sel) {
  3635 + case 0:
  3636 + gen_op_mtc0_status();
  3637 + rn = "Status";
  3638 + break;
  3639 + case 1:
  3640 + gen_op_mtc0_intctl();
  3641 + rn = "IntCtl";
  3642 + break;
  3643 + case 2:
  3644 + gen_op_mtc0_srsctl();
  3645 + rn = "SRSCtl";
  3646 + break;
  3647 + case 3:
  3648 + gen_op_mtc0_srsmap(); /* shadow registers */
  3649 + rn = "SRSMap";
  3650 + break;
  3651 + default:
  3652 + goto die;
  3653 + }
  3654 + /* Stop translation as we may have switched the execution mode */
  3655 + ctx->bstate = BS_STOP;
  3656 + break;
  3657 + case 13:
  3658 + switch (sel) {
  3659 + case 0:
  3660 + gen_op_mtc0_cause();
  3661 + rn = "Cause";
  3662 + break;
  3663 + default:
  3664 + goto die;
  3665 + }
  3666 + /* Stop translation as we may have switched the execution mode */
  3667 + ctx->bstate = BS_STOP;
  3668 + break;
  3669 + case 14:
  3670 + switch (sel) {
  3671 + case 0:
  3672 + gen_op_dmtc0_epc();
  3673 + rn = "EPC";
  3674 + break;
  3675 + default:
  3676 + goto die;
  3677 + }
  3678 + break;
  3679 + case 15:
  3680 + switch (sel) {
  3681 + case 0:
  3682 + /* ignored */
  3683 + rn = "PRid";
  3684 + break;
  3685 + case 1:
  3686 + gen_op_dmtc0_ebase();
  3687 + rn = "EBase";
  3688 + break;
  3689 + default:
  3690 + goto die;
  3691 + }
  3692 + break;
  3693 + case 16:
  3694 + switch (sel) {
  3695 + case 0:
  3696 + gen_op_mtc0_config0();
  3697 + rn = "Config";
  3698 + break;
  3699 + case 1:
  3700 + /* ignored */
  3701 + rn = "Config1";
  3702 + break;
  3703 + case 2:
  3704 + gen_op_mtc0_config2();
  3705 + rn = "Config2";
  3706 + break;
  3707 + case 3:
  3708 + /* ignored */
  3709 + rn = "Config3";
  3710 + break;
  3711 + /* 6,7 are implementation dependent */
  3712 + default:
  3713 + rn = "Invalid config selector";
  3714 + goto die;
  3715 + }
  3716 + /* Stop translation as we may have switched the execution mode */
  3717 + ctx->bstate = BS_STOP;
  3718 + break;
  3719 + case 17:
  3720 + switch (sel) {
  3721 + case 0:
  3722 + /* ignored */
  3723 + rn = "LLAddr";
  3724 + break;
  3725 + default:
  3726 + goto die;
  3727 + }
  3728 + break;
  3729 + case 18:
  3730 + switch (sel) {
  3731 + case 0:
  3732 + gen_op_dmtc0_watchlo0();
  3733 + rn = "WatchLo";
  3734 + break;
  3735 + case 1:
  3736 +// gen_op_dmtc0_watchlo1();
  3737 + rn = "WatchLo1";
  3738 +// break;
  3739 + case 2:
  3740 +// gen_op_dmtc0_watchlo2();
  3741 + rn = "WatchLo2";
  3742 +// break;
  3743 + case 3:
  3744 +// gen_op_dmtc0_watchlo3();
  3745 + rn = "WatchLo3";
  3746 +// break;
  3747 + case 4:
  3748 +// gen_op_dmtc0_watchlo4();
  3749 + rn = "WatchLo4";
  3750 +// break;
  3751 + case 5:
  3752 +// gen_op_dmtc0_watchlo5();
  3753 + rn = "WatchLo5";
  3754 +// break;
  3755 + case 6:
  3756 +// gen_op_dmtc0_watchlo6();
  3757 + rn = "WatchLo6";
  3758 +// break;
  3759 + case 7:
  3760 +// gen_op_dmtc0_watchlo7();
  3761 + rn = "WatchLo7";
  3762 +// break;
  3763 + default:
  3764 + goto die;
  3765 + }
  3766 + break;
  3767 + case 19:
  3768 + switch (sel) {
  3769 + case 0:
  3770 + gen_op_mtc0_watchhi0();
  3771 + rn = "WatchHi";
  3772 + break;
  3773 + case 1:
  3774 +// gen_op_dmtc0_watchhi1();
  3775 + rn = "WatchHi1";
  3776 +// break;
  3777 + case 2:
  3778 +// gen_op_dmtc0_watchhi2();
  3779 + rn = "WatchHi2";
  3780 +// break;
  3781 + case 3:
  3782 +// gen_op_dmtc0_watchhi3();
  3783 + rn = "WatchHi3";
  3784 +// break;
  3785 + case 4:
  3786 +// gen_op_dmtc0_watchhi4();
  3787 + rn = "WatchHi4";
  3788 +// break;
  3789 + case 5:
  3790 +// gen_op_dmtc0_watchhi5();
  3791 + rn = "WatchHi5";
  3792 +// break;
  3793 + case 6:
  3794 +// gen_op_dmtc0_watchhi6();
  3795 + rn = "WatchHi6";
  3796 +// break;
  3797 + case 7:
  3798 +// gen_op_dmtc0_watchhi7();
  3799 + rn = "WatchHi7";
  3800 +// break;
  3801 + default:
  3802 + goto die;
  3803 + }
  3804 + break;
  3805 + case 20:
  3806 + switch (sel) {
  3807 + case 0:
  3808 + /* 64 bit MMU only */
  3809 + gen_op_dmtc0_xcontext();
  3810 + rn = "XContext";
  3811 + break;
  3812 + default:
  3813 + goto die;
  3814 + }
  3815 + break;
  3816 + case 21:
  3817 + /* Officially reserved, but sel 0 is used for R1x000 framemask */
  3818 + switch (sel) {
  3819 + case 0:
  3820 + gen_op_mtc0_framemask();
  3821 + rn = "Framemask";
  3822 + break;
  3823 + default:
  3824 + goto die;
  3825 + }
  3826 + break;
  3827 + case 22:
  3828 + /* ignored */
  3829 + rn = "Diagnostic"; /* implementation dependent */
  3830 + break;
  3831 + case 23:
  3832 + switch (sel) {
  3833 + case 0:
  3834 + gen_op_mtc0_debug(); /* EJTAG support */
  3835 + rn = "Debug";
  3836 + break;
  3837 + case 1:
  3838 +// gen_op_dmtc0_tracecontrol(); /* PDtrace support */
  3839 + rn = "TraceControl";
  3840 +// break;
  3841 + case 2:
  3842 +// gen_op_dmtc0_tracecontrol2(); /* PDtrace support */
  3843 + rn = "TraceControl2";
  3844 +// break;
  3845 + case 3:
  3846 +// gen_op_dmtc0_usertracedata(); /* PDtrace support */
  3847 + rn = "UserTraceData";
  3848 +// break;
  3849 + case 4:
  3850 +// gen_op_dmtc0_debug(); /* PDtrace support */
  3851 + rn = "TraceBPC";
  3852 +// break;
  3853 + default:
  3854 + goto die;
  3855 + }
  3856 + /* Stop translation as we may have switched the execution mode */
  3857 + ctx->bstate = BS_STOP;
  3858 + break;
  3859 + case 24:
  3860 + switch (sel) {
  3861 + case 0:
  3862 + gen_op_dmtc0_depc(); /* EJTAG support */
  3863 + rn = "DEPC";
  3864 + break;
  3865 + default:
  3866 + goto die;
  3867 + }
  3868 + break;
  3869 + case 25:
  3870 + switch (sel) {
  3871 + case 0:
  3872 + gen_op_mtc0_performance0();
  3873 + rn = "Performance0";
  3874 + break;
  3875 + case 1:
  3876 +// gen_op_dmtc0_performance1();
  3877 + rn = "Performance1";
  3878 +// break;
  3879 + case 2:
  3880 +// gen_op_dmtc0_performance2();
  3881 + rn = "Performance2";
  3882 +// break;
  3883 + case 3:
  3884 +// gen_op_dmtc0_performance3();
  3885 + rn = "Performance3";
  3886 +// break;
  3887 + case 4:
  3888 +// gen_op_dmtc0_performance4();
  3889 + rn = "Performance4";
  3890 +// break;
  3891 + case 5:
  3892 +// gen_op_dmtc0_performance5();
  3893 + rn = "Performance5";
  3894 +// break;
  3895 + case 6:
  3896 +// gen_op_dmtc0_performance6();
  3897 + rn = "Performance6";
  3898 +// break;
  3899 + case 7:
  3900 +// gen_op_dmtc0_performance7();
  3901 + rn = "Performance7";
  3902 +// break;
  3903 + default:
  3904 + goto die;
  3905 + }
  3906 + break;
  3907 + case 26:
  3908 + /* ignored */
  3909 + rn = "ECC";
  3910 + break;
  3911 + case 27:
  3912 + switch (sel) {
  3913 + case 0 ... 3:
  3914 + /* ignored */
  3915 + rn = "CacheErr";
  3916 + break;
  3917 + default:
  3918 + goto die;
  3919 + }
  3920 + break;
  3921 + case 28:
  3922 + switch (sel) {
  3923 + case 0:
  3924 + case 2:
  3925 + case 4:
  3926 + case 6:
  3927 + gen_op_mtc0_taglo();
  3928 + rn = "TagLo";
  3929 + break;
  3930 + case 1:
  3931 + case 3:
  3932 + case 5:
  3933 + case 7:
  3934 + gen_op_mtc0_datalo();
  3935 + rn = "DataLo";
  3936 + break;
  3937 + default:
  3938 + goto die;
  3939 + }
  3940 + break;
  3941 + case 29:
  3942 + switch (sel) {
  3943 + case 0:
  3944 + case 2:
  3945 + case 4:
  3946 + case 6:
  3947 + gen_op_mtc0_taghi();
  3948 + rn = "TagHi";
  3949 + break;
  3950 + case 1:
  3951 + case 3:
  3952 + case 5:
  3953 + case 7:
  3954 + gen_op_mtc0_datahi();
  3955 + rn = "DataHi";
  3956 + break;
  3957 + default:
  3958 + rn = "invalid sel";
  3959 + goto die;
  3960 + }
  3961 + break;
  3962 + case 30:
  3963 + switch (sel) {
  3964 + case 0:
  3965 + gen_op_dmtc0_errorepc();
  3966 + rn = "ErrorEPC";
  3967 + break;
  3968 + default:
  3969 + goto die;
  3970 + }
  3971 + break;
  3972 + case 31:
  3973 + switch (sel) {
  3974 + case 0:
  3975 + gen_op_mtc0_desave(); /* EJTAG support */
  3976 + rn = "DESAVE";
  3977 + break;
  3978 + default:
  3979 + goto die;
  3980 + }
  3981 + /* Stop translation as we may have switched the execution mode */
  3982 + ctx->bstate = BS_STOP;
  3983 + break;
  3984 + default:
  3985 + goto die;
  3986 + }
  3987 +#if defined MIPS_DEBUG_DISAS
  3988 + if (loglevel & CPU_LOG_TB_IN_ASM) {
  3989 + fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
  3990 + rn, reg, sel);
  3991 + }
  3992 +#endif
  3993 + return;
  3994 +
  3995 +die:
  3996 +#if defined MIPS_DEBUG_DISAS
  3997 + if (loglevel & CPU_LOG_TB_IN_ASM) {
  3998 + fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
  3999 + rn, reg, sel);
  4000 + }
  4001 +#endif
  4002 + generate_exception(ctx, EXCP_RI);
  4003 +}
  4004 +
2830 4005 static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
2831 4006 {
2832 4007 const char *opn = "unk";
... ... @@ -2854,7 +4029,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
2854 4029 break;
2855 4030 case OPC_MTC0:
2856 4031 /* If we get an exception, we want to restart at next instruction */
2857   - /* XXX: breaks for mtc in delay slot */
  4032 + /* XXX: breaks for mtc in delay slot */
2858 4033 ctx->pc += 4;
2859 4034 save_cpu_state(ctx, 1);
2860 4035 ctx->pc -= 4;
... ... @@ -2862,6 +4037,25 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
2862 4037 gen_mtc0(ctx, rd, ctx->opcode & 0x7);
2863 4038 opn = "mtc0";
2864 4039 break;
  4040 + case OPC_DMFC0:
  4041 + if (rt == 0) {
  4042 + /* Treat as NOP */
  4043 + return;
  4044 + }
  4045 + gen_dmfc0(ctx, rd, ctx->opcode & 0x7);
  4046 + gen_op_store_T0_gpr(rt);
  4047 + opn = "dmfc0";
  4048 + break;
  4049 + case OPC_DMTC0:
  4050 + /* If we get an exception, we want to restart at next instruction */
  4051 + /* XXX: breaks for dmtc in delay slot */
  4052 + ctx->pc += 4;
  4053 + save_cpu_state(ctx, 1);
  4054 + ctx->pc -= 4;
  4055 + GEN_LOAD_REG_TN(T0, rt);
  4056 + gen_dmtc0(ctx, rd, ctx->opcode & 0x7);
  4057 + opn = "dmtc0";
  4058 + break;
2865 4059 #if defined(MIPS_USES_R4K_TLB)
2866 4060 case OPC_TLBWI:
2867 4061 gen_op_tlbwi();
... ... @@ -3002,6 +4196,9 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
3002 4196 gen_op_ctc1();
3003 4197 opn = "ctc1";
3004 4198 break;
  4199 + case OPC_DMFC1:
  4200 + case OPC_DMTC1:
  4201 + /* Not implemented, fallthrough. */
3005 4202 default:
3006 4203 if (loglevel & CPU_LOG_TB_IN_ASM) {
3007 4204 fprintf(logfile, "Invalid CP1 opcode: %08x %03x %03x %03x\n",
... ... @@ -3703,6 +4900,10 @@ static void decode_opc (DisasContext *ctx)
3703 4900 case OPC_CFC1:
3704 4901 case OPC_MTC1:
3705 4902 case OPC_CTC1:
  4903 +#ifdef MIPS_HAS_MIPS64
  4904 + case OPC_DMFC1:
  4905 + case OPC_DMTC1:
  4906 +#endif
3706 4907 gen_cp1(ctx, op1, rt, rd);
3707 4908 break;
3708 4909 case OPC_BC1:
... ... @@ -4099,7 +5300,7 @@ void cpu_reset (CPUMIPSState *env)
4099 5300 }
4100 5301 env->PC = (int32_t)0xBFC00000;
4101 5302 #if defined (MIPS_USES_R4K_TLB)
4102   - env->CP0_random = MIPS_TLB_NB - 1;
  5303 + env->CP0_Random = MIPS_TLB_NB - 1;
4103 5304 env->tlb_in_use = MIPS_TLB_NB;
4104 5305 #endif
4105 5306 env->CP0_Wired = 0;
... ...