gwj / at91sam9263 · Commits

Commit a6763a588127d8b0f7e64312e9153c6c6bae822f

Authored by ths
1 parent 204a1b8d

Fix MIPS64 address computation specialcase, by Aurelien Jarno. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2793 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 18 additions and 2 deletions
target-mips/op.c
  View file @a6763a5
... ... @@ -289,6 +289,22 @@ void op_store_LO (void)
289 289 #undef MEMSUFFIX
290 290 #endif
291 291  
  292 +/* Addresses computation */
  293 +void op_addr_add (void)
  294 +{
  295 +/* For compatibility with 32-bit code, data reference in user mode
  296 + with Status_UX = 0 should be casted to 32-bit and sign extended.
  297 + See the MIPS64 PRA manual, section 4.10. */
  298 +#ifdef TARGET_MIPS64
  299 + if ((env->CP0_Status & (1 << CP0St_UM)) &&
  300 + !(env->CP0_Status & (1 << CP0St_UX)))
  301 + T0 = (int64_t)(int32_t)(T0 + T1);
  302 + else
  303 +#endif
  304 + T0 += T1;
  305 + RETURN();
  306 +}
  307 +
292 308 /* Arithmetic */
293 309 void op_add (void)
294 310 {
... ...
target-mips/translate.c
  View file @a6763a5
... ... @@ -719,7 +719,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
719 719 } else {
720 720 gen_op_load_gpr_T0(base);
721 721 gen_op_set_T1(offset);
722   - gen_op_add();
  722 + gen_op_addr_add();
723 723 }
724 724 /* Don't do NOP if destination is zero: we must perform the actual
725 725 * memory access
... ... @@ -868,7 +868,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
868 868 } else {
869 869 gen_op_load_gpr_T0(base);
870 870 gen_op_set_T1(offset);
871   - gen_op_add();
  871 + gen_op_addr_add();
872 872 }
873 873 /* Don't do NOP if destination is zero: we must perform the actual
874 874 * memory access
... ...