gwj / at91sam9263 · Commits

Commit 534ce69ff05bee2448419f9cad796d6511bc1f9a

Authored by ths
1 parent e9df014c

More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may 

end up empty for 32bit mips, which dyngen trips over.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2648 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 10 additions and 10 deletions
target-mips/op.c
  View file @534ce69
... ... @@ -1293,7 +1293,7 @@ void op_mtc0_entrylo1 (void)
1293 1293  
1294 1294 void op_mtc0_context (void)
1295 1295 {
1296   - env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & ~0x007FFFFF);
  1296 + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1297 1297 RETURN();
1298 1298 }
1299 1299  
... ... @@ -1458,12 +1458,6 @@ void op_mtc0_watchhi0 (void)
1458 1458 RETURN();
1459 1459 }
1460 1460  
1461   -void op_mtc0_xcontext (void)
1462   -{
1463   - env->CP0_XContext = (int32_t)T0; /* XXX */
1464   - RETURN();
1465   -}
1466   -
1467 1461 void op_mtc0_framemask (void)
1468 1462 {
1469 1463 env->CP0_Framemask = T0; /* XXX */
... ... @@ -1528,6 +1522,7 @@ void op_mtc0_desave (void)
1528 1522 RETURN();
1529 1523 }
1530 1524  
  1525 +#ifdef TARGET_MIPS64
1531 1526 void op_dmfc0_entrylo0 (void)
1532 1527 {
1533 1528 T0 = env->CP0_EntryLo0;
... ... @@ -1612,7 +1607,7 @@ void op_dmtc0_entrylo1 (void)
1612 1607  
1613 1608 void op_dmtc0_context (void)
1614 1609 {
1615   - env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
  1610 + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1616 1611 RETURN();
1617 1612 }
1618 1613  
... ... @@ -1632,7 +1627,7 @@ void op_dmtc0_watchlo0 (void)
1632 1627  
1633 1628 void op_dmtc0_xcontext (void)
1634 1629 {
1635   - env->CP0_XContext = T0; /* XXX */
  1630 + env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff);
1636 1631 RETURN();
1637 1632 }
1638 1633  
... ... @@ -1647,6 +1642,7 @@ void op_dmtc0_errorepc (void)
1647 1642 env->CP0_ErrorEPC = T0;
1648 1643 RETURN();
1649 1644 }
  1645 +#endif /* TARGET_MIPS64 */
1650 1646  
1651 1647 #if 0
1652 1648 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
... ...
target-mips/translate.c
  View file @534ce69
... ... @@ -2750,7 +2750,7 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
2750 2750 switch (sel) {
2751 2751 case 0:
2752 2752 /* 64 bit MMU only */
2753   - gen_op_mtc0_xcontext();
  2753 + /* Nothing writable in lower 32 bits */
2754 2754 rn = "XContext";
2755 2755 break;
2756 2756 default:
... ... @@ -2946,6 +2946,7 @@ die:
2946 2946 generate_exception(ctx, EXCP_RI);
2947 2947 }
2948 2948  
  2949 +#ifdef TARGET_MIPS64
2949 2950 static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
2950 2951 {
2951 2952 const char *rn = "invalid";
... ... @@ -4120,6 +4121,7 @@ die:
4120 4121 #endif
4121 4122 generate_exception(ctx, EXCP_RI);
4122 4123 }
  4124 +#endif /* TARGET_MIPS64 */
4123 4125  
4124 4126 static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
4125 4127 {
... ... @@ -4140,6 +4142,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
4140 4142 gen_mtc0(ctx, rd, ctx->opcode & 0x7);
4141 4143 opn = "mtc0";
4142 4144 break;
  4145 +#ifdef TARGET_MIPS64
4143 4146 case OPC_DMFC0:
4144 4147 if (rt == 0) {
4145 4148 /* Treat as NOP */
... ... @@ -4154,6 +4157,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
4154 4157 gen_dmtc0(ctx, rd, ctx->opcode & 0x7);
4155 4158 opn = "dmtc0";
4156 4159 break;
  4160 +#endif
4157 4161 #if defined(MIPS_USES_R4K_TLB)
4158 4162 case OPC_TLBWI:
4159 4163 gen_op_tlbwi();
... ...