gwj / at91sam9263 · Commits

Commit f1b0aa5de7f48650aa6260d5dfb8ece1899e286c

Authored by ths
1 parent 6b4d2ba1

Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2819 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 72 additions and 120 deletions
target-mips/op.c
  View file @f1b0aa5
... ... @@ -1260,7 +1260,7 @@ void op_mtc0_entrylo0 (void)
1260 1260 {
1261 1261 /* Large physaddr not implemented */
1262 1262 /* 1k pages not implemented */
1263   - env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
  1263 + env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1264 1264 RETURN();
1265 1265 }
1266 1266  
... ... @@ -1268,7 +1268,7 @@ void op_mtc0_entrylo1 (void)
1268 1268 {
1269 1269 /* Large physaddr not implemented */
1270 1270 /* 1k pages not implemented */
1271   - env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
  1271 + env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1272 1272 RETURN();
1273 1273 }
1274 1274  
... ... @@ -1338,9 +1338,9 @@ void op_mtc0_status (void)
1338 1338 uint32_t val, old;
1339 1339 uint32_t mask = env->Status_rw_bitmask;
1340 1340  
1341   - /* No reverse endianness, no MDMX/DSP, no 64bit ops,
1342   - no 64bit addressing implemented. */
1343   - val = (int32_t)T0 & mask;
  1341 + /* No reverse endianness, no MDMX/DSP, no 64bit ops
  1342 + implemented. */
  1343 + val = T0 & mask;
1344 1344 old = env->CP0_Status;
1345 1345 if (!(val & (1 << CP0St_EXL)) &&
1346 1346 !(val & (1 << CP0St_ERL)) &&
... ... @@ -1395,7 +1395,7 @@ void op_mtc0_cause (void)
1395 1395  
1396 1396 void op_mtc0_epc (void)
1397 1397 {
1398   - env->CP0_EPC = (int32_t)T0;
  1398 + env->CP0_EPC = T0;
1399 1399 RETURN();
1400 1400 }
1401 1401  
... ... @@ -1424,7 +1424,7 @@ void op_mtc0_watchlo0 (void)
1424 1424 {
1425 1425 /* Watch exceptions for instructions, data loads, data stores
1426 1426 not implemented. */
1427   - env->CP0_WatchLo = (int32_t)(T0 & ~0x7);
  1427 + env->CP0_WatchLo = (T0 & ~0x7);
1428 1428 RETURN();
1429 1429 }
1430 1430  
... ... @@ -1453,7 +1453,7 @@ void op_mtc0_debug (void)
1453 1453  
1454 1454 void op_mtc0_depc (void)
1455 1455 {
1456   - env->CP0_DEPC = (int32_t)T0;
  1456 + env->CP0_DEPC = T0;
1457 1457 RETURN();
1458 1458 }
1459 1459  
... ... @@ -1489,7 +1489,7 @@ void op_mtc0_datahi (void)
1489 1489  
1490 1490 void op_mtc0_errorepc (void)
1491 1491 {
1492   - env->CP0_ErrorEPC = (int32_t)T0;
  1492 + env->CP0_ErrorEPC = T0;
1493 1493 RETURN();
1494 1494 }
1495 1495  
... ... @@ -1500,6 +1500,12 @@ void op_mtc0_desave (void)
1500 1500 }
1501 1501  
1502 1502 #ifdef TARGET_MIPS64
  1503 +void op_mtc0_xcontext (void)
  1504 +{
  1505 + env->CP0_XContext = (env->CP0_XContext & 0x1ffffffffULL) | (T0 & ~0x1ffffffffULL);
  1506 + RETURN();
  1507 +}
  1508 +
1503 1509 void op_dmfc0_entrylo0 (void)
1504 1510 {
1505 1511 T0 = env->CP0_EntryLo0;
... ... @@ -1565,60 +1571,6 @@ void op_dmfc0_errorepc (void)
1565 1571 T0 = env->CP0_ErrorEPC;
1566 1572 RETURN();
1567 1573 }
1568   -
1569   -void op_dmtc0_entrylo0 (void)
1570   -{
1571   - /* Large physaddr not implemented */
1572   - /* 1k pages not implemented */
1573   - env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1574   - RETURN();
1575   -}
1576   -
1577   -void op_dmtc0_entrylo1 (void)
1578   -{
1579   - /* Large physaddr not implemented */
1580   - /* 1k pages not implemented */
1581   - env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1582   - RETURN();
1583   -}
1584   -
1585   -void op_dmtc0_context (void)
1586   -{
1587   - env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1588   - RETURN();
1589   -}
1590   -
1591   -void op_dmtc0_epc (void)
1592   -{
1593   - env->CP0_EPC = T0;
1594   - RETURN();
1595   -}
1596   -
1597   -void op_dmtc0_watchlo0 (void)
1598   -{
1599   - /* Watch exceptions for instructions, data loads, data stores
1600   - not implemented. */
1601   - env->CP0_WatchLo = T0 & ~0x7;
1602   - RETURN();
1603   -}
1604   -
1605   -void op_dmtc0_xcontext (void)
1606   -{
1607   - env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff);
1608   - RETURN();
1609   -}
1610   -
1611   -void op_dmtc0_depc (void)
1612   -{
1613   - env->CP0_DEPC = T0;
1614   - RETURN();
1615   -}
1616   -
1617   -void op_dmtc0_errorepc (void)
1618   -{
1619   - env->CP0_ErrorEPC = T0;
1620   - RETURN();
1621   -}
1622 1574 #endif /* TARGET_MIPS64 */
1623 1575  
1624 1576 /* CP1 functions */
... ...
target-mips/translate.c
  View file @f1b0aa5
... ... @@ -2790,7 +2790,7 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
2790 2790 switch (sel) {
2791 2791 case 0:
2792 2792 #ifdef TARGET_MIPS64
2793   - /* Nothing writable in lower 32 bits */
  2793 + gen_op_mtc0_xcontext();
2794 2794 rn = "XContext";
2795 2795 break;
2796 2796 #endif
... ... @@ -3583,15 +3583,15 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3583 3583 rn = "Index";
3584 3584 break;
3585 3585 case 1:
3586   -// gen_op_dmtc0_mvpcontrol(); /* MT ASE */
  3586 +// gen_op_mtc0_mvpcontrol(); /* MT ASE */
3587 3587 rn = "MVPControl";
3588 3588 // break;
3589 3589 case 2:
3590   -// gen_op_dmtc0_mvpconf0(); /* MT ASE */
  3590 +// gen_op_mtc0_mvpconf0(); /* MT ASE */
3591 3591 rn = "MVPConf0";
3592 3592 // break;
3593 3593 case 3:
3594   -// gen_op_dmtc0_mvpconf1(); /* MT ASE */
  3594 +// gen_op_mtc0_mvpconf1(); /* MT ASE */
3595 3595 rn = "MVPConf1";
3596 3596 // break;
3597 3597 default:
... ... @@ -3605,31 +3605,31 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3605 3605 rn = "Random";
3606 3606 break;
3607 3607 case 1:
3608   -// gen_op_dmtc0_vpecontrol(); /* MT ASE */
  3608 +// gen_op_mtc0_vpecontrol(); /* MT ASE */
3609 3609 rn = "VPEControl";
3610 3610 // break;
3611 3611 case 2:
3612   -// gen_op_dmtc0_vpeconf0(); /* MT ASE */
  3612 +// gen_op_mtc0_vpeconf0(); /* MT ASE */
3613 3613 rn = "VPEConf0";
3614 3614 // break;
3615 3615 case 3:
3616   -// gen_op_dmtc0_vpeconf1(); /* MT ASE */
  3616 +// gen_op_mtc0_vpeconf1(); /* MT ASE */
3617 3617 rn = "VPEConf1";
3618 3618 // break;
3619 3619 case 4:
3620   -// gen_op_dmtc0_YQMask(); /* MT ASE */
  3620 +// gen_op_mtc0_YQMask(); /* MT ASE */
3621 3621 rn = "YQMask";
3622 3622 // break;
3623 3623 case 5:
3624   -// gen_op_dmtc0_vpeschedule(); /* MT ASE */
  3624 +// gen_op_mtc0_vpeschedule(); /* MT ASE */
3625 3625 rn = "VPESchedule";
3626 3626 // break;
3627 3627 case 6:
3628   -// gen_op_dmtc0_vpeschefback(); /* MT ASE */
  3628 +// gen_op_mtc0_vpeschefback(); /* MT ASE */
3629 3629 rn = "VPEScheFBack";
3630 3630 // break;
3631 3631 case 7:
3632   -// gen_op_dmtc0_vpeopt(); /* MT ASE */
  3632 +// gen_op_mtc0_vpeopt(); /* MT ASE */
3633 3633 rn = "VPEOpt";
3634 3634 // break;
3635 3635 default:
... ... @@ -3639,35 +3639,35 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3639 3639 case 2:
3640 3640 switch (sel) {
3641 3641 case 0:
3642   - gen_op_dmtc0_entrylo0();
  3642 + gen_op_mtc0_entrylo0();
3643 3643 rn = "EntryLo0";
3644 3644 break;
3645 3645 case 1:
3646   -// gen_op_dmtc0_tcstatus(); /* MT ASE */
  3646 +// gen_op_mtc0_tcstatus(); /* MT ASE */
3647 3647 rn = "TCStatus";
3648 3648 // break;
3649 3649 case 2:
3650   -// gen_op_dmtc0_tcbind(); /* MT ASE */
  3650 +// gen_op_mtc0_tcbind(); /* MT ASE */
3651 3651 rn = "TCBind";
3652 3652 // break;
3653 3653 case 3:
3654   -// gen_op_dmtc0_tcrestart(); /* MT ASE */
  3654 +// gen_op_mtc0_tcrestart(); /* MT ASE */
3655 3655 rn = "TCRestart";
3656 3656 // break;
3657 3657 case 4:
3658   -// gen_op_dmtc0_tchalt(); /* MT ASE */
  3658 +// gen_op_mtc0_tchalt(); /* MT ASE */
3659 3659 rn = "TCHalt";
3660 3660 // break;
3661 3661 case 5:
3662   -// gen_op_dmtc0_tccontext(); /* MT ASE */
  3662 +// gen_op_mtc0_tccontext(); /* MT ASE */
3663 3663 rn = "TCContext";
3664 3664 // break;
3665 3665 case 6:
3666   -// gen_op_dmtc0_tcschedule(); /* MT ASE */
  3666 +// gen_op_mtc0_tcschedule(); /* MT ASE */
3667 3667 rn = "TCSchedule";
3668 3668 // break;
3669 3669 case 7:
3670   -// gen_op_dmtc0_tcschefback(); /* MT ASE */
  3670 +// gen_op_mtc0_tcschefback(); /* MT ASE */
3671 3671 rn = "TCScheFBack";
3672 3672 // break;
3673 3673 default:
... ... @@ -3677,7 +3677,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3677 3677 case 3:
3678 3678 switch (sel) {
3679 3679 case 0:
3680   - gen_op_dmtc0_entrylo1();
  3680 + gen_op_mtc0_entrylo1();
3681 3681 rn = "EntryLo1";
3682 3682 break;
3683 3683 default:
... ... @@ -3687,11 +3687,11 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3687 3687 case 4:
3688 3688 switch (sel) {
3689 3689 case 0:
3690   - gen_op_dmtc0_context();
  3690 + gen_op_mtc0_context();
3691 3691 rn = "Context";
3692 3692 break;
3693 3693 case 1:
3694   -// gen_op_dmtc0_contextconfig(); /* SmartMIPS ASE */
  3694 +// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
3695 3695 rn = "ContextConfig";
3696 3696 // break;
3697 3697 default:
... ... @@ -3719,23 +3719,23 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3719 3719 rn = "Wired";
3720 3720 break;
3721 3721 case 1:
3722   -// gen_op_dmtc0_srsconf0(); /* shadow registers */
  3722 +// gen_op_mtc0_srsconf0(); /* shadow registers */
3723 3723 rn = "SRSConf0";
3724 3724 // break;
3725 3725 case 2:
3726   -// gen_op_dmtc0_srsconf1(); /* shadow registers */
  3726 +// gen_op_mtc0_srsconf1(); /* shadow registers */
3727 3727 rn = "SRSConf1";
3728 3728 // break;
3729 3729 case 3:
3730   -// gen_op_dmtc0_srsconf2(); /* shadow registers */
  3730 +// gen_op_mtc0_srsconf2(); /* shadow registers */
3731 3731 rn = "SRSConf2";
3732 3732 // break;
3733 3733 case 4:
3734   -// gen_op_dmtc0_srsconf3(); /* shadow registers */
  3734 +// gen_op_mtc0_srsconf3(); /* shadow registers */
3735 3735 rn = "SRSConf3";
3736 3736 // break;
3737 3737 case 5:
3738   -// gen_op_dmtc0_srsconf4(); /* shadow registers */
  3738 +// gen_op_mtc0_srsconf4(); /* shadow registers */
3739 3739 rn = "SRSConf4";
3740 3740 // break;
3741 3741 default:
... ... @@ -3831,7 +3831,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3831 3831 case 14:
3832 3832 switch (sel) {
3833 3833 case 0:
3834   - gen_op_dmtc0_epc();
  3834 + gen_op_mtc0_epc();
3835 3835 rn = "EPC";
3836 3836 break;
3837 3837 default:
... ... @@ -3893,35 +3893,35 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3893 3893 case 18:
3894 3894 switch (sel) {
3895 3895 case 0:
3896   - gen_op_dmtc0_watchlo0();
  3896 + gen_op_mtc0_watchlo0();
3897 3897 rn = "WatchLo";
3898 3898 break;
3899 3899 case 1:
3900   -// gen_op_dmtc0_watchlo1();
  3900 +// gen_op_mtc0_watchlo1();
3901 3901 rn = "WatchLo1";
3902 3902 // break;
3903 3903 case 2:
3904   -// gen_op_dmtc0_watchlo2();
  3904 +// gen_op_mtc0_watchlo2();
3905 3905 rn = "WatchLo2";
3906 3906 // break;
3907 3907 case 3:
3908   -// gen_op_dmtc0_watchlo3();
  3908 +// gen_op_mtc0_watchlo3();
3909 3909 rn = "WatchLo3";
3910 3910 // break;
3911 3911 case 4:
3912   -// gen_op_dmtc0_watchlo4();
  3912 +// gen_op_mtc0_watchlo4();
3913 3913 rn = "WatchLo4";
3914 3914 // break;
3915 3915 case 5:
3916   -// gen_op_dmtc0_watchlo5();
  3916 +// gen_op_mtc0_watchlo5();
3917 3917 rn = "WatchLo5";
3918 3918 // break;
3919 3919 case 6:
3920   -// gen_op_dmtc0_watchlo6();
  3920 +// gen_op_mtc0_watchlo6();
3921 3921 rn = "WatchLo6";
3922 3922 // break;
3923 3923 case 7:
3924   -// gen_op_dmtc0_watchlo7();
  3924 +// gen_op_mtc0_watchlo7();
3925 3925 rn = "WatchLo7";
3926 3926 // break;
3927 3927 default:
... ... @@ -3935,31 +3935,31 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3935 3935 rn = "WatchHi";
3936 3936 break;
3937 3937 case 1:
3938   -// gen_op_dmtc0_watchhi1();
  3938 +// gen_op_mtc0_watchhi1();
3939 3939 rn = "WatchHi1";
3940 3940 // break;
3941 3941 case 2:
3942   -// gen_op_dmtc0_watchhi2();
  3942 +// gen_op_mtc0_watchhi2();
3943 3943 rn = "WatchHi2";
3944 3944 // break;
3945 3945 case 3:
3946   -// gen_op_dmtc0_watchhi3();
  3946 +// gen_op_mtc0_watchhi3();
3947 3947 rn = "WatchHi3";
3948 3948 // break;
3949 3949 case 4:
3950   -// gen_op_dmtc0_watchhi4();
  3950 +// gen_op_mtc0_watchhi4();
3951 3951 rn = "WatchHi4";
3952 3952 // break;
3953 3953 case 5:
3954   -// gen_op_dmtc0_watchhi5();
  3954 +// gen_op_mtc0_watchhi5();
3955 3955 rn = "WatchHi5";
3956 3956 // break;
3957 3957 case 6:
3958   -// gen_op_dmtc0_watchhi6();
  3958 +// gen_op_mtc0_watchhi6();
3959 3959 rn = "WatchHi6";
3960 3960 // break;
3961 3961 case 7:
3962   -// gen_op_dmtc0_watchhi7();
  3962 +// gen_op_mtc0_watchhi7();
3963 3963 rn = "WatchHi7";
3964 3964 // break;
3965 3965 default:
... ... @@ -3970,7 +3970,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3970 3970 switch (sel) {
3971 3971 case 0:
3972 3972 #ifdef TARGET_MIPS64
3973   - gen_op_dmtc0_xcontext();
  3973 + gen_op_mtc0_xcontext();
3974 3974 rn = "XContext";
3975 3975 break;
3976 3976 #endif
... ... @@ -4000,19 +4000,19 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
4000 4000 rn = "Debug";
4001 4001 break;
4002 4002 case 1:
4003   -// gen_op_dmtc0_tracecontrol(); /* PDtrace support */
  4003 +// gen_op_mtc0_tracecontrol(); /* PDtrace support */
4004 4004 rn = "TraceControl";
4005 4005 // break;
4006 4006 case 2:
4007   -// gen_op_dmtc0_tracecontrol2(); /* PDtrace support */
  4007 +// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
4008 4008 rn = "TraceControl2";
4009 4009 // break;
4010 4010 case 3:
4011   -// gen_op_dmtc0_usertracedata(); /* PDtrace support */
  4011 +// gen_op_mtc0_usertracedata(); /* PDtrace support */
4012 4012 rn = "UserTraceData";
4013 4013 // break;
4014 4014 case 4:
4015   -// gen_op_dmtc0_debug(); /* PDtrace support */
  4015 +// gen_op_mtc0_debug(); /* PDtrace support */
4016 4016 rn = "TraceBPC";
4017 4017 // break;
4018 4018 default:
... ... @@ -4024,7 +4024,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
4024 4024 case 24:
4025 4025 switch (sel) {
4026 4026 case 0:
4027   - gen_op_dmtc0_depc(); /* EJTAG support */
  4027 + gen_op_mtc0_depc(); /* EJTAG support */
4028 4028 rn = "DEPC";
4029 4029 break;
4030 4030 default:
... ... @@ -4038,31 +4038,31 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
4038 4038 rn = "Performance0";
4039 4039 break;
4040 4040 case 1:
4041   -// gen_op_dmtc0_performance1();
  4041 +// gen_op_mtc0_performance1();
4042 4042 rn = "Performance1";
4043 4043 // break;
4044 4044 case 2:
4045   -// gen_op_dmtc0_performance2();
  4045 +// gen_op_mtc0_performance2();
4046 4046 rn = "Performance2";
4047 4047 // break;
4048 4048 case 3:
4049   -// gen_op_dmtc0_performance3();
  4049 +// gen_op_mtc0_performance3();
4050 4050 rn = "Performance3";
4051 4051 // break;
4052 4052 case 4:
4053   -// gen_op_dmtc0_performance4();
  4053 +// gen_op_mtc0_performance4();
4054 4054 rn = "Performance4";
4055 4055 // break;
4056 4056 case 5:
4057   -// gen_op_dmtc0_performance5();
  4057 +// gen_op_mtc0_performance5();
4058 4058 rn = "Performance5";
4059 4059 // break;
4060 4060 case 6:
4061   -// gen_op_dmtc0_performance6();
  4061 +// gen_op_mtc0_performance6();
4062 4062 rn = "Performance6";
4063 4063 // break;
4064 4064 case 7:
4065   -// gen_op_dmtc0_performance7();
  4065 +// gen_op_mtc0_performance7();
4066 4066 rn = "Performance7";
4067 4067 // break;
4068 4068 default:
... ... @@ -4127,7 +4127,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
4127 4127 case 30:
4128 4128 switch (sel) {
4129 4129 case 0:
4130   - gen_op_dmtc0_errorepc();
  4130 + gen_op_mtc0_errorepc();
4131 4131 rn = "ErrorEPC";
4132 4132 break;
4133 4133 default:
... ...