gwj / at91sam9263 · Commits

Commit e58c8ba5f6b1bd9af00cf5fcebce4bdba0f0aabb

Authored by ths
1 parent 5425a216

Another fix for CP0 Cause register handling. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2658 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 2 additions and 2 deletions
target-mips/helper.c
  View file @e58c8ba
... ... @@ -403,7 +403,7 @@ void do_interrupt (CPUState *env)
403 403 env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
404 404 }
405 405 env->PC += offset;
406   - env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
  406 + env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
407 407 break;
408 408 default:
409 409 if (logfile) {
... ...
target-mips/op.c
  View file @e58c8ba
... ... @@ -1401,7 +1401,7 @@ void op_mtc0_cause (void)
1401 1401 if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1402 1402 mask |= 1 << CP0Ca_DC;
1403 1403  
1404   - env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask);
  1404 + env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
1405 1405  
1406 1406 /* Handle the software interrupt as an hardware one, as they
1407 1407 are very similar */
... ...