gwj / at91sam9263 · Commits

Commit b29a0341d7ed7e7df4bf77a41db8e614f1ddb645

Authored by ths
1 parent 4de9b249

EBase is limited to KSEG0/KSEG1 even on 64bit CPUs. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2351 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 6 additions and 21 deletions
target-mips/cpu.h
  View file @b29a034
... ... @@ -162,7 +162,7 @@ struct CPUMIPSState {
162 162 #define CP0Ca_EC 2
163 163 target_ulong CP0_EPC;
164 164 int32_t CP0_PRid;
165   - target_ulong CP0_EBase;
  165 + int32_t CP0_EBase;
166 166 int32_t CP0_Config0;
167 167 #define CP0C0_M 31
168 168 #define CP0C0_K23 28
... ...
target-mips/op.c
  View file @b29a034
... ... @@ -1158,7 +1158,7 @@ void op_mfc0_prid (void)
1158 1158  
1159 1159 void op_mfc0_ebase (void)
1160 1160 {
1161   - T0 = (int32_t)env->CP0_EBase;
  1161 + T0 = env->CP0_EBase;
1162 1162 RETURN();
1163 1163 }
1164 1164  
... ... @@ -1423,7 +1423,7 @@ void op_mtc0_ebase (void)
1423 1423 {
1424 1424 /* vectored interrupts not implemented */
1425 1425 /* Multi-CPU not implemented */
1426   - env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
  1426 + env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1427 1427 RETURN();
1428 1428 }
1429 1429  
... ... @@ -1563,12 +1563,6 @@ void op_dmfc0_epc (void)
1563 1563 RETURN();
1564 1564 }
1565 1565  
1566   -void op_dmfc0_ebase (void)
1567   -{
1568   - T0 = env->CP0_EBase;
1569   - RETURN();
1570   -}
1571   -
1572 1566 void op_dmfc0_lladdr (void)
1573 1567 {
1574 1568 T0 = env->CP0_LLAddr >> 4;
... ... @@ -1627,15 +1621,6 @@ void op_dmtc0_epc (void)
1627 1621 RETURN();
1628 1622 }
1629 1623  
1630   -void op_dmtc0_ebase (void)
1631   -{
1632   - /* vectored interrupts not implemented */
1633   - /* Multi-CPU not implemented */
1634   - /* XXX: 64bit addressing broken */
1635   - env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
1636   - RETURN();
1637   -}
1638   -
1639 1624 void op_dmtc0_watchlo0 (void)
1640 1625 {
1641 1626 env->CP0_WatchLo = T0;
... ...
target-mips/translate.c
  View file @b29a034
... ... @@ -3099,7 +3099,7 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
3099 3099 rn = "PRid";
3100 3100 break;
3101 3101 case 1:
3102   - gen_op_dmfc0_ebase();
  3102 + gen_op_mfc0_ebase();
3103 3103 rn = "EBase";
3104 3104 break;
3105 3105 default:
... ... @@ -3683,7 +3683,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3683 3683 rn = "PRid";
3684 3684 break;
3685 3685 case 1:
3686   - gen_op_dmtc0_ebase();
  3686 + gen_op_mtc0_ebase();
3687 3687 rn = "EBase";
3688 3688 break;
3689 3689 default:
... ... @@ -5305,7 +5305,7 @@ void cpu_reset (CPUMIPSState *env)
5305 5305 #endif
5306 5306 env->CP0_Wired = 0;
5307 5307 /* SMP not implemented */
5308   - env->CP0_EBase = (int32_t)0x80000000;
  5308 + env->CP0_EBase = 0x80000000;
5309 5309 env->CP0_Config0 = MIPS_CONFIG0;
5310 5310 env->CP0_Config1 = MIPS_CONFIG1;
5311 5311 env->CP0_Config2 = MIPS_CONFIG2;
... ...