gwj / at91sam9263 · Files

/*

 * QEMU generic PowerPC hardware System Emulator

 *

 * Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "ppc.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "nvram.h"

#include "qemu-log.h"

//#define PPC_DEBUG_IRQ

//#define PPC_DEBUG_TB

#ifdef PPC_DEBUG_IRQ

#  define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)

#else
#  define LOG_IRQ(...) do { } while (0)
#endif


#ifdef PPC_DEBUG_TB

#  define LOG_TB(...) qemu_log(__VA_ARGS__)

#else
#  define LOG_TB(...) do { } while (0)
#endif

static void cpu_ppc_tb_stop (CPUState *env);
static void cpu_ppc_tb_start (CPUState *env);

static void ppc_set_irq (CPUState *env, int n_IRQ, int level)

{
    if (level) {
        env->pending_interrupts |= 1 << n_IRQ;
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
    } else {
        env->pending_interrupts &= ~(1 << n_IRQ);
        if (env->pending_interrupts == 0)
            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
    }

    LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32

                "req %08x\n", __func__, env, n_IRQ, level,

                env->pending_interrupts, env->interrupt_request);

}

/* PowerPC 6xx / 7xx internal IRQ controller */
static void ppc6xx_set_irq (void *opaque, int pin, int level)

{

    CPUState *env = opaque;
    int cur_level;

    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,

                env, pin, level);

    cur_level = (env->irq_input_state >> pin) & 1;
    /* Don't generate spurious events */

    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {

        switch (pin) {

        case PPC6xx_INPUT_TBEN:
            /* Level sensitive - active high */

            LOG_IRQ("%s: %s the time base\n",

                        __func__, level ? "start" : "stop");
            if (level) {
                cpu_ppc_tb_start(env);
            } else {
                cpu_ppc_tb_stop(env);
            }

        case PPC6xx_INPUT_INT:
            /* Level sensitive - active high */

            LOG_IRQ("%s: set the external IRQ state to %d\n",

                        __func__, level);

            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
            break;

        case PPC6xx_INPUT_SMI:

            /* Level sensitive - active high */

            LOG_IRQ("%s: set the SMI IRQ state to %d\n",

                        __func__, level);

            ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
            break;

        case PPC6xx_INPUT_MCP:

            /* Negative edge sensitive */
            /* XXX: TODO: actual reaction may depends on HID0 status
             *            603/604/740/750: check HID0[EMCP]
             */
            if (cur_level == 1 && level == 0) {

                LOG_IRQ("%s: raise machine check state\n",

                            __func__);

                ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
            }
            break;

        case PPC6xx_INPUT_CKSTP_IN:

            /* Level sensitive - active low */
            /* XXX: TODO: relay the signal to CKSTP_OUT pin */

            /* XXX: Note that the only way to restart the CPU is to reset it */

            if (level) {

                LOG_IRQ("%s: stop the CPU\n", __func__);

                env->halted = 1;
            }
            break;

        case PPC6xx_INPUT_HRESET:

            /* Level sensitive - active low */
            if (level) {

                LOG_IRQ("%s: reset the CPU\n", __func__);

                env->interrupt_request |= CPU_INTERRUPT_EXITTB;
                /* XXX: TOFIX */
#if 0
                cpu_ppc_reset(env);
#else
                qemu_system_reset_request();

#endif
            }
            break;

        case PPC6xx_INPUT_SRESET:

            LOG_IRQ("%s: set the RESET IRQ state to %d\n",

                        __func__, level);

            ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
            break;
        default:
            /* Unknown pin - do nothing */

            LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);

            return;
        }
        if (level)
            env->irq_input_state |= 1 << pin;
        else
            env->irq_input_state &= ~(1 << pin);

    }
}

void ppc6xx_irq_init (CPUState *env)

{

    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
                                                  PPC6xx_INPUT_NB);

}

#if defined(TARGET_PPC64)

/* PowerPC 970 internal IRQ controller */
static void ppc970_set_irq (void *opaque, int pin, int level)
{
    CPUState *env = opaque;
    int cur_level;

    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,

                env, pin, level);
    cur_level = (env->irq_input_state >> pin) & 1;
    /* Don't generate spurious events */
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
        switch (pin) {
        case PPC970_INPUT_INT:
            /* Level sensitive - active high */

            LOG_IRQ("%s: set the external IRQ state to %d\n",

                        __func__, level);
            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
            break;
        case PPC970_INPUT_THINT:
            /* Level sensitive - active high */

            LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,

                        level);
            ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
            break;
        case PPC970_INPUT_MCP:
            /* Negative edge sensitive */
            /* XXX: TODO: actual reaction may depends on HID0 status
             *            603/604/740/750: check HID0[EMCP]
             */
            if (cur_level == 1 && level == 0) {

                LOG_IRQ("%s: raise machine check state\n",

                            __func__);
                ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
            }
            break;
        case PPC970_INPUT_CKSTP:
            /* Level sensitive - active low */
            /* XXX: TODO: relay the signal to CKSTP_OUT pin */
            if (level) {

                LOG_IRQ("%s: stop the CPU\n", __func__);

                env->halted = 1;
            } else {

                LOG_IRQ("%s: restart the CPU\n", __func__);

                env->halted = 0;
            }
            break;
        case PPC970_INPUT_HRESET:
            /* Level sensitive - active low */
            if (level) {
#if 0 // XXX: TOFIX

                LOG_IRQ("%s: reset the CPU\n", __func__);

                cpu_reset(env);
#endif
            }
            break;
        case PPC970_INPUT_SRESET:

            LOG_IRQ("%s: set the RESET IRQ state to %d\n",

                        __func__, level);
            ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
            break;
        case PPC970_INPUT_TBEN:

            LOG_IRQ("%s: set the TBEN state to %d\n", __func__,

                        level);
            /* XXX: TODO */
            break;
        default:
            /* Unknown pin - do nothing */

            LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);

            return;
        }
        if (level)
            env->irq_input_state |= 1 << pin;
        else
            env->irq_input_state &= ~(1 << pin);
    }
}

void ppc970_irq_init (CPUState *env)
{

    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
                                                  PPC970_INPUT_NB);

}

#endif /* defined(TARGET_PPC64) */

/* PowerPC 40x internal IRQ controller */
static void ppc40x_set_irq (void *opaque, int pin, int level)

{
    CPUState *env = opaque;
    int cur_level;

    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,

                env, pin, level);

    cur_level = (env->irq_input_state >> pin) & 1;
    /* Don't generate spurious events */
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
        switch (pin) {

        case PPC40x_INPUT_RESET_SYS:

            if (level) {

                LOG_IRQ("%s: reset the PowerPC system\n",

                            __func__);
                ppc40x_system_reset(env);
            }
            break;

        case PPC40x_INPUT_RESET_CHIP:

            if (level) {

                LOG_IRQ("%s: reset the PowerPC chip\n", __func__);

                ppc40x_chip_reset(env);
            }
            break;

        case PPC40x_INPUT_RESET_CORE:

            /* XXX: TODO: update DBSR[MRR] */
            if (level) {

                LOG_IRQ("%s: reset the PowerPC core\n", __func__);

                ppc40x_core_reset(env);

            }
            break;

        case PPC40x_INPUT_CINT:

            /* Level sensitive - active high */

            LOG_IRQ("%s: set the critical IRQ state to %d\n",

                        __func__, level);

            ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);

            break;

        case PPC40x_INPUT_INT:

            /* Level sensitive - active high */

            LOG_IRQ("%s: set the external IRQ state to %d\n",

                        __func__, level);

            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
            break;

        case PPC40x_INPUT_HALT:

            /* Level sensitive - active low */
            if (level) {

                LOG_IRQ("%s: stop the CPU\n", __func__);

                env->halted = 1;
            } else {

                LOG_IRQ("%s: restart the CPU\n", __func__);

                env->halted = 0;
            }
            break;

        case PPC40x_INPUT_DEBUG:

            /* Level sensitive - active high */

            LOG_IRQ("%s: set the debug pin state to %d\n",

                        __func__, level);

            ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);

            break;
        default:
            /* Unknown pin - do nothing */

            LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);

            return;
        }
        if (level)
            env->irq_input_state |= 1 << pin;
        else
            env->irq_input_state &= ~(1 << pin);
    }
}

void ppc40x_irq_init (CPUState *env)

{

    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
                                                  env, PPC40x_INPUT_NB);

}

/* PowerPC E500 internal IRQ controller */
static void ppce500_set_irq (void *opaque, int pin, int level)
{
    CPUState *env = opaque;
    int cur_level;

    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
                env, pin, level);
    cur_level = (env->irq_input_state >> pin) & 1;
    /* Don't generate spurious events */
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
        switch (pin) {
        case PPCE500_INPUT_MCK:
            if (level) {
                LOG_IRQ("%s: reset the PowerPC system\n",
                            __func__);
                qemu_system_reset_request();
            }
            break;
        case PPCE500_INPUT_RESET_CORE:
            if (level) {
                LOG_IRQ("%s: reset the PowerPC core\n", __func__);
                ppc_set_irq(env, PPC_INTERRUPT_MCK, level);
            }
            break;
        case PPCE500_INPUT_CINT:
            /* Level sensitive - active high */
            LOG_IRQ("%s: set the critical IRQ state to %d\n",
                        __func__, level);
            ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
            break;
        case PPCE500_INPUT_INT:
            /* Level sensitive - active high */
            LOG_IRQ("%s: set the core IRQ state to %d\n",
                        __func__, level);
            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
            break;
        case PPCE500_INPUT_DEBUG:
            /* Level sensitive - active high */
            LOG_IRQ("%s: set the debug pin state to %d\n",
                        __func__, level);
            ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
            break;
        default:
            /* Unknown pin - do nothing */
            LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
            return;
        }
        if (level)
            env->irq_input_state |= 1 << pin;
        else
            env->irq_input_state &= ~(1 << pin);
    }
}

void ppce500_irq_init (CPUState *env)
{
    env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
                                        env, PPCE500_INPUT_NB);
}

/*****************************************************************************/

/* PowerPC time base and decrementer emulation */

struct ppc_tb_t {
    /* Time base management */

    int64_t  tb_offset;    /* Compensation                    */
    int64_t  atb_offset;   /* Compensation                    */
    uint32_t tb_freq;      /* TB frequency                    */

    /* Decrementer management */

    uint64_t decr_next;    /* Tick for next decr interrupt    */
    uint32_t decr_freq;    /* decrementer frequency           */

    struct QEMUTimer *decr_timer;

    /* Hypervisor decrementer management */
    uint64_t hdecr_next;    /* Tick for next hdecr interrupt  */
    struct QEMUTimer *hdecr_timer;
    uint64_t purr_load;
    uint64_t purr_start;

    void *opaque;

};

static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk,

                                              int64_t tb_offset)

{
    /* TB time in tb periods */

    return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset;

}

uint32_t cpu_ppc_load_tbl (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);

    LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);

    return tb & 0xFFFFFFFF;
}

static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)

{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);

    LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);

    return tb >> 32;
}

uint32_t cpu_ppc_load_tbu (CPUState *env)
{
    return _cpu_ppc_load_tbu(env);
}

static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk,

                                            int64_t *tb_offsetp,
                                            uint64_t value)

{

    *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);

    LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",

                __func__, value, *tb_offsetp);

}

void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);

    tb &= 0xFFFFFFFF00000000ULL;

    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
                     &tb_env->tb_offset, tb | (uint64_t)value);

}

static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value)

{
    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);

    tb &= 0x00000000FFFFFFFFULL;

    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
                     &tb_env->tb_offset, ((uint64_t)value << 32) | tb);

}

void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
{
    _cpu_ppc_store_tbu(env, value);
}

uint32_t cpu_ppc_load_atbl (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);

    LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);

    return tb & 0xFFFFFFFF;
}

uint32_t cpu_ppc_load_atbu (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);

    LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);

    return tb >> 32;
}

void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);

    tb &= 0xFFFFFFFF00000000ULL;

    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
                     &tb_env->atb_offset, tb | (uint64_t)value);

}

void cpu_ppc_store_atbu (CPUState *env, uint32_t value)

{
    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;

    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);

    tb &= 0x00000000FFFFFFFFULL;

    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
                     &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
}

static void cpu_ppc_tb_stop (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb, atb, vmclk;

    /* If the time base is already frozen, do nothing */
    if (tb_env->tb_freq != 0) {
        vmclk = qemu_get_clock(vm_clock);
        /* Get the time base */
        tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
        /* Get the alternate time base */
        atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
        /* Store the time base value (ie compute the current offset) */
        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
        /* Store the alternate time base value (compute the current offset) */
        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
        /* Set the time base frequency to zero */
        tb_env->tb_freq = 0;
        /* Now, the time bases are frozen to tb_offset / atb_offset value */
    }
}

static void cpu_ppc_tb_start (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t tb, atb, vmclk;

    /* If the time base is not frozen, do nothing */
    if (tb_env->tb_freq == 0) {
        vmclk = qemu_get_clock(vm_clock);
        /* Get the time base from tb_offset */
        tb = tb_env->tb_offset;
        /* Get the alternate time base from atb_offset */
        atb = tb_env->atb_offset;
        /* Restore the tb frequency from the decrementer frequency */
        tb_env->tb_freq = tb_env->decr_freq;
        /* Store the time base value */
        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
        /* Store the alternate time base value */
        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
    }

}

static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
                                                  uint64_t *next)

{
    ppc_tb_t *tb_env = env->tb_env;
    uint32_t decr;

    int64_t diff;

    diff = tb_env->decr_next - qemu_get_clock(vm_clock);
    if (diff >= 0)

        decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec);

    else

        decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec);

    LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);

    return decr;
}

uint32_t cpu_ppc_load_decr (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;

    return _cpu_ppc_load_decr(env, &tb_env->decr_next);
}

uint32_t cpu_ppc_load_hdecr (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;

    return _cpu_ppc_load_decr(env, &tb_env->hdecr_next);
}

uint64_t cpu_ppc_load_purr (CPUState *env)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t diff;

    diff = qemu_get_clock(vm_clock) - tb_env->purr_start;

    return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
}

/* When decrementer expires,
 * all we need to do is generate or queue a CPU exception
 */

static always_inline void cpu_ppc_decr_excp (CPUState *env)

{
    /* Raise it */

    LOG_TB("raise decrementer exception\n");

    ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);

}

static always_inline void cpu_ppc_hdecr_excp (CPUState *env)

{
    /* Raise it */

    LOG_TB("raise decrementer exception\n");

    ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
}

static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,

                                  struct QEMUTimer *timer,
                                  void (*raise_excp)(CPUState *),
                                  uint32_t decr, uint32_t value,
                                  int is_excp)

{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t now, next;

    LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,

                decr, value);

    now = qemu_get_clock(vm_clock);

    next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq);

    if (is_excp)

        next += *nextp - now;

    if (next == now)

        next++;

    *nextp = next;

    /* Adjust timer */

    qemu_mod_timer(timer, next);

    /* If we set a negative value and the decrementer was positive,
     * raise an exception.
     */
    if ((value & 0x80000000) && !(decr & 0x80000000))

        (*raise_excp)(env);
}

static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
                                               uint32_t value, int is_excp)

{
    ppc_tb_t *tb_env = env->tb_env;

    __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,
                         &cpu_ppc_decr_excp, decr, value, is_excp);

}

void cpu_ppc_store_decr (CPUState *env, uint32_t value)
{
    _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
}

static void cpu_ppc_decr_cb (void *opaque)
{
    _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}

static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
                                                uint32_t value, int is_excp)

{
    ppc_tb_t *tb_env = env->tb_env;

    if (tb_env->hdecr_timer != NULL) {
        __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
                             &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
    }

}

void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
{
    _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
}

static void cpu_ppc_hdecr_cb (void *opaque)
{
    _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}

void cpu_ppc_store_purr (CPUState *env, uint64_t value)
{
    ppc_tb_t *tb_env = env->tb_env;

    tb_env->purr_load = value;
    tb_env->purr_start = qemu_get_clock(vm_clock);
}