gwj / at91sam9263 · Commits

Commit aae9366a036b813d58fad2d99d28a2a478109f75

Authored by j_mayer
1 parent 6b542af7

More PowerPC debug print fixes - hardware emulation pass. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3726 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 6 changed files with 134 additions and 117 deletions
hw/ppc.c
  View file @aae9366
... ... @@ -48,8 +48,8 @@ static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
48 48 }
49 49 #if defined(PPC_DEBUG_IRQ)
50 50 if (loglevel & CPU_LOG_INT) {
51   - fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
52   - __func__, env, n_IRQ, level,
  51 + fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08" PRIx32
  52 + "req %08x\n", __func__, env, n_IRQ, level,
53 53 env->pending_interrupts, env->interrupt_request);
54 54 }
55 55 #endif
... ... @@ -457,7 +457,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env)
457 457 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
458 458 #if defined(PPC_DEBUG_TB)
459 459 if (loglevel != 0) {
460   - fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
  460 + fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
461 461 }
462 462 #endif
463 463  
... ... @@ -472,7 +472,7 @@ static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
472 472 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
473 473 #if defined(PPC_DEBUG_TB)
474 474 if (loglevel != 0) {
475   - fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
  475 + fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
476 476 }
477 477 #endif
478 478  
... ... @@ -491,8 +491,8 @@ static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk,
491 491 *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);
492 492 #ifdef PPC_DEBUG_TB
493 493 if (loglevel != 0) {
494   - fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value,
495   - *tb_offsetp);
  494 + fprintf(logfile, "%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
  495 + __func__, value, *tb_offsetp);
496 496 }
497 497 #endif
498 498 }
... ... @@ -532,7 +532,7 @@ uint32_t cpu_ppc_load_atbl (CPUState *env)
532 532 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
533 533 #if defined(PPC_DEBUG_TB)
534 534 if (loglevel != 0) {
535   - fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
  535 + fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
536 536 }
537 537 #endif
538 538  
... ... @@ -547,7 +547,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env)
547 547 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
548 548 #if defined(PPC_DEBUG_TB)
549 549 if (loglevel != 0) {
550   - fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
  550 + fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
551 551 }
552 552 #endif
553 553  
... ... @@ -602,7 +602,7 @@ static void cpu_ppc_tb_start (CPUState *env)
602 602 {
603 603 ppc_tb_t *tb_env = env->tb_env;
604 604 uint64_t tb, atb, vmclk;
605   -
  605 +
606 606 /* If the time base is not frozen, do nothing */
607 607 if (tb_env->tb_freq == 0) {
608 608 vmclk = qemu_get_clock(vm_clock);
... ... @@ -633,7 +633,7 @@ static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
633 633 decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec);
634 634 #if defined(PPC_DEBUG_TB)
635 635 if (loglevel != 0) {
636   - fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
  636 + fprintf(logfile, "%s: %08" PRIx32 "\n", __func__, decr);
637 637 }
638 638 #endif
639 639  
... ... @@ -700,7 +700,8 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
700 700  
701 701 #ifdef PPC_DEBUG_TB
702 702 if (loglevel != 0) {
703   - fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
  703 + fprintf(logfile, "%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
  704 + decr, value);
704 705 }
705 706 #endif
706 707 now = qemu_get_clock(vm_clock);
... ... @@ -910,7 +911,7 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
910 911 } else {
911 912 #ifdef PPC_DEBUG_TB
912 913 if (loglevel != 0) {
913   - fprintf(logfile, "%s: start PIT 0x" REGX "\n",
  914 + fprintf(logfile, "%s: start PIT %016" PRIx64 "\n",
914 915 __func__, ppcemb_timer->pit_reload);
915 916 }
916 917 #endif
... ... @@ -1032,7 +1033,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
1032 1033 ppcemb_timer = tb_env->opaque;
1033 1034 #ifdef PPC_DEBUG_TB
1034 1035 if (loglevel != 0) {
1035   - fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
  1036 + fprintf(logfile, "%s val" ADDRX "\n", __func__, val);
1036 1037 }
1037 1038 #endif
1038 1039 ppcemb_timer->pit_reload = val;
... ... @@ -1048,7 +1049,7 @@ void store_booke_tsr (CPUState *env, target_ulong val)
1048 1049 {
1049 1050 #ifdef PPC_DEBUG_TB
1050 1051 if (loglevel != 0) {
1051   - fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
  1052 + fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);
1052 1053 }
1053 1054 #endif
1054 1055 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
... ... @@ -1063,7 +1064,7 @@ void store_booke_tcr (CPUState *env, target_ulong val)
1063 1064 tb_env = env->tb_env;
1064 1065 #ifdef PPC_DEBUG_TB
1065 1066 if (loglevel != 0) {
1066   - fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
  1067 + fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);
1067 1068 }
1068 1069 #endif
1069 1070 env->spr[SPR_40x_TCR] = val & 0xFFC00000;
... ... @@ -1078,7 +1079,8 @@ static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
1078 1079  
1079 1080 #ifdef PPC_DEBUG_TB
1080 1081 if (loglevel != 0) {
1081   - fprintf(logfile, "%s set new frequency to %u\n", __func__, freq);
  1082 + fprintf(logfile, "%s set new frequency to %" PRIu32 "\n", __func__,
  1083 + freq);
1082 1084 }
1083 1085 #endif
1084 1086 tb_env->tb_freq = freq;
... ... @@ -1102,8 +1104,7 @@ clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
1102 1104 tb_env->opaque = ppcemb_timer;
1103 1105 #ifdef PPC_DEBUG_TB
1104 1106 if (loglevel != 0) {
1105   - fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer,
1106   - &ppc_emb_set_tb_clk);
  1107 + fprintf(logfile, "%s freq %" PRIu32 "\n", __func__, freq);
1107 1108 }
1108 1109 #endif
1109 1110 if (ppcemb_timer != NULL) {
... ... @@ -1239,7 +1240,7 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1239 1240 fflush(stdout);
1240 1241 break;
1241 1242 case 2:
1242   - printf("Set loglevel to %04x\n", val);
  1243 + printf("Set loglevel to %04" PRIx32 "\n", val);
1243 1244 cpu_set_log(val | 0x100);
1244 1245 break;
1245 1246 }
... ...
hw/ppc405_uc.c
  View file @aae9366
... ... @@ -40,7 +40,7 @@ extern FILE *logfile;
40 40 #define DEBUG_GPT
41 41 #define DEBUG_MAL
42 42 #define DEBUG_CLOCKS
43   -//#define DEBUG_UNASSIGNED
  43 +//#define DEBUG_CLOCKS_LL
44 44  
45 45 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
46 46 uint32_t flags)
... ... @@ -298,7 +298,7 @@ static void opba_writeb (void *opaque,
298 298 ppc4xx_opba_t *opba;
299 299  
300 300 #ifdef DEBUG_OPBA
301   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  301 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
302 302 #endif
303 303 opba = opaque;
304 304 switch (addr - opba->base) {
... ... @@ -330,7 +330,7 @@ static void opba_writew (void *opaque,
330 330 target_phys_addr_t addr, uint32_t value)
331 331 {
332 332 #ifdef DEBUG_OPBA
333   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  333 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
334 334 #endif
335 335 opba_writeb(opaque, addr, value >> 8);
336 336 opba_writeb(opaque, addr + 1, value);
... ... @@ -353,7 +353,7 @@ static void opba_writel (void *opaque,
353 353 target_phys_addr_t addr, uint32_t value)
354 354 {
355 355 #ifdef DEBUG_OPBA
356   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  356 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
357 357 #endif
358 358 opba_writeb(opaque, addr, value >> 24);
359 359 opba_writeb(opaque, addr + 1, value >> 16);
... ... @@ -389,7 +389,7 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
389 389 if (opba != NULL) {
390 390 opba->base = offset;
391 391 #ifdef DEBUG_OPBA
392   - printf("%s: offset=" PADDRX "\n", __func__, offset);
  392 + printf("%s: offset " PADDRX "\n", __func__, offset);
393 393 #endif
394 394 ppc4xx_mmio_register(env, mmio, offset, 0x002,
395 395 opba_read, opba_write, opba);
... ... @@ -429,6 +429,10 @@ enum {
429 429 SDRAM0_CFGDATA = 0x011,
430 430 };
431 431  
  432 +/* XXX: TOFIX: some patches have made this code become inconsistent:
  433 + * there are type inconsistencies, mixing target_phys_addr_t, target_ulong
  434 + * and uint32_t
  435 + */
432 436 static uint32_t sdram_bcr (target_phys_addr_t ram_base,
433 437 target_phys_addr_t ram_size)
434 438 {
... ... @@ -457,8 +461,7 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
457 461 bcr = 0x000C0000;
458 462 break;
459 463 default:
460   - printf("%s: invalid RAM size " TARGET_FMT_plx "\n",
461   - __func__, ram_size);
  464 + printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
462 465 return 0x00000000;
463 466 }
464 467 bcr |= ram_base & 0xFF800000;
... ... @@ -491,7 +494,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
491 494 if (*bcrp & 0x00000001) {
492 495 /* Unmap RAM */
493 496 #ifdef DEBUG_SDRAM
494   - printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
  497 + printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
495 498 __func__, sdram_base(*bcrp), sdram_size(*bcrp));
496 499 #endif
497 500 cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
... ... @@ -500,7 +503,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
500 503 *bcrp = bcr & 0xFFDEE001;
501 504 if (enabled && (bcr & 0x00000001)) {
502 505 #ifdef DEBUG_SDRAM
503   - printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
  506 + printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
504 507 __func__, sdram_base(bcr), sdram_size(bcr));
505 508 #endif
506 509 cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
... ... @@ -529,7 +532,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
529 532  
530 533 for (i = 0; i < sdram->nbanks; i++) {
531 534 #ifdef DEBUG_SDRAM
532   - printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
  535 + printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
533 536 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
534 537 #endif
535 538 cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
... ... @@ -1110,7 +1113,7 @@ static void ppc405_gpio_writeb (void *opaque,
1110 1113  
1111 1114 gpio = opaque;
1112 1115 #ifdef DEBUG_GPIO
1113   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  1116 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1114 1117 #endif
1115 1118 }
1116 1119  
... ... @@ -1133,7 +1136,7 @@ static void ppc405_gpio_writew (void *opaque,
1133 1136  
1134 1137 gpio = opaque;
1135 1138 #ifdef DEBUG_GPIO
1136   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  1139 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1137 1140 #endif
1138 1141 }
1139 1142  
... ... @@ -1156,7 +1159,7 @@ static void ppc405_gpio_writel (void *opaque,
1156 1159  
1157 1160 gpio = opaque;
1158 1161 #ifdef DEBUG_GPIO
1159   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  1162 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1160 1163 #endif
1161 1164 }
1162 1165  
... ... @@ -1190,7 +1193,7 @@ void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
1190 1193 ppc405_gpio_reset(gpio);
1191 1194 qemu_register_reset(&ppc405_gpio_reset, gpio);
1192 1195 #ifdef DEBUG_GPIO
1193   - printf("%s: offset=" PADDRX "\n", __func__, offset);
  1196 + printf("%s: offset " PADDRX "\n", __func__, offset);
1194 1197 #endif
1195 1198 ppc4xx_mmio_register(env, mmio, offset, 0x038,
1196 1199 ppc405_gpio_read, ppc405_gpio_write, gpio);
... ... @@ -1218,7 +1221,7 @@ void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1218 1221 void *serial;
1219 1222  
1220 1223 #ifdef DEBUG_SERIAL
1221   - printf("%s: offset=" PADDRX "\n", __func__, offset);
  1224 + printf("%s: offset " PADDRX "\n", __func__, offset);
1222 1225 #endif
1223 1226 serial = serial_mm_init(offset, 0, irq, chr, 0);
1224 1227 ppc4xx_mmio_register(env, mmio, offset, 0x008,
... ... @@ -1248,7 +1251,9 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
1248 1251 uint32_t dsarc, uint32_t dsacntl)
1249 1252 {
1250 1253 #ifdef DEBUG_OCM
1251   - printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
  1254 + printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
  1255 + " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
  1256 + " (%08" PRIx32 " %08" PRIx32 ")\n",
1252 1257 isarc, isacntl, dsarc, dsacntl,
1253 1258 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
1254 1259 #endif
... ... @@ -1256,14 +1261,14 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
1256 1261 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
1257 1262 if (ocm->isacntl & 0x80000000) {
1258 1263 /* Unmap previously assigned memory region */
1259   - printf("OCM unmap ISA %08x\n", ocm->isarc);
  1264 + printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
1260 1265 cpu_register_physical_memory(ocm->isarc, 0x04000000,
1261 1266 IO_MEM_UNASSIGNED);
1262 1267 }
1263 1268 if (isacntl & 0x80000000) {
1264 1269 /* Map new instruction memory region */
1265 1270 #ifdef DEBUG_OCM
1266   - printf("OCM map ISA %08x\n", isarc);
  1271 + printf("OCM map ISA %08" PRIx32 "\n", isarc);
1267 1272 #endif
1268 1273 cpu_register_physical_memory(isarc, 0x04000000,
1269 1274 ocm->offset | IO_MEM_RAM);
... ... @@ -1276,7 +1281,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
1276 1281 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
1277 1282 /* Unmap previously assigned memory region */
1278 1283 #ifdef DEBUG_OCM
1279   - printf("OCM unmap DSA %08x\n", ocm->dsarc);
  1284 + printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
1280 1285 #endif
1281 1286 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
1282 1287 IO_MEM_UNASSIGNED);
... ... @@ -1287,7 +1292,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
1287 1292 if (!(isacntl & 0x80000000) || dsarc != isarc) {
1288 1293 /* Map new data memory region */
1289 1294 #ifdef DEBUG_OCM
1290   - printf("OCM map DSA %08x\n", dsarc);
  1295 + printf("OCM map DSA %08" PRIx32 "\n", dsarc);
1291 1296 #endif
1292 1297 cpu_register_physical_memory(dsarc, 0x04000000,
1293 1298 ocm->offset | IO_MEM_RAM);
... ... @@ -1475,7 +1480,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1475 1480 break;
1476 1481 }
1477 1482 #ifdef DEBUG_I2C
1478   - printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret);
  1483 + printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
1479 1484 #endif
1480 1485  
1481 1486 return ret;
... ... @@ -1487,7 +1492,7 @@ static void ppc4xx_i2c_writeb (void *opaque,
1487 1492 ppc4xx_i2c_t *i2c;
1488 1493  
1489 1494 #ifdef DEBUG_I2C
1490   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  1495 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1491 1496 #endif
1492 1497 i2c = opaque;
1493 1498 switch (addr - i2c->base) {
... ... @@ -1557,7 +1562,7 @@ static void ppc4xx_i2c_writew (void *opaque,
1557 1562 target_phys_addr_t addr, uint32_t value)
1558 1563 {
1559 1564 #ifdef DEBUG_I2C
1560   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  1565 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1561 1566 #endif
1562 1567 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1563 1568 ppc4xx_i2c_writeb(opaque, addr + 1, value);
... ... @@ -1582,7 +1587,7 @@ static void ppc4xx_i2c_writel (void *opaque,
1582 1587 target_phys_addr_t addr, uint32_t value)
1583 1588 {
1584 1589 #ifdef DEBUG_I2C
1585   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  1590 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1586 1591 #endif
1587 1592 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1588 1593 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
... ... @@ -1629,7 +1634,7 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
1629 1634 i2c->irq = irq;
1630 1635 ppc4xx_i2c_reset(i2c);
1631 1636 #ifdef DEBUG_I2C
1632   - printf("%s: offset=" PADDRX "\n", __func__, offset);
  1637 + printf("%s: offset " PADDRX "\n", __func__, offset);
1633 1638 #endif
1634 1639 ppc4xx_mmio_register(env, mmio, offset, 0x011,
1635 1640 i2c_read, i2c_write, i2c);
... ... @@ -1668,7 +1673,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
1668 1673 target_phys_addr_t addr, uint32_t value)
1669 1674 {
1670 1675 #ifdef DEBUG_I2C
1671   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  1676 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1672 1677 #endif
1673 1678 /* XXX: generate a bus fault */
1674 1679 }
... ... @@ -1686,7 +1691,7 @@ static void ppc4xx_gpt_writew (void *opaque,
1686 1691 target_phys_addr_t addr, uint32_t value)
1687 1692 {
1688 1693 #ifdef DEBUG_I2C
1689   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  1694 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1690 1695 #endif
1691 1696 /* XXX: generate a bus fault */
1692 1697 }
... ... @@ -1805,7 +1810,7 @@ static void ppc4xx_gpt_writel (void *opaque,
1805 1810 int idx;
1806 1811  
1807 1812 #ifdef DEBUG_I2C
1808   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  1813 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1809 1814 #endif
1810 1815 gpt = opaque;
1811 1816 switch (addr - gpt->base) {
... ... @@ -1913,7 +1918,7 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
1913 1918 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
1914 1919 ppc4xx_gpt_reset(gpt);
1915 1920 #ifdef DEBUG_GPT
1916   - printf("%s: offset=" PADDRX "\n", __func__, offset);
  1921 + printf("%s: offset " PADDRX "\n", __func__, offset);
1917 1922 #endif
1918 1923 ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
1919 1924 gpt_read, gpt_write, gpt);
... ... @@ -2656,9 +2661,13 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2656 2661 VCO_out = 0;
2657 2662 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2658 2663 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2659   - // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
  2664 +#ifdef DEBUG_CLOCKS_LL
  2665 + printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
  2666 +#endif
2660 2667 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2661   - // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
  2668 +#ifdef DEBUG_CLOCKS_LL
  2669 + printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
  2670 +#endif
2662 2671 VCO_out = cpc->sysclk * M * D;
2663 2672 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2664 2673 /* Error - unlock the PLL */
... ... @@ -2683,53 +2692,53 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2683 2692 }
2684 2693 /* Now, compute all other clocks */
2685 2694 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2686   -#ifdef DEBUG_CLOCKS
2687   - // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
  2695 +#ifdef DEBUG_CLOCKS_LL
  2696 + printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2688 2697 #endif
2689 2698 CPU_clk = PLL_out / D;
2690 2699 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2691   -#ifdef DEBUG_CLOCKS
2692   - // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
  2700 +#ifdef DEBUG_CLOCKS_LL
  2701 + printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2693 2702 #endif
2694 2703 PLB_clk = CPU_clk / D;
2695 2704 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2696   -#ifdef DEBUG_CLOCKS
2697   - // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
  2705 +#ifdef DEBUG_CLOCKS_LL
  2706 + printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2698 2707 #endif
2699 2708 OPB_clk = PLB_clk / D;
2700 2709 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2701   -#ifdef DEBUG_CLOCKS
2702   - // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
  2710 +#ifdef DEBUG_CLOCKS_LL
  2711 + printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2703 2712 #endif
2704 2713 EBC_clk = PLB_clk / D;
2705 2714 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2706   -#ifdef DEBUG_CLOCKS
2707   - // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
  2715 +#ifdef DEBUG_CLOCKS_LL
  2716 + printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2708 2717 #endif
2709 2718 MAL_clk = PLB_clk / D;
2710 2719 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2711   -#ifdef DEBUG_CLOCKS
2712   - // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
  2720 +#ifdef DEBUG_CLOCKS_LL
  2721 + printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2713 2722 #endif
2714 2723 PCI_clk = PLB_clk / D;
2715 2724 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2716   -#ifdef DEBUG_CLOCKS
2717   - // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
  2725 +#ifdef DEBUG_CLOCKS_LL
  2726 + printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2718 2727 #endif
2719 2728 UART0_clk = PLL_out / D;
2720 2729 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2721   -#ifdef DEBUG_CLOCKS
2722   - // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
  2730 +#ifdef DEBUG_CLOCKS_LL
  2731 + printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2723 2732 #endif
2724 2733 UART1_clk = PLL_out / D;
2725 2734 #ifdef DEBUG_CLOCKS
2726   - printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
  2735 + printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2727 2736 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2728   - printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
  2737 + printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
  2738 + " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
  2739 + " UART1 %" PRIu32 "\n",
2729 2740 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2730 2741 UART0_clk, UART1_clk);
2731   - printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb,
2732   - cpc->clk_setup[PPC405EP_CPU_CLK].opaque);
2733 2742 #endif
2734 2743 /* Setup CPU clocks */
2735 2744 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
... ...
hw/ppc4xx_devs.c
  View file @aae9366
... ... @@ -30,6 +30,7 @@ extern int loglevel;
30 30 extern FILE *logfile;
31 31  
32 32 //#define DEBUG_MMIO
  33 +//#define DEBUG_UNASSIGNED
33 34 #define DEBUG_UIC
34 35  
35 36 /*****************************************************************************/
... ... @@ -136,8 +137,8 @@ static void mmio_writelen (ppc4xx_mmio_t *mmio,
136 137  
137 138 idx = MMIO_IDX(addr - mmio->base);
138 139 #if defined(DEBUG_MMIO)
139   - printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
140   - mmio, len, addr, idx, value);
  140 + printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
  141 + __func__, mmio, len, addr, idx, value);
141 142 #endif
142 143 mem_write = mmio->mem_write[idx];
143 144 (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
... ... @@ -156,7 +157,7 @@ static void mmio_writeb (void *opaque,
156 157 target_phys_addr_t addr, uint32_t value)
157 158 {
158 159 #if defined(DEBUG_MMIO)
159   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  160 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
160 161 #endif
161 162 mmio_writelen(opaque, addr, value, 0);
162 163 }
... ... @@ -174,7 +175,7 @@ static void mmio_writew (void *opaque,
174 175 target_phys_addr_t addr, uint32_t value)
175 176 {
176 177 #if defined(DEBUG_MMIO)
177   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  178 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
178 179 #endif
179 180 mmio_writelen(opaque, addr, value, 1);
180 181 }
... ... @@ -192,7 +193,7 @@ static void mmio_writel (void *opaque,
192 193 target_phys_addr_t addr, uint32_t value)
193 194 {
194 195 #if defined(DEBUG_MMIO)
195   - printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
  196 + printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
196 197 #endif
197 198 mmio_writelen(opaque, addr, value, 2);
198 199 }
... ... @@ -214,7 +215,7 @@ int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
214 215 CPUReadMemoryFunc **mem_read,
215 216 CPUWriteMemoryFunc **mem_write, void *opaque)
216 217 {
217   - uint32_t end;
  218 + target_phys_addr_t end;
218 219 int idx, eidx;
219 220  
220 221 if ((offset + len) > TARGET_PAGE_SIZE)
... ... @@ -223,8 +224,8 @@ int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
223 224 end = offset + len - 1;
224 225 eidx = MMIO_IDX(end);
225 226 #if defined(DEBUG_MMIO)
226   - printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
227   - end, idx, eidx);
  227 + printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
  228 + __func__, offset, len, end, idx, eidx);
228 229 #endif
229 230 for (; idx <= eidx; idx++) {
230 231 mmio->mem_read[idx] = mem_read;
... ... @@ -245,8 +246,8 @@ ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
245 246 mmio->base = base;
246 247 mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
247 248 #if defined(DEBUG_MMIO)
248   - printf("%s: %p base %08x len %08x %d\n", __func__,
249   - mmio, base, TARGET_PAGE_SIZE, mmio_memory);
  249 + printf("%s: base " PADDRX " len %08x %d\n", __func__,
  250 + base, TARGET_PAGE_SIZE, mmio_memory);
250 251 #endif
251 252 cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
252 253 ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
... ... @@ -297,9 +298,10 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
297 298 cr = uic->uicsr & uic->uicer & uic->uiccr;
298 299 #ifdef DEBUG_UIC
299 300 if (loglevel & CPU_LOG_INT) {
300   - fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
301   - " %08x ir %08x cr %08x\n", __func__,
302   - uic->uicsr, uic->uicer, uic->uiccr,
  301 + fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
  302 + " uiccr %08" PRIx32 "\n"
  303 + " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
  304 + __func__, uic->uicsr, uic->uicer, uic->uiccr,
303 305 uic->uicsr & uic->uicer, ir, cr);
304 306 }
305 307 #endif
... ... @@ -342,8 +344,8 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
342 344 }
343 345 #ifdef DEBUG_UIC
344 346 if (loglevel & CPU_LOG_INT) {
345   - fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
346   - uic->uicvr);
  347 + fprintf(logfile, "Raise UIC critical interrupt - "
  348 + "vector %08" PRIx32 "\n", uic->uicvr);
347 349 }
348 350 #endif
349 351 } else {
... ... @@ -366,8 +368,9 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
366 368 mask = 1 << irq_num;
367 369 #ifdef DEBUG_UIC
368 370 if (loglevel & CPU_LOG_INT) {
369   - fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
370   - "%08x\n", __func__, irq_num, level,
  371 + fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
  372 + " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
  373 + __func__, irq_num, level,
371 374 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
372 375 }
373 376 #endif
... ... @@ -392,8 +395,8 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
392 395 }
393 396 #ifdef DEBUG_UIC
394 397 if (loglevel & CPU_LOG_INT) {
395   - fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
396   - irq_num, level, uic->uicsr, sr);
  398 + fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
  399 + "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
397 400 }
398 401 #endif
399 402 if (sr != uic->uicsr)
... ...
hw/ppc_chrp.c
  View file @aae9366
... ... @@ -255,7 +255,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size,
255 255 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
256 256 ram_size, vga_ram_size,
257 257 vga_bios_offset, vga_bios_size);
258   -
  258 +
259 259 /* XXX: suppress that */
260 260 dummy_irq = i8259_init(NULL);
261 261  
... ... @@ -274,7 +274,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size,
274 274 #endif
275 275 /* cuda also initialize ADB */
276 276 cuda_init(&cuda_mem_index, pic[0x19]);
277   -
  277 +
278 278 adb_kbd_init(&adb_bus);
279 279 adb_mouse_init(&adb_bus);
280 280  
... ... @@ -314,7 +314,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size,
314 314  
315 315 /* Special port to get debug messages from Open-Firmware */
316 316 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
317   - }
  317 +}
318 318  
319 319 QEMUMachine core99_machine = {
320 320 "mac99",
... ...
hw/ppc_oldworld.c
  View file @aae9366
... ... @@ -41,7 +41,7 @@ static int vga_osi_call (CPUState *env)
41 41 static int vga_vbl_enabled;
42 42 int linesize;
43 43  
44   - // printf("osi_call R5=%d\n", env->gpr[5]);
  44 + // printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
45 45  
46 46 /* same handler as PearPC, coming from the original MOL video
47 47 driver. */
... ... @@ -93,7 +93,8 @@ static int vga_osi_call (CPUState *env)
93 93 /* R6 = x, R7 = y, R8 = visible, R9 = data */
94 94 break;
95 95 default:
96   - fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
  96 + fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
  97 + ppc_dump_gpr(env, 5));
97 98 break;
98 99 }
99 100  
... ... @@ -245,7 +246,7 @@ static void ppc_heathrow_init (int ram_size, int vga_ram_size,
245 246 }
246 247  
247 248 isa_mem_base = 0x80000000;
248   -
  249 +
249 250 /* Register 2 MB of ISA IO space */
250 251 isa_mmio_init(0xfe000000, 0x00200000);
251 252  
... ... @@ -277,13 +278,13 @@ static void ppc_heathrow_init (int ram_size, int vga_ram_size,
277 278 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
278 279 ram_size, vga_ram_size,
279 280 vga_bios_offset, vga_bios_size);
280   -
  281 +
281 282 /* XXX: suppress that */
282 283 dummy_irq = i8259_init(NULL);
283 284  
284 285 /* XXX: use Mac Serial port */
285 286 serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
286   -
  287 +
287 288 for(i = 0; i < nb_nics; i++) {
288 289 if (!nd_table[i].model)
289 290 nd_table[i].model = "ne2k_pci";
... ... @@ -301,7 +302,7 @@ static void ppc_heathrow_init (int ram_size, int vga_ram_size,
301 302  
302 303 adb_kbd_init(&adb_bus);
303 304 adb_mouse_init(&adb_bus);
304   -
  305 +
305 306 nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
306 307 pmac_format_nvram_partition(nvr, 0x2000);
307 308  
... ...
hw/ppc_prep.c
  View file @aae9366
... ... @@ -113,7 +113,7 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
113 113 static void _PPC_intack_write (void *opaque,
114 114 target_phys_addr_t addr, uint32_t value)
115 115 {
116   - // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
  116 +// printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
117 117 }
118 118  
119 119 static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
... ... @@ -122,7 +122,7 @@ static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
122 122  
123 123 if (addr == 0xBFFFFFF0)
124 124 retval = pic_intack_read(isa_pic);
125   - // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
  125 +// printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
126 126  
127 127 return retval;
128 128 }
... ... @@ -192,7 +192,7 @@ static struct {
192 192 static void PPC_XCSR_writeb (void *opaque,
193 193 target_phys_addr_t addr, uint32_t value)
194 194 {
195   - printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
  195 + printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
196 196 }
197 197  
198 198 static void PPC_XCSR_writew (void *opaque,
... ... @@ -201,7 +201,7 @@ static void PPC_XCSR_writew (void *opaque,
201 201 #ifdef TARGET_WORDS_BIGENDIAN
202 202 value = bswap16(value);
203 203 #endif
204   - printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
  204 + printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
205 205 }
206 206  
207 207 static void PPC_XCSR_writel (void *opaque,
... ... @@ -210,14 +210,14 @@ static void PPC_XCSR_writel (void *opaque,
210 210 #ifdef TARGET_WORDS_BIGENDIAN
211 211 value = bswap32(value);
212 212 #endif
213   - printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
  213 + printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
214 214 }
215 215  
216 216 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
217 217 {
218 218 uint32_t retval = 0;
219 219  
220   - printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
  220 + printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
221 221  
222 222 return retval;
223 223 }
... ... @@ -226,7 +226,7 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
226 226 {
227 227 uint32_t retval = 0;
228 228  
229   - printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
  229 + printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
230 230 #ifdef TARGET_WORDS_BIGENDIAN
231 231 retval = bswap16(retval);
232 232 #endif
... ... @@ -238,7 +238,7 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
238 238 {
239 239 uint32_t retval = 0;
240 240  
241   - printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
  241 + printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
242 242 #ifdef TARGET_WORDS_BIGENDIAN
243 243 retval = bswap32(retval);
244 244 #endif
... ... @@ -280,7 +280,8 @@ static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
280 280 {
281 281 sysctrl_t *sysctrl = opaque;
282 282  
283   - PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
  283 + PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
  284 + val);
284 285 sysctrl->fake_io[addr - 0x0398] = val;
285 286 }
286 287  
... ... @@ -288,7 +289,7 @@ static uint32_t PREP_io_read (void *opaque, uint32_t addr)
288 289 {
289 290 sysctrl_t *sysctrl = opaque;
290 291  
291   - PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
  292 + PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
292 293 sysctrl->fake_io[addr - 0x0398]);
293 294 return sysctrl->fake_io[addr - 0x0398];
294 295 }
... ... @@ -297,7 +298,8 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
297 298 {
298 299 sysctrl_t *sysctrl = opaque;
299 300  
300   - PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
  301 + PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
  302 + addr - PPC_IO_BASE, val);
301 303 switch (addr) {
302 304 case 0x0092:
303 305 /* Special port 92 */
... ... @@ -353,8 +355,8 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
353 355 sysctrl->contiguous_map = val & 0x01;
354 356 break;
355 357 default:
356   - printf("ERROR: unaffected IO port write: %04lx => %02x\n",
357   - (long)addr, val);
  358 + printf("ERROR: unaffected IO port write: %04" PRIx32
  359 + " => %02" PRIx32"\n", addr, val);
358 360 break;
359 361 }
360 362 }
... ... @@ -416,10 +418,11 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
416 418 retval = sysctrl->contiguous_map;
417 419 break;
418 420 default:
419   - printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
  421 + printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
420 422 break;
421 423 }
422   - PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
  424 + PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
  425 + addr - PPC_IO_BASE, retval);
423 426  
424 427 return retval;
425 428 }
... ... @@ -468,7 +471,7 @@ static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
468 471 #ifdef TARGET_WORDS_BIGENDIAN
469 472 value = bswap16(value);
470 473 #endif
471   - PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
  474 + PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
472 475 cpu_outw(NULL, addr, value);
473 476 }
474 477  
... ... @@ -482,7 +485,7 @@ static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
482 485 #ifdef TARGET_WORDS_BIGENDIAN
483 486 ret = bswap16(ret);
484 487 #endif
485   - PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
  488 + PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
486 489  
487 490 return ret;
488 491 }
... ... @@ -496,7 +499,7 @@ static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
496 499 #ifdef TARGET_WORDS_BIGENDIAN
497 500 value = bswap32(value);
498 501 #endif
499   - PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
  502 + PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
500 503 cpu_outl(NULL, addr, value);
501 504 }
502 505  
... ... @@ -510,7 +513,7 @@ static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
510 513 #ifdef TARGET_WORDS_BIGENDIAN
511 514 ret = bswap32(ret);
512 515 #endif
513   - PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
  516 + PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
514 517  
515 518 return ret;
516 519 }
... ...