gwj / at91sam9263 · Commits

Commit e96efcfcb19b81d87ed3baec419b14cdd6e021a4

Authored by j_mayer
1 parent ba13c432

Fix miscellaneous display warnings for PowerPC & alpha targets 

and parallel CFI flash driver.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2661 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 8 changed files with 46 additions and 31 deletions
hw/pflash_cfi02.c
  View file @e96efcf
... ... @@ -91,7 +91,7 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
91 91 uint32_t ret;
92 92 uint8_t *p;
93 93  
94   - DPRINTF("%s: offset %08x\n", __func__, offset);
  94 + DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
95 95 ret = -1;
96 96 offset -= pfl->base;
97 97 boff = offset & 0xFF;
... ... @@ -161,7 +161,7 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
161 161 default:
162 162 goto flash_read;
163 163 }
164   - DPRINTF("%s: ID %d %x\n", __func__, boff, ret);
  164 + DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret);
165 165 break;
166 166 case 0xA0:
167 167 case 0x10:
... ... @@ -214,7 +214,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
214 214 offset -= pfl->base;
215 215  
216 216 cmd = value;
217   - DPRINTF("%s: offset %08x %08x %d\n", __func__, offset, value, width);
  217 + DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
  218 + offset, value, width);
218 219 if (pfl->cmd != 0xA0 && cmd == 0xF0) {
219 220 DPRINTF("%s: flash reset asked (%02x %02x)\n",
220 221 __func__, pfl->cmd, cmd);
... ... @@ -239,7 +240,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
239 240 return;
240 241 }
241 242 if (boff != 0x555 || cmd != 0xAA) {
242   - DPRINTF("%s: unlock0 failed %04x %02x %04x\n",
  243 + DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n",
243 244 __func__, boff, cmd, 0x555);
244 245 goto reset_flash;
245 246 }
... ... @@ -249,7 +250,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
249 250 /* We started an unlock sequence */
250 251 check_unlock1:
251 252 if (boff != 0x2AA || cmd != 0x55) {
252   - DPRINTF("%s: unlock1 failed %04x %02x\n", __func__, boff, cmd);
  253 + DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__,
  254 + boff, cmd);
253 255 goto reset_flash;
254 256 }
255 257 DPRINTF("%s: unlock sequence done\n", __func__);
... ... @@ -257,7 +259,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
257 259 case 2:
258 260 /* We finished an unlock sequence */
259 261 if (!pfl->bypass && boff != 0x555) {
260   - DPRINTF("%s: command failed %04x %02x\n", __func__, boff, cmd);
  262 + DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__,
  263 + boff, cmd);
261 264 goto reset_flash;
262 265 }
263 266 switch (cmd) {
... ... @@ -281,7 +284,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
281 284 /* We need another unlock sequence */
282 285 goto check_unlock0;
283 286 case 0xA0:
284   - DPRINTF("%s: write data offset %08x %08x %d\n",
  287 + DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n",
285 288 __func__, offset, value, width);
286 289 p = pfl->storage;
287 290 switch (width) {
... ... @@ -352,7 +355,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
352 355 switch (cmd) {
353 356 case 0x10:
354 357 if (boff != 0x555) {
355   - DPRINTF("%s: chip erase: invalid address %04x\n",
  358 + DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n",
356 359 __func__, offset);
357 360 goto reset_flash;
358 361 }
... ... @@ -369,7 +372,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
369 372 /* Sector erase */
370 373 p = pfl->storage;
371 374 offset &= ~(pfl->sector_len - 1);
372   - DPRINTF("%s: start sector erase at %08x\n", __func__, offset);
  375 + DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__,
  376 + offset);
373 377 memset(p + offset, 0xFF, pfl->sector_len);
374 378 pflash_update(pfl, offset, pfl->sector_len);
375 379 pfl->status = 0x00;
... ...
hw/ppc.c
  View file @e96efcf
... ... @@ -464,8 +464,8 @@ static void cpu_4xx_fit_cb (void *opaque)
464 464 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
465 465 ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
466 466 if (loglevel) {
467   - fprintf(logfile, "%s: ir %d TCR %08x TSR %08x\n", __func__,
468   - (env->spr[SPR_40x_TCR] >> 23) & 0x1,
  467 + fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
  468 + (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
469 469 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
470 470 }
471 471 }
... ... @@ -495,9 +495,10 @@ static void cpu_4xx_pit_cb (void *opaque)
495 495 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
496 496 ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
497 497 if (loglevel) {
498   - fprintf(logfile, "%s: ar %d ir %d TCR %08x TSR %08x %08lx\n", __func__,
499   - (env->spr[SPR_40x_TCR] >> 22) & 0x1,
500   - (env->spr[SPR_40x_TCR] >> 26) & 0x1,
  498 + fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
  499 + "%016" PRIx64 "\n", __func__,
  500 + (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
  501 + (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
501 502 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
502 503 ppcemb_timer->pit_reload);
503 504 }
... ... @@ -536,7 +537,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
536 537 if (next == now)
537 538 next++;
538 539 if (loglevel) {
539   - fprintf(logfile, "%s: TCR %08x TSR %08x\n", __func__,
  540 + fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
540 541 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
541 542 }
542 543 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
... ... @@ -587,7 +588,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
587 588 qemu_del_timer(tb_env->decr_timer);
588 589 } else {
589 590 if (loglevel)
590   - fprintf(logfile, "%s: start PIT 0x%08x\n", __func__, val);
  591 + fprintf(logfile, "%s: start PIT 0x" ADDRX "\n", __func__, val);
591 592 now = qemu_get_clock(vm_clock);
592 593 next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq);
593 594 if (next == now)
... ...
hw/ppc_chrp.c
  View file @e96efcf
... ... @@ -48,7 +48,7 @@ static int macio_nvram_mem_index = -1;
48 48  
49 49 static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
50 50 {
51   - printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
  51 + printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
52 52 }
53 53  
54 54 static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
... ... @@ -61,7 +61,7 @@ static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
61 61  
62 62 static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
63 63 {
64   - printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
  64 + printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
65 65 return 0;
66 66 }
67 67  
... ... @@ -261,7 +261,7 @@ static int vga_osi_call(CPUState *env)
261 261 /* R6 = x, R7 = y, R8 = visible, R9 = data */
262 262 break;
263 263 default:
264   - fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]);
  264 + fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
265 265 break;
266 266 }
267 267 return 1; /* osi_call handled */
... ...
linux-user/main.c
  View file @e96efcf
... ... @@ -755,10 +755,10 @@ void cpu_loop(CPUPPCState *env)
755 755 info._sifields._sigfault._addr = env->nip - 4;
756 756 queue_signal(info.si_signo, &info);
757 757 case EXCP_DSI:
758   - fprintf(stderr, "Invalid data memory access: 0x%08x\n",
  758 + fprintf(stderr, "Invalid data memory access: 0x" ADDRX "\n",
759 759 env->spr[SPR_DAR]);
760 760 if (loglevel) {
761   - fprintf(logfile, "Invalid data memory access: 0x%08x\n",
  761 + fprintf(logfile, "Invalid data memory access: 0x" ADDRX "\n",
762 762 env->spr[SPR_DAR]);
763 763 }
764 764 switch (env->error_code & 0xFF000000) {
... ... @@ -1549,7 +1549,7 @@ void cpu_loop(CPUM68KState *env)
1549 1549 #ifdef TARGET_ALPHA
1550 1550 void cpu_loop (CPUState *env)
1551 1551 {
1552   - int trapnr, ret;
  1552 + int trapnr;
1553 1553 target_siginfo_t info;
1554 1554  
1555 1555 while (1) {
... ...
target-alpha/cpu.h
  View file @e96efcf
... ... @@ -382,6 +382,13 @@ enum {
382 382 IR_ZERO = 31,
383 383 };
384 384  
  385 +CPUAlphaState * cpu_alpha_init (void);
  386 +int cpu_alpha_exec(CPUAlphaState *s);
  387 +/* you can call this signal handler from your SIGBUS and SIGSEGV
  388 + signal handlers to inform the virtual CPU of exceptions. non zero
  389 + is returned if the signal was handled by the virtual CPU. */
  390 +int cpu_alpha_signal_handler(int host_signum, void *pinfo,
  391 + void *puc);
385 392 int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);
386 393 int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
387 394 void cpu_loop_exit (void);
... ...
target-alpha/translate.c
  View file @e96efcf
... ... @@ -2004,7 +2004,8 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
2004 2004 #if defined ALPHA_DEBUG_DISAS
2005 2005 insn_count++;
2006 2006 if (logfile != NULL) {
2007   - fprintf(logfile, "pc %016lx mem_idx\n", ctx.pc, ctx.mem_idx);
  2007 + fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
  2008 + ctx.pc, ctx.mem_idx);
2008 2009 }
2009 2010 #endif
2010 2011 insn = ldl_code(ctx.pc);
... ...
target-ppc/cpu.h
  View file @e96efcf
... ... @@ -35,24 +35,26 @@ typedef uint64_t ppc_gpr_t;
35 35 #define TARGET_LONG_BITS 64
36 36 #define TARGET_GPR_BITS 64
37 37 #define REGX "%016" PRIx64
38   -#define ADDRX "%016" PRIx64
39 38 #elif defined(TARGET_PPCSPE)
  39 +/* e500v2 have 36 bits physical address space */
  40 +#define TARGET_PHYS_ADDR_BITS 64
40 41 /* GPR are 64 bits: used by vector extension */
41 42 typedef uint64_t ppc_gpr_t;
42 43 #define TARGET_LONG_BITS 32
43 44 #define TARGET_GPR_BITS 64
44 45 #define REGX "%016" PRIx64
45   -#define ADDRX "%08" PRIx32
46 46 #else
47 47 typedef uint32_t ppc_gpr_t;
48 48 #define TARGET_LONG_BITS 32
49 49 #define TARGET_GPR_BITS 32
50 50 #define REGX "%08" PRIx32
51   -#define ADDRX "%08" PRIx32
52 51 #endif
53 52  
54 53 #include "cpu-defs.h"
55 54  
  55 +#define ADDRX TARGET_FMT_lx
  56 +#define PADDRX TARGET_FMT_plx
  57 +
56 58 #include <setjmp.h>
57 59  
58 60 #include "softfloat.h"
... ...
target-ppc/helper.c
  View file @e96efcf
... ... @@ -38,7 +38,7 @@
38 38 /* PowerPC MMU emulation */
39 39  
40 40 #if defined(CONFIG_USER_ONLY)
41   -int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
  41 +int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
42 42 int is_user, int is_softmmu)
43 43 {
44 44 int exception, error_code;
... ... @@ -631,7 +631,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
631 631 }
632 632  
633 633 int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
634   - uint32_t address, int rw, int access_type)
  634 + target_ulong address, int rw, int access_type)
635 635 {
636 636 ppcemb_tlb_t *tlb;
637 637 target_phys_addr_t raddr;
... ... @@ -649,8 +649,8 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
649 649 }
650 650 mask = ~(tlb->size - 1);
651 651 if (loglevel) {
652   - fprintf(logfile, "%s: TLB %d address %08x PID %04x <=> "
653   - "%08x %08x %04x\n",
  652 + fprintf(logfile, "%s: TLB %d address " ADDRX " PID " ADDRX " <=> "
  653 + ADDRX " " ADDRX " " ADDRX "\n",
654 654 __func__, i, address, env->spr[SPR_40x_PID],
655 655 tlb->EPN, mask, tlb->PID);
656 656 }
... ... @@ -832,7 +832,7 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
832 832 }
833 833  
834 834 /* Perform address translation */
835   -int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
  835 +int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
836 836 int is_user, int is_softmmu)
837 837 {
838 838 mmu_ctx_t ctx;
... ...