gwj / at91sam9263 · Commits

Commit d0dfae6e91d9b2044523ed4db890860f898af86b

Authored by j_mayer
1 parent 08e46e54

Add bus model (or input pins) into PowerPC CPU flags. 

Add PowerPC 970 bus and exceptions model.
Add code provision for PowerPC 970 instanciation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2680 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 238 additions and 42 deletions
hw/ppc.c
  View file @d0dfae6
... ... @@ -161,6 +161,128 @@ void ppc6xx_irq_init (CPUState *env)
161 161 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
162 162 }
163 163  
  164 +/* PowerPC 970 internal IRQ controller */
  165 +static void ppc970_set_irq (void *opaque, int pin, int level)
  166 +{
  167 + CPUState *env = opaque;
  168 + int cur_level;
  169 +
  170 +#if defined(PPC_DEBUG_IRQ)
  171 + if (loglevel & CPU_LOG_INT) {
  172 + fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
  173 + env, pin, level);
  174 + }
  175 +#endif
  176 + cur_level = (env->irq_input_state >> pin) & 1;
  177 + /* Don't generate spurious events */
  178 + if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
  179 + switch (pin) {
  180 + case PPC970_INPUT_INT:
  181 + /* Level sensitive - active high */
  182 +#if defined(PPC_DEBUG_IRQ)
  183 + if (loglevel & CPU_LOG_INT) {
  184 + fprintf(logfile, "%s: set the external IRQ state to %d\n",
  185 + __func__, level);
  186 + }
  187 +#endif
  188 + ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
  189 + break;
  190 + case PPC970_INPUT_THINT:
  191 + /* Level sensitive - active high */
  192 +#if defined(PPC_DEBUG_IRQ)
  193 + if (loglevel & CPU_LOG_INT) {
  194 + fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
  195 + level);
  196 + }
  197 +#endif
  198 + ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
  199 + break;
  200 + case PPC970_INPUT_MCP:
  201 + /* Negative edge sensitive */
  202 + /* XXX: TODO: actual reaction may depends on HID0 status
  203 + * 603/604/740/750: check HID0[EMCP]
  204 + */
  205 + if (cur_level == 1 && level == 0) {
  206 +#if defined(PPC_DEBUG_IRQ)
  207 + if (loglevel & CPU_LOG_INT) {
  208 + fprintf(logfile, "%s: raise machine check state\n",
  209 + __func__);
  210 + }
  211 +#endif
  212 + ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
  213 + }
  214 + break;
  215 + case PPC970_INPUT_CKSTP:
  216 + /* Level sensitive - active low */
  217 + /* XXX: TODO: relay the signal to CKSTP_OUT pin */
  218 + if (level) {
  219 +#if defined(PPC_DEBUG_IRQ)
  220 + if (loglevel & CPU_LOG_INT) {
  221 + fprintf(logfile, "%s: stop the CPU\n", __func__);
  222 + }
  223 +#endif
  224 + env->halted = 1;
  225 + } else {
  226 +#if defined(PPC_DEBUG_IRQ)
  227 + if (loglevel & CPU_LOG_INT) {
  228 + fprintf(logfile, "%s: restart the CPU\n", __func__);
  229 + }
  230 +#endif
  231 + env->halted = 0;
  232 + }
  233 + break;
  234 + case PPC970_INPUT_HRESET:
  235 + /* Level sensitive - active low */
  236 + if (level) {
  237 +#if 0 // XXX: TOFIX
  238 +#if defined(PPC_DEBUG_IRQ)
  239 + if (loglevel & CPU_LOG_INT) {
  240 + fprintf(logfile, "%s: reset the CPU\n", __func__);
  241 + }
  242 +#endif
  243 + cpu_reset(env);
  244 +#endif
  245 + }
  246 + break;
  247 + case PPC970_INPUT_SRESET:
  248 +#if defined(PPC_DEBUG_IRQ)
  249 + if (loglevel & CPU_LOG_INT) {
  250 + fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
  251 + __func__, level);
  252 + }
  253 +#endif
  254 + ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
  255 + break;
  256 + case PPC970_INPUT_TBEN:
  257 +#if defined(PPC_DEBUG_IRQ)
  258 + if (loglevel & CPU_LOG_INT) {
  259 + fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
  260 + level);
  261 + }
  262 +#endif
  263 + /* XXX: TODO */
  264 + break;
  265 + default:
  266 + /* Unknown pin - do nothing */
  267 +#if defined(PPC_DEBUG_IRQ)
  268 + if (loglevel & CPU_LOG_INT) {
  269 + fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
  270 + }
  271 +#endif
  272 + return;
  273 + }
  274 + if (level)
  275 + env->irq_input_state |= 1 << pin;
  276 + else
  277 + env->irq_input_state &= ~(1 << pin);
  278 + }
  279 +}
  280 +
  281 +void ppc970_irq_init (CPUState *env)
  282 +{
  283 + env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
  284 +}
  285 +
164 286 /* PowerPC 405 internal IRQ controller */
165 287 static void ppc405_set_irq (void *opaque, int pin, int level)
166 288 {
... ...
target-ppc/cpu.h
  View file @d0dfae6
... ... @@ -393,51 +393,60 @@ enum {
393 393 /* CPU run-time flags (MMU and exception model) */
394 394 enum {
395 395 /* MMU model */
396   - PPC_FLAGS_MMU_MASK = 0x0000000F,
  396 + PPC_FLAGS_MMU_MASK = 0x000000FF,
397 397 /* Standard 32 bits PowerPC MMU */
398   - PPC_FLAGS_MMU_32B = 0x00000000,
  398 + PPC_FLAGS_MMU_32B = 0x00000000,
399 399 /* Standard 64 bits PowerPC MMU */
400   - PPC_FLAGS_MMU_64B = 0x00000001,
  400 + PPC_FLAGS_MMU_64B = 0x00000001,
401 401 /* PowerPC 601 MMU */
402   - PPC_FLAGS_MMU_601 = 0x00000002,
  402 + PPC_FLAGS_MMU_601 = 0x00000002,
403 403 /* PowerPC 6xx MMU with software TLB */
404   - PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
  404 + PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
405 405 /* PowerPC 4xx MMU with software TLB */
406   - PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
  406 + PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
407 407 /* PowerPC 403 MMU */
408   - PPC_FLAGS_MMU_403 = 0x00000005,
409   - /* Freescale e500 MMU model */
410   - PPC_FLAGS_MMU_e500 = 0x00000006,
  408 + PPC_FLAGS_MMU_403 = 0x00000005,
  409 + /* BookE FSL MMU model */
  410 + PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006,
411 411 /* BookE MMU model */
412   - PPC_FLAGS_MMU_BOOKE = 0x00000007,
  412 + PPC_FLAGS_MMU_BOOKE = 0x00000007,
  413 + /* 64 bits "bridge" PowerPC MMU */
  414 + PPC_FLAGS_MMU_64BRIDGE = 0x00000008,
413 415 /* Exception model */
414   - PPC_FLAGS_EXCP_MASK = 0x000000F0,
  416 + PPC_FLAGS_EXCP_MASK = 0x0000FF00,
415 417 /* Standard PowerPC exception model */
416   - PPC_FLAGS_EXCP_STD = 0x00000000,
  418 + PPC_FLAGS_EXCP_STD = 0x00000000,
417 419 /* PowerPC 40x exception model */
418   - PPC_FLAGS_EXCP_40x = 0x00000010,
  420 + PPC_FLAGS_EXCP_40x = 0x00000100,
419 421 /* PowerPC 601 exception model */
420   - PPC_FLAGS_EXCP_601 = 0x00000020,
  422 + PPC_FLAGS_EXCP_601 = 0x00000200,
421 423 /* PowerPC 602 exception model */
422   - PPC_FLAGS_EXCP_602 = 0x00000030,
  424 + PPC_FLAGS_EXCP_602 = 0x00000300,
423 425 /* PowerPC 603 exception model */
424   - PPC_FLAGS_EXCP_603 = 0x00000040,
  426 + PPC_FLAGS_EXCP_603 = 0x00000400,
425 427 /* PowerPC 604 exception model */
426   - PPC_FLAGS_EXCP_604 = 0x00000050,
  428 + PPC_FLAGS_EXCP_604 = 0x00000500,
427 429 /* PowerPC 7x0 exception model */
428   - PPC_FLAGS_EXCP_7x0 = 0x00000060,
  430 + PPC_FLAGS_EXCP_7x0 = 0x00000600,
429 431 /* PowerPC 7x5 exception model */
430   - PPC_FLAGS_EXCP_7x5 = 0x00000070,
  432 + PPC_FLAGS_EXCP_7x5 = 0x00000700,
431 433 /* PowerPC 74xx exception model */
432   - PPC_FLAGS_EXCP_74xx = 0x00000080,
  434 + PPC_FLAGS_EXCP_74xx = 0x00000800,
433 435 /* PowerPC 970 exception model */
434   - PPC_FLAGS_EXCP_970 = 0x00000090,
  436 + PPC_FLAGS_EXCP_970 = 0x00000900,
435 437 /* BookE exception model */
436   - PPC_FLAGS_EXCP_BOOKE = 0x000000A0,
  438 + PPC_FLAGS_EXCP_BOOKE = 0x00000A00,
  439 + /* Input pins model */
  440 + PPC_FLAGS_INPUT_MASK = 0x000F0000,
  441 + PPC_FLAGS_INPUT_6xx = 0x00000000,
  442 + PPC_FLAGS_INPUT_BookE = 0x00010000,
  443 + PPC_FLAGS_INPUT_40x = 0x00020000,
  444 + PPC_FLAGS_INPUT_970 = 0x00030000,
437 445 };
438 446  
439 447 #define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
440 448 #define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
  449 +#define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK)
441 450  
442 451 /*****************************************************************************/
443 452 /* Supported instruction set definitions */
... ... @@ -454,64 +463,78 @@ enum {
454 463 #define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
455 464 PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \
456 465 PPC_40x_SPEC)
457   -#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
  466 +#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \
  467 + PPC_FLAGS_INPUT_40x)
458 468 /* PowerPC 405 */
459 469 #define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
460 470 PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \
461 471 PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \
462 472 PPC_405_MAC)
463   -#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
  473 +#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
  474 + PPC_FLAGS_INPUT_40x)
464 475 /* PowerPC 440 */
465 476 #define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
466 477 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
467   -#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
  478 +#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
  479 + PPC_FLAGS_INPUT_BookE)
468 480 /* Generic BookE PowerPC */
469 481 #define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
470 482 PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
471   -#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
  483 +#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
  484 + PPC_FLAGS_INPUT_BookE)
472 485 /* e500 core */
473 486 #define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
474 487 PPC_CACHE_OPT | PPC_E500_VECTOR)
475   -#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
  488 +#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
  489 + PPC_FLAGS_INPUT_BookE)
476 490 /* Non-embedded PowerPC */
477 491 #define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
478   - PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
  492 + PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
479 493 /* PowerPC 601 */
480 494 #define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
481   -#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
  495 +#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 | \
  496 + PPC_FLAGS_INPUT_6xx)
482 497 /* PowerPC 602 */
483 498 #define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
484 499 PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
485   -#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
  500 +#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 | \
  501 + PPC_FLAGS_INPUT_6xx)
486 502 /* PowerPC 603 */
487 503 #define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
488 504 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
489   -#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
  505 +#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
  506 + PPC_FLAGS_INPUT_6xx)
490 507 /* PowerPC G2 */
491 508 #define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
492 509 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
493   -#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
  510 +#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
  511 + PPC_FLAGS_INPUT_6xx)
494 512 /* PowerPC 604 */
495 513 #define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
496 514 PPC_MEM_TLBSYNC | PPC_TB)
497   -#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
  515 +#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 | \
  516 + PPC_FLAGS_INPUT_6xx)
498 517 /* PowerPC 740/750 (aka G3) */
499 518 #define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
500 519 PPC_MEM_TLBSYNC | PPC_TB)
501   -#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
  520 +#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 | \
  521 + PPC_FLAGS_INPUT_6xx)
502 522 /* PowerPC 745/755 */
503 523 #define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
504 524 PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
505   -#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
  525 +#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 | \
  526 + PPC_FLAGS_INPUT_6xx)
506 527 /* PowerPC 74xx (aka G4) */
507 528 #define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
508 529 PPC_MEM_TLBSYNC | PPC_TB)
509   -#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
  530 +#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx | \
  531 + PPC_FLAGS_INPUT_6xx)
510 532 /* PowerPC 970 (aka G5) */
511 533 #define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \
512 534 PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \
513 535 PPC_64B | PPC_64_BRIDGE | PPC_SLBI)
514   -#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64B | PPC_FLAGS_EXCP_970)
  536 +#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 | \
  537 + PPC_FLAGS_INPUT_970)
515 538  
516 539 /* Default PowerPC will be 604/970 */
517 540 #define PPC_INSNS_PPC32 PPC_INSNS_604
... ... @@ -1347,6 +1370,17 @@ enum {
1347 1370 PPC405_INPUT_DEBUG = 6,
1348 1371 };
1349 1372  
  1373 +enum {
  1374 + /* PowerPC 970 input pins */
  1375 + PPC970_INPUT_HRESET = 0,
  1376 + PPC970_INPUT_SRESET = 1,
  1377 + PPC970_INPUT_CKSTP = 2,
  1378 + PPC970_INPUT_TBEN = 3,
  1379 + PPC970_INPUT_MCP = 4,
  1380 + PPC970_INPUT_INT = 5,
  1381 + PPC970_INPUT_THINT = 6,
  1382 +};
  1383 +
1350 1384 /* Hardware exceptions definitions */
1351 1385 enum {
1352 1386 /* External hardware exception sources */
... ... @@ -1356,12 +1390,13 @@ enum {
1356 1390 PPC_INTERRUPT_SMI = 3, /* System management interrupt */
1357 1391 PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */
1358 1392 PPC_INTERRUPT_DEBUG = 5, /* External debug exception */
  1393 + PPC_INTERRUPT_THERM = 6, /* Thermal exception */
1359 1394 /* Internal hardware exception sources */
1360   - PPC_INTERRUPT_DECR = 6, /* Decrementer exception */
1361   - PPC_INTERRUPT_HDECR = 7, /* Hypervisor decrementer exception */
1362   - PPC_INTERRUPT_PIT = 8, /* Programmable inteval timer interrupt */
1363   - PPC_INTERRUPT_FIT = 9, /* Fixed interval timer interrupt */
1364   - PPC_INTERRUPT_WDT = 10, /* Watchdog timer interrupt */
  1395 + PPC_INTERRUPT_DECR = 7, /* Decrementer exception */
  1396 + PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */
  1397 + PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */
  1398 + PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */
  1399 + PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */
1365 1400 };
1366 1401  
1367 1402 /*****************************************************************************/
... ...
target-ppc/helper.c
  View file @d0dfae6
... ... @@ -2003,6 +2003,13 @@ void ppc_hw_interrupt (CPUPPCState *env)
2003 2003 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2004 2004 #endif
2005 2005 raised = 1;
  2006 +#if 0 // TODO
  2007 + /* Thermal interrupt */
  2008 + } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
  2009 + env->exception_index = EXCP_970_THRM;
  2010 + env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
  2011 + raised = 1;
  2012 +#endif
2006 2013 }
2007 2014 #if 0 // TODO
2008 2015 /* External debug exception */
... ...
target-ppc/translate_init.c
  View file @d0dfae6
... ... @@ -48,6 +48,7 @@ void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48 48 #endif
49 49 PPC_IRQ_INIT_FN(405);
50 50 PPC_IRQ_INIT_FN(6xx);
  51 +PPC_IRQ_INIT_FN(970);
51 52  
52 53 /* Generic callbacks:
53 54 * do nothing but store/retrieve spr value
... ... @@ -2350,6 +2351,8 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
2350 2351 case CPU_PPC_POWER5: /* Power 5 */
2351 2352 case CPU_PPC_POWER5P: /* Power 5+ */
2352 2353 #endif
  2354 + break;
  2355 +
2353 2356 case CPU_PPC_970: /* PowerPC 970 */
2354 2357 case CPU_PPC_970FX10: /* PowerPC 970 FX */
2355 2358 case CPU_PPC_970FX20:
... ... @@ -2358,12 +2361,41 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
2358 2361 case CPU_PPC_970FX31:
2359 2362 case CPU_PPC_970MP10: /* PowerPC 970 MP */
2360 2363 case CPU_PPC_970MP11:
  2364 + gen_spr_generic(env);
  2365 + gen_spr_ne_601(env);
  2366 + /* XXX: not correct */
  2367 + gen_low_BATs(env);
  2368 + /* Time base */
  2369 + gen_tbl(env);
  2370 + gen_spr_7xx(env);
  2371 + /* Hardware implementation registers */
  2372 + /* XXX : not implemented */
  2373 + spr_register(env, SPR_HID0, "HID0",
  2374 + SPR_NOACCESS, SPR_NOACCESS,
  2375 + &spr_read_generic, &spr_write_generic,
  2376 + 0x00000000);
  2377 + /* XXX : not implemented */
  2378 + spr_register(env, SPR_HID1, "HID1",
  2379 + SPR_NOACCESS, SPR_NOACCESS,
  2380 + &spr_read_generic, &spr_write_generic,
  2381 + 0x00000000);
  2382 + /* XXX : not implemented */
  2383 + spr_register(env, SPR_750_HID2, "HID2",
  2384 + SPR_NOACCESS, SPR_NOACCESS,
  2385 + &spr_read_generic, &spr_write_generic,
  2386 + 0x00000000);
  2387 + /* Allocate hardware IRQ controller */
  2388 + ppc970_irq_init(env);
  2389 + break;
  2390 +
2361 2391 #if defined (TODO)
2362 2392 case CPU_PPC_CELL10: /* Cell family */
2363 2393 case CPU_PPC_CELL20:
2364 2394 case CPU_PPC_CELL30:
2365 2395 case CPU_PPC_CELL31:
2366 2396 #endif
  2397 + break;
  2398 +
2367 2399 #if defined (TODO)
2368 2400 case CPU_PPC_RS64: /* Apache (RS64/A35) */
2369 2401 case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */
... ...